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Crystallization and silicon diffusion nanoscale effects on the electrical properties of Al2O3 based devices
Microelectronic Engineering 86 (2009) 1921–1924
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Crystallization and silicon diffusion nanoscale effects on the electrical properties of Al2O3 based devices M. Lanza a,*, M. Porti a, M. Nafria a, X. Aymerich a, G. Benstetter b, E. Lodermeier b, H. Ranzinger b, G. Jaschke c, S. Teichert c, L. Wilde d, P. Michalowski d a
Dept. Eng. Elect., Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain Elect. Eng. Department, University of Applied Sciences Deggendorf, Edlmaierstrasse 6-8, 94469 Deggendorf, Germany c Qimonda Dresden GmbH & Co. OHG, Königsbrücker Strasse 180, D-01099 Dresden, Germany d Fraunhofer Center Nanoelectronic Technology, Königsbrücker Strasse 180, D-01099 Dresden, Germany b
a r t i c l e
i n f o
Article history: Received 3 March 2009 Accepted 3 March 2009 Available online 10 March 2009
a b s t r a c t In this work, Atomic Force Microscopy (AFM) based techniques are used to study, at the nanoscale, the dependence of the electrical properties of Al2O3 stacks for Flash memories on the percent of diffused Silicon and material crystallization after being annealed at different temperatures. Ó 2009 Elsevier B.V. All rights reserved.
Keywords: Atomic Force Microscope High-k Electrical characterization
1. Introduction The reduction of the dimensions of memory devices based on a polycrystalline silicon floating gate (standard non-volatile memories) and a SiO2 tunnel oxide is accompanied by an increase of the leakage currents, which leads to serious reliability problems [1]. To reduce the excess of currents, the ultra thin SiO2 stacks are being replaced for other high-k materials [2]. However, highk dielectrics still show some drawbacks that must be solved. For this reason, to have a better knowledge of their properties and to improve memory devices performance, an accurate electrical characterization of the tunnel oxide is needed. Most of the knowledge about the electrical behavior of high-k dielectric materials has been gained from measurements performed on fully processed MOS capacitors or transistors [3], using standard electrical characterization methods at wafer level. This kind of tests, however, provides partially averaged information on the electrical properties of the material. On the contrary, Atomic Force Microscope (AFM) based techniques, as demonstrated for SiO2 and other materials in [4–11], are able to characterize the gate dielectric at a nanometer scale, showing properties to which the standard techniques are blind. Since these techniques work on bare (dielectric) surfaces, the conductive tip plays the role of the metal gate of a nanometer sized MOS capacitor with an area of 300 nm2 [12]. When the tip-sample system is polarized, current flows * Corresponding author. Tel.: +34 935813513; fax: +34 935812600. E-mail address: [email protected] (M. Lanza). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.020
through the structure so that the electrical properties of the devices can be evaluated with nanometer resolution. Characterization at the nanoscale allows to study which factors determine the electrical properties of the dielectric stack and details on how they affect to them. For example, AFM related techniques have allowed to study the impact of the annealing temperature and composition on the nanoscale conduction properties of Hf based high-k dielectrics [13]. In this work, AFM is used to investigate, at the nanoscale, the dependence of the electrical behavior of Al2O3 stacks as gate dielectric for Flash memories on the percent of diffused Silicon and on the material crystallization derived from annealing processes at different temperatures (TA), due to its impact on the performance and reliability of memory devices.
2. Experimental The samples consisted of seven groups of a nominal 10 nm thick Al2O3 layer and a 1 nm SiO2 interface layer on top of p-type Silicon substrate. After the Al2O3 deposition, they were annealed by an RTP (Rapid Thermal Process) in nitrogen at different temperatures during 20 s. No gate electrode material was deposited on top, so that the conductive AFM tip can measure directly the electrical properties of the high-k dielectric. The topographical and electrical properties were measured with a Dimension 3100 AFM provided with CAFM (Conductive AFM) and KPFM (Kelvin Probe Force Microscope) modules. The CAFM allows to obtain current images by applying a constant voltage between
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M. Lanza et al. / Microelectronic Engineering 86 (2009) 1921–1924
the tip and the sample during the scan and I–V characteristics on fixed locations by applying ramped voltage tests. On the other hand, the KPFM allows to obtain, simultaneously to the topography, images of the contact potential difference (CPD) between the tip and the substrate. For all the measurements, Si tips with a Pt–Ir coating were used, due to their enough lateral resolution and resistance to wear out. This factor is important when different samples have to be measured under the same conditions (and therefore, with the same tip) to compare their electrical characteristics. The electrons through the stack have been injected from the substrate, by applying negative voltages (tip grounded), in order to avoid surface oxidation. Topographical images have been obtained in tapping mode using Silicon ultra sharps tips without coating, which offer a better spatial resolution.
3. Results We will start analyzing, for each sample, the content of the diffused Silicon into the Al2O3 layer due to the annealing process (an unintentional effect observed during the manufacturing process). To do so, the depth profile has been analyzed by 28Si signal ToFSIMS (Time-of-Flight Secondary Ion Mass Spectrometry). Fig. 1a shows the obtained depth profile, whose magnitude is proportional to the density of Silicon in the material. After 275 s of sputtering, the ToF-SIMS process collected only 28Si isotopes, which means that the substrate has been reached. As can be seen, two regions can be easily recognized in the gate dielectric stack. First of all, there is a region near the surface (from 0 to 50 s) where the density of Silicon decreases with the sputtering time. This was an expected effect because, as other works demonstrated [14], the Al2O3 insulator changes to conductor at the 1 1 0 surface. In the second region, the percent of Silicon increases when getting closer to the Substrate (for all annealing temperatures) until it reaches a maximum at 275 s. The most remarkable result is the dependence of the percent of Silicon on TA. As the graphic shows, the higher annealing temperature, the higher the content of Silicon diffused from the substrate into the Al2O3 stack. The dependence of the crystallization of the high-k dielectric on the annealing temperature has been also investigated. The crystallization of the Al2O3 layer has been analyzed using Grazing Incidence X-ray diffraction (GIXRD). The results show (Fig. 1b) that
the Al2O3 crystallizes at a temperature between 850 °C and 900 °C. AFM topography images further support these results. Topography maps of some stacks have been obtained in tapping mode. In particular, the samples annealed at 750 (Fig. 2a), 975 (Fig. 2b) and 1000 °C were investigated. Fig. 2a and b indicates an increase of the surface roughness after crystallization. Finally, before the electrical characterization, the physical thickness of the different layers was also determined with X-ray reflectometry. The thicknesses are shown in Table 1, columns 2 and 3, which will be correlated to the data obtained from current images. The electrical conduction of the different samples has been analyzed by measuring I–V curves at different positions of the stacks. Fig. 3 shows the statistical distribution of the onset voltages (minimum voltage needed to measure current above the noise level) and Table 1 (columns 4 and 5) shows their statistical parameters (mean and rms values). From both, Fig. 3 and Table 1, it can be determined that the samples show three different electrical behaviors, depending on the annealing temperature. The first group corresponds to amorphous samples (TA 6 850 °C), the second one is formed of crystalline samples (TA P 925 °C) and the third one corresponds to the sample annealed at 900 °C, which exhibits unique properties. Amorphous samples show a smaller deviation than crystalline structures, indicating that amorphous samples are more homogenous, due to the inexistence of poly-crystals. The sample annealed at 900 °C exhibits a particular electrical behavior: as columns 2 and 3 in Table 1 shows, on the one hand, a large decrease of the physical Al2O3 thickness is observed between 850 °C and 900 °C and, on the other, an increase of the physical SiO2 thickness is measured between 900 °C and 925 °C. This means that the 900 °C annealed sample has the smallest equivalent oxide thickness (column 6) and, therefore, the highest conductivity. Except for the sample annealed at 900 °C, it can be observed that, for both, the crystalline and the amorphous samples, a higher annealing temperature results in a smaller mean value (larger conductivity) and a higher deviation of the onset voltage (larger inhomogeneity). Generally, the annealing process is used to eliminate defects in the dielectric and improve its performance but, in this case, the increase of the conductivity for larger TA could be explained from the increase of the amount of Silicon. The Si atoms could act as tunneling centers that lead to an increase of the tunneling current. These results are supported by the current images obtained on the different annealed samples. The current images have been ob-
Fig. 1. 28Si ToF-SIMS depth profile for Al2O3 stacks (a) and GIXRD data (b). They have allowed to determine, respectively, the percent of diffused silicon and the crystallization of the stacks, for all annealing temperatures.
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M. Lanza et al. / Microelectronic Engineering 86 (2009) 1921–1924
tained by applying the same voltage to all the structures. Once more, the three electrical behaviors can be distinguished. Fig. 2c
and d shows, as example, current images of the samples annealed at 750 °C and 975 °C when the scan voltage was 10.25 V in both
Fig. 2. Topographic (a, b), Current (c, d) and KPFM (e, f) maps of Al2O3 stacks annealed at 750 °C (left column) and 975 °C (right column). The table shows their mean and rms values. Images a and b are 150 150 nm2 and the rest are 500 500 nm2. Table 1 Experimental and theoretical values of some magnitudes of the analyzed samples, as a function of the annealing temperature. Annealing temperature (°C)
Physical Al2O3 thickness (nm)
Physical SiO2 thickness (nm)
Mean value of the onset voltage (V)
Deviation of the onset voltage (V)
Total equivalent oxide thickness (nm)
Deviation of the CPD signal (mV)
750 850 900 925 950 975 1000
14.6 14.6 12.6 12.4 12.4 12.0 12.3
1.0 1.0 0.9 1.1 1.2 – 1.1
13.5 12.7 12.4 13.7 13.4 12.9 12.6
0.12 0.20 0.44 0.28 0.32 0.47 0.46
7.31 7.29 6.32 6.50 6.58 6.49
6.12 6.04 6.77 7.05 7.73 7.02 6.59
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M. Lanza et al. / Microelectronic Engineering 86 (2009) 1921–1924
annealing at different temperatures. I–V curves and current images show that the conductivity of amorphous samples (TA < 900 °C) is more homogeneous than that of crystalline ones. In addition, for each group of samples (amorphous and crystalline) separately, it has been observed that the higher annealing temperature (or Silicon content), the smaller the homogeneity and the higher the electrical conductivity, which have been associated to the larger Si content. CPD images show a more inhomogeneous distribution of trapping sites in the stack after crystallization. Therefore, crystallization and Si content (which depend on the annealing temperature) strongly contribute to the inhomogeneity increase of the conduction and trapping properties of the stacks. Acknowledgements Fig. 3. Statistical distribution of the onset voltage obtained from the I–V curves measured at several locations on samples annealed at different temperatures.
cases. The uniform current distribution observed for amorphous samples (Fig. 2c) and its roughness analysis (table in Fig. 2) conclude to the higher homogeneity compared to the crystalline structures (Fig. 2d). The sample annealed at 900 °C (not shown) exhibits an inhomogeneous current distribution and a higher conductivity. The structures whose current images are shown in Fig. 2c and d have been also analyzed with KPFM (Fig. 2e and f), which can provide information about the presence of charge and trapping centers in the stack. Table 1, last column, shows the deviation obtained from the CPD images of each of the investigated structures. The results do not show a progressive increase of the rms value of CPD images with the annealing temperature (and, therefore, the diffused Si content), but a sudden increase around the crystallization temperature. Therefore, the charge observed from KPFM images could be related to some kind of defects or trapping sites generated after the crystallization (instead of those related to the diffusion of Si), maybe around the grain boundaries, which could also enhance the non-inhomogeneity observed in current images. 4. Conclusion The electrical properties of Al2O3 stacks have been studied at nanometer scale using CAFM and KPFM to analyze the impact of
This work has been partially supported by the Spanish MICINN (TEC2007-61294/MIC research project and HA2007-0029 Integrated Action), the DURSI of the Generalitat de Catalunya (2005SGR-00061) and ‘‘La Caixa + Deutscher Akademischer Austausch Dienst (DAAD)” pre-doctoral fellowships. References [1] A. Padovani, L. Larcher, S. Verma, P. Pavan, P. Majhi, P. Kapur, K. Parat, G. Bersuker, K. Saraswat, Proc. ULIS (2008) 111–114. [2] F. Irrera, Microelectron. Reliab. 41 (11) (2001) 1809–1813. [3] W.J. Zhu, T.P. Ma, T. Tamagawa, J. Kim, Y. Di, IEEE Electron Device Lett. 23 (2002) 97–99. [4] W. Polspoel, W. Vandervorst, Microelectron. Eng. 84 (3) (2007) 495–500. [5] W. Frammelsberger, G. Benstetter, J. Kiely, R. Stamp, Appl. Surf. Sci. 252 (6) (2006) 2375–2388. [6] M. Porti, M. Nafría, X. Aymerich, IEEE Trans. Nanotech. 3 (1) (2004) 55–60. [7] SD. Wang, MN. Chang, CY. Chen, TF. Ley, Electrochem. Solid State Lett. 8 (9) (2005) G233–G236. [8] C. Sire, S. Blonkowski, MJ. Gordon, T. Baron, Appl. Phys. Lett. 91 (24) (2007) 242905. [9] YL. Wu, ST. Lin, CP. Lee, IEEE Trans. Device Mat. Reliab. 8 (2) (2008) 352–357. [10] A. Paskaleva, V. Yanev, M. Rommel, M. Lemberger, AJ. Bauer, J. Appl. Phys. 104 (2) (2008) 024108. [11] E. Efthymiou, S. Bernardini, S.N. Volkos, B. Hamilton, J.F. Zhang, H.J. Uppal, A.R. Peaker, Microelectron. Eng. 84 (9–10) (2007) 2290–2293. [12] M. Porti, M. Nafría, X. Aymerich, IEEE Trans. Electron Device 50 (4) (2003) 933– 940. [13] M. Lanza, M. Porti, M. Nafría, G. Benstetter, W. Frammelsberger, E. Lodermeier, H. Ranzinger, G. Jaschke, Microelectron. Reliab. 47 (2007) 1424–1428. [14] H. Pinto, R.M. Nieminen, S.D. Elliott, Phys. Rev. B 70 (2004) 125402-1–12540211.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Crystallization and silicon diffusion nanoscale effects on the electrical properties of Al2O3 based devices M. Lanza a,*, M. Porti a, M. Nafria a, X. Aymerich a, G. Benstetter b, E. Lodermeier b, H. Ranzinger b, G. Jaschke c, S. Teichert c, L. Wilde d, P. Michalowski d a
Dept. Eng. Elect., Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain Elect. Eng. Department, University of Applied Sciences Deggendorf, Edlmaierstrasse 6-8, 94469 Deggendorf, Germany c Qimonda Dresden GmbH & Co. OHG, Königsbrücker Strasse 180, D-01099 Dresden, Germany d Fraunhofer Center Nanoelectronic Technology, Königsbrücker Strasse 180, D-01099 Dresden, Germany b
a r t i c l e
i n f o
Article history: Received 3 March 2009 Accepted 3 March 2009 Available online 10 March 2009
a b s t r a c t In this work, Atomic Force Microscopy (AFM) based techniques are used to study, at the nanoscale, the dependence of the electrical properties of Al2O3 stacks for Flash memories on the percent of diffused Silicon and material crystallization after being annealed at different temperatures. Ó 2009 Elsevier B.V. All rights reserved.
Keywords: Atomic Force Microscope High-k Electrical characterization
1. Introduction The reduction of the dimensions of memory devices based on a polycrystalline silicon floating gate (standard non-volatile memories) and a SiO2 tunnel oxide is accompanied by an increase of the leakage currents, which leads to serious reliability problems [1]. To reduce the excess of currents, the ultra thin SiO2 stacks are being replaced for other high-k materials [2]. However, highk dielectrics still show some drawbacks that must be solved. For this reason, to have a better knowledge of their properties and to improve memory devices performance, an accurate electrical characterization of the tunnel oxide is needed. Most of the knowledge about the electrical behavior of high-k dielectric materials has been gained from measurements performed on fully processed MOS capacitors or transistors [3], using standard electrical characterization methods at wafer level. This kind of tests, however, provides partially averaged information on the electrical properties of the material. On the contrary, Atomic Force Microscope (AFM) based techniques, as demonstrated for SiO2 and other materials in [4–11], are able to characterize the gate dielectric at a nanometer scale, showing properties to which the standard techniques are blind. Since these techniques work on bare (dielectric) surfaces, the conductive tip plays the role of the metal gate of a nanometer sized MOS capacitor with an area of 300 nm2 [12]. When the tip-sample system is polarized, current flows * Corresponding author. Tel.: +34 935813513; fax: +34 935812600. E-mail address: [email protected] (M. Lanza). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.020
through the structure so that the electrical properties of the devices can be evaluated with nanometer resolution. Characterization at the nanoscale allows to study which factors determine the electrical properties of the dielectric stack and details on how they affect to them. For example, AFM related techniques have allowed to study the impact of the annealing temperature and composition on the nanoscale conduction properties of Hf based high-k dielectrics [13]. In this work, AFM is used to investigate, at the nanoscale, the dependence of the electrical behavior of Al2O3 stacks as gate dielectric for Flash memories on the percent of diffused Silicon and on the material crystallization derived from annealing processes at different temperatures (TA), due to its impact on the performance and reliability of memory devices.
2. Experimental The samples consisted of seven groups of a nominal 10 nm thick Al2O3 layer and a 1 nm SiO2 interface layer on top of p-type Silicon substrate. After the Al2O3 deposition, they were annealed by an RTP (Rapid Thermal Process) in nitrogen at different temperatures during 20 s. No gate electrode material was deposited on top, so that the conductive AFM tip can measure directly the electrical properties of the high-k dielectric. The topographical and electrical properties were measured with a Dimension 3100 AFM provided with CAFM (Conductive AFM) and KPFM (Kelvin Probe Force Microscope) modules. The CAFM allows to obtain current images by applying a constant voltage between
1922
M. Lanza et al. / Microelectronic Engineering 86 (2009) 1921–1924
the tip and the sample during the scan and I–V characteristics on fixed locations by applying ramped voltage tests. On the other hand, the KPFM allows to obtain, simultaneously to the topography, images of the contact potential difference (CPD) between the tip and the substrate. For all the measurements, Si tips with a Pt–Ir coating were used, due to their enough lateral resolution and resistance to wear out. This factor is important when different samples have to be measured under the same conditions (and therefore, with the same tip) to compare their electrical characteristics. The electrons through the stack have been injected from the substrate, by applying negative voltages (tip grounded), in order to avoid surface oxidation. Topographical images have been obtained in tapping mode using Silicon ultra sharps tips without coating, which offer a better spatial resolution.
3. Results We will start analyzing, for each sample, the content of the diffused Silicon into the Al2O3 layer due to the annealing process (an unintentional effect observed during the manufacturing process). To do so, the depth profile has been analyzed by 28Si signal ToFSIMS (Time-of-Flight Secondary Ion Mass Spectrometry). Fig. 1a shows the obtained depth profile, whose magnitude is proportional to the density of Silicon in the material. After 275 s of sputtering, the ToF-SIMS process collected only 28Si isotopes, which means that the substrate has been reached. As can be seen, two regions can be easily recognized in the gate dielectric stack. First of all, there is a region near the surface (from 0 to 50 s) where the density of Silicon decreases with the sputtering time. This was an expected effect because, as other works demonstrated [14], the Al2O3 insulator changes to conductor at the 1 1 0 surface. In the second region, the percent of Silicon increases when getting closer to the Substrate (for all annealing temperatures) until it reaches a maximum at 275 s. The most remarkable result is the dependence of the percent of Silicon on TA. As the graphic shows, the higher annealing temperature, the higher the content of Silicon diffused from the substrate into the Al2O3 stack. The dependence of the crystallization of the high-k dielectric on the annealing temperature has been also investigated. The crystallization of the Al2O3 layer has been analyzed using Grazing Incidence X-ray diffraction (GIXRD). The results show (Fig. 1b) that
the Al2O3 crystallizes at a temperature between 850 °C and 900 °C. AFM topography images further support these results. Topography maps of some stacks have been obtained in tapping mode. In particular, the samples annealed at 750 (Fig. 2a), 975 (Fig. 2b) and 1000 °C were investigated. Fig. 2a and b indicates an increase of the surface roughness after crystallization. Finally, before the electrical characterization, the physical thickness of the different layers was also determined with X-ray reflectometry. The thicknesses are shown in Table 1, columns 2 and 3, which will be correlated to the data obtained from current images. The electrical conduction of the different samples has been analyzed by measuring I–V curves at different positions of the stacks. Fig. 3 shows the statistical distribution of the onset voltages (minimum voltage needed to measure current above the noise level) and Table 1 (columns 4 and 5) shows their statistical parameters (mean and rms values). From both, Fig. 3 and Table 1, it can be determined that the samples show three different electrical behaviors, depending on the annealing temperature. The first group corresponds to amorphous samples (TA 6 850 °C), the second one is formed of crystalline samples (TA P 925 °C) and the third one corresponds to the sample annealed at 900 °C, which exhibits unique properties. Amorphous samples show a smaller deviation than crystalline structures, indicating that amorphous samples are more homogenous, due to the inexistence of poly-crystals. The sample annealed at 900 °C exhibits a particular electrical behavior: as columns 2 and 3 in Table 1 shows, on the one hand, a large decrease of the physical Al2O3 thickness is observed between 850 °C and 900 °C and, on the other, an increase of the physical SiO2 thickness is measured between 900 °C and 925 °C. This means that the 900 °C annealed sample has the smallest equivalent oxide thickness (column 6) and, therefore, the highest conductivity. Except for the sample annealed at 900 °C, it can be observed that, for both, the crystalline and the amorphous samples, a higher annealing temperature results in a smaller mean value (larger conductivity) and a higher deviation of the onset voltage (larger inhomogeneity). Generally, the annealing process is used to eliminate defects in the dielectric and improve its performance but, in this case, the increase of the conductivity for larger TA could be explained from the increase of the amount of Silicon. The Si atoms could act as tunneling centers that lead to an increase of the tunneling current. These results are supported by the current images obtained on the different annealed samples. The current images have been ob-
Fig. 1. 28Si ToF-SIMS depth profile for Al2O3 stacks (a) and GIXRD data (b). They have allowed to determine, respectively, the percent of diffused silicon and the crystallization of the stacks, for all annealing temperatures.
1923
M. Lanza et al. / Microelectronic Engineering 86 (2009) 1921–1924
tained by applying the same voltage to all the structures. Once more, the three electrical behaviors can be distinguished. Fig. 2c
and d shows, as example, current images of the samples annealed at 750 °C and 975 °C when the scan voltage was 10.25 V in both
Fig. 2. Topographic (a, b), Current (c, d) and KPFM (e, f) maps of Al2O3 stacks annealed at 750 °C (left column) and 975 °C (right column). The table shows their mean and rms values. Images a and b are 150 150 nm2 and the rest are 500 500 nm2. Table 1 Experimental and theoretical values of some magnitudes of the analyzed samples, as a function of the annealing temperature. Annealing temperature (°C)
Physical Al2O3 thickness (nm)
Physical SiO2 thickness (nm)
Mean value of the onset voltage (V)
Deviation of the onset voltage (V)
Total equivalent oxide thickness (nm)
Deviation of the CPD signal (mV)
750 850 900 925 950 975 1000
14.6 14.6 12.6 12.4 12.4 12.0 12.3
1.0 1.0 0.9 1.1 1.2 – 1.1
13.5 12.7 12.4 13.7 13.4 12.9 12.6
0.12 0.20 0.44 0.28 0.32 0.47 0.46
7.31 7.29 6.32 6.50 6.58 6.49
6.12 6.04 6.77 7.05 7.73 7.02 6.59
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annealing at different temperatures. I–V curves and current images show that the conductivity of amorphous samples (TA < 900 °C) is more homogeneous than that of crystalline ones. In addition, for each group of samples (amorphous and crystalline) separately, it has been observed that the higher annealing temperature (or Silicon content), the smaller the homogeneity and the higher the electrical conductivity, which have been associated to the larger Si content. CPD images show a more inhomogeneous distribution of trapping sites in the stack after crystallization. Therefore, crystallization and Si content (which depend on the annealing temperature) strongly contribute to the inhomogeneity increase of the conduction and trapping properties of the stacks. Acknowledgements Fig. 3. Statistical distribution of the onset voltage obtained from the I–V curves measured at several locations on samples annealed at different temperatures.
cases. The uniform current distribution observed for amorphous samples (Fig. 2c) and its roughness analysis (table in Fig. 2) conclude to the higher homogeneity compared to the crystalline structures (Fig. 2d). The sample annealed at 900 °C (not shown) exhibits an inhomogeneous current distribution and a higher conductivity. The structures whose current images are shown in Fig. 2c and d have been also analyzed with KPFM (Fig. 2e and f), which can provide information about the presence of charge and trapping centers in the stack. Table 1, last column, shows the deviation obtained from the CPD images of each of the investigated structures. The results do not show a progressive increase of the rms value of CPD images with the annealing temperature (and, therefore, the diffused Si content), but a sudden increase around the crystallization temperature. Therefore, the charge observed from KPFM images could be related to some kind of defects or trapping sites generated after the crystallization (instead of those related to the diffusion of Si), maybe around the grain boundaries, which could also enhance the non-inhomogeneity observed in current images. 4. Conclusion The electrical properties of Al2O3 stacks have been studied at nanometer scale using CAFM and KPFM to analyze the impact of
This work has been partially supported by the Spanish MICINN (TEC2007-61294/MIC research project and HA2007-0029 Integrated Action), the DURSI of the Generalitat de Catalunya (2005SGR-00061) and ‘‘La Caixa + Deutscher Akademischer Austausch Dienst (DAAD)” pre-doctoral fellowships. References [1] A. Padovani, L. Larcher, S. Verma, P. Pavan, P. Majhi, P. Kapur, K. Parat, G. Bersuker, K. Saraswat, Proc. ULIS (2008) 111–114. [2] F. Irrera, Microelectron. Reliab. 41 (11) (2001) 1809–1813. [3] W.J. Zhu, T.P. Ma, T. Tamagawa, J. Kim, Y. Di, IEEE Electron Device Lett. 23 (2002) 97–99. [4] W. Polspoel, W. Vandervorst, Microelectron. Eng. 84 (3) (2007) 495–500. [5] W. Frammelsberger, G. Benstetter, J. Kiely, R. Stamp, Appl. Surf. Sci. 252 (6) (2006) 2375–2388. [6] M. Porti, M. Nafría, X. Aymerich, IEEE Trans. Nanotech. 3 (1) (2004) 55–60. [7] SD. Wang, MN. Chang, CY. Chen, TF. Ley, Electrochem. Solid State Lett. 8 (9) (2005) G233–G236. [8] C. Sire, S. Blonkowski, MJ. Gordon, T. Baron, Appl. Phys. Lett. 91 (24) (2007) 242905. [9] YL. Wu, ST. Lin, CP. Lee, IEEE Trans. Device Mat. Reliab. 8 (2) (2008) 352–357. [10] A. Paskaleva, V. Yanev, M. Rommel, M. Lemberger, AJ. Bauer, J. Appl. Phys. 104 (2) (2008) 024108. [11] E. Efthymiou, S. Bernardini, S.N. Volkos, B. Hamilton, J.F. Zhang, H.J. Uppal, A.R. Peaker, Microelectron. Eng. 84 (9–10) (2007) 2290–2293. [12] M. Porti, M. Nafría, X. Aymerich, IEEE Trans. Electron Device 50 (4) (2003) 933– 940. [13] M. Lanza, M. Porti, M. Nafría, G. Benstetter, W. Frammelsberger, E. Lodermeier, H. Ranzinger, G. Jaschke, Microelectron. Reliab. 47 (2007) 1424–1428. [14] H. Pinto, R.M. Nieminen, S.D. Elliott, Phys. Rev. B 70 (2004) 125402-1–12540211.