a-Si Heterostructure

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ScienceDirect Materials Today: Proceedings 5 (2018) 9790–9797

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IC-FNM 2016

Current Controlled Switching in Si/PS/a-Si Heterostructure Sudipta Chakrabartya,*, Sourav Mandalb, Ujjwal Ghantac, Jayoti Dasd, and Syed Minhaz Hossaina a

Department of Physics, IIEST, Shibpur, Howrah-711103, India Centre of Excellence for Green Energy and Sensor Systems, IIEST, Shibpur, Howrah-711103, India c School of Materials Science & Engineering, IIEST, Shibpur, Howrah-711103, India d Department of Physics, Jadavpur University, Kolkata-700 032, India b

Abstract

Current controlled switching has been observed in p-type crystalline Silicon (p-c-Si)/porous Si (PS)/n-type hydrogenated amorphous Silicon (n-a-Si:H) heterostructure. Mechanism of the switching is proposed consideringpresence of trapped carriers at the silicon nanocrystal-SiOx interface. A part of the trapped charges are considered to be bound near the n-a-Si:H/PS and PS/p-c-Si interface forming an additional coulomb barrier for the majority carriers. It is assumed that during the flow of current through the PS layer, the captured carriers get detrapped by impact-excitation leading to breaking of the barrier after certain threshold value resulting in the switching. This model matches well with the experimental results. © 2017 Elsevier Ltd. All rights reserved. Selection and/or Peer-review under responsibility of International Conference on Functional Nano-Materials, 2016. Keywords:Switching; interface; porous silicon; amorphous silicon.

1. Introduction Porous Silicon has received great attention in last two decades as an optoelectronic material due to its strongvisible light emitting property under UV excitation[1].Charge transport as well as electroluminescence properties of porous silicon(PS) has alsobeen studied but not so much as its photoluminescence (PL)

* Corresponding author. Tel.: 9674512905,8900108456. E-mail address:[email protected] 2214-7853© 2017 Elsevier Ltd. All rights reserved. Selection and/or Peer-review under responsibility of International Conference on Functional Nano-Materials, 2016.

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properties[2,3].Porous silicon is a complex sponge like nanostructure containing oxidized silicon nanocrystals and voids having large surface to volume ratio [2]. Due to this large surface area there exists a large number of surface defects states and dangling bonds where charge carriers may easily get trapped. Hysteresis in I-V characteristics of PS has been observedand trapped charges in the PS layer have been considered responsible for this observation [3]. Recent studies show resistive switching in systems like porous silicon oxide[4] and PSZnOnanocomposite[5].Currentlyworks of U. Ghanta et.al. shows resistive switching behavior in isolated nanocrystalline silicon[6] as well as in complex network of porous silicon quantum rods[7]. Resistive switching devices are also of interest due to ultrafast switching action, good memory characteristics with low power consumption[8,9].These devices are suitable for fabrication of non-volatile random access memories (RAM, also named as RRAM or ReRAM)[10].However, studies on switching action in porous silicon has not been explored largely. In this study, a device has been fabricated with PS layer sandwiched between a p-Si substrate and n type amorphous silicon layer grown by PECVD.Al and Ag have been deposited by thermal evaporationon the p and n side of the device respectively for making ohmic contacts. I-V characteristics of the device have been studied and reported in this paper. A sharp current controlled switching is observed in the I-V plot under forward bias. This switching is interpreted on the basis of existence of trapped charges at the Si-nc-oxide interface present in the PS layer. A part of the trapped charges are considered to be polarized at the a-Si:H/Ag and Si/PS interface as reported for switching in ZnOnano wire [11].With increasing current through the PS layer, the trapped charges gradually get detrapped and above a threshold current (Ith), all the trapped charge carriers including the polarized ones becomes free overcoming coulomb barrier leading to sharp increase in conductance of the PS layer. A model is proposed on the basis of this mechanism and the result is very similar to the experimentally obtained ones. Nomenclature PS PL a-Si PECVD HRS LRS

porous silicon Photoluminescence amorphous silicon plasma enhanced chemical Vapour deposition high resistance state low resistance state

2. Experimental details The device is fabricated in three steps. At first,PS layer is synthesized on polished p-type Silicon substrate (100) of resistivity 8 Ohm-cm by electrochemical etching in HF-ethanol (1:1) electrolyte after depositing Al on the back side by standard process described elsewhere [12,13,14]. Etching time, current density and HF concentration were 5 minutes, 20 mA/cm2 and24% respectively producing a PS layer of 4.0µm thickness and 60% porosity[14]. After preparation, PL spectrum of the PS layer have been recorded byAvantes (Avaspec-3648) spectrometer using405nm diode laser (with 10mW intensity) excitation. Then a 30 nm thick n-type hydrogenated amorphous silicon (n-a-Si:H) layer (with band gap of 1.74 eV) have been deposited by PECVD system over the PS layer with a gas mixture of 1% phosphine in Silane and H2. The doping concentration of the n-a-Si:H was 1.72×1017/cm3. An Ag layer of thickness of 3nm is grown on the n-a-Si:H layer creating an ohmic contactwith the n-type aSi.300 nm thick aluminium layers with diameter~1mmhas beendeposited at various positions on the Ag layer for probing during I-V measurements.Current-voltage characteristics of the device have been recorded using HPsource-meter (Agilent-U3606A) in the range of 0V to 1.8V with a step of 5mV. In the reverse bias, the sample current was ~mAwhere as in the forward bias the current was ~10 mA. Structure and surface morphology of the PS layer have been studied using AFM (Veeco DI CP II). Phase contrast AFM has been employed to have an idea about the different phases present in the PS layer.

Chakrabarty et al. / Materials Today: Proceedings 5 (2018) 9790–9797

Fig. 1.3D plot of AFM topographof porous Si layer with inset (a)showingAFM topograph of oxide surrounded Core nano-structure.

900 800

Intensity (a. u.)

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700 600 500 400 300 200 100 400

500

600

700

800

Wavelength (nm) Fig. 2. PL spectrum of the porous Si layer

900

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3. Results and discussions Fig. 1 shows the AFM topograph of the PS layer indicating presence of randomly distributed columnar nanostructure of silicon. The phase contrast AFM topography (inset-(a) of Fig. 1) shows that a dark core is surrounded by a bright annular region.Phase imaging AFM maps the stiffness variation of the sample surfaceto distinguish different phases with different elastic moduli as the stiffer region appears brighter here[15].From the existence of two distinct phases, it is evident that the core nanostructure is surrounded by oxide shell [16, 17].

Resistance (Ohm)

Fig. 2 is the recorded PL spectrum showing peak at 604nm that gives an estimate of 2.05eV for the optical band gap of the PS layer used in the device. HRS

(b)

65 60 55 50

LRS

45 40

8

10

12

14

16

18

Ith Current (mA)

20

22

2.0E-02

(a)

1.8E-02 1.6E-02

1E-3

Current (A)

Current (A)

0.01

70

1.4E-02 1.2E-02 1.0E-02 8.0E-03 6.0E-03

1E-4

4.0E-03 0.6

0.7

0.8

0.9

1.0

1.1

Voltage (v)

-1.6 -1.2 -0.8 -0.4 0.0

0.4

0.8

1.2

1.6

2.0

Voltage (V) Fig. 3. I-V characteristics with both forward and reverse scan with (a) close view on switching region in I-V plot and (b) Resistance vsCurrent characteristics showing change of resistance during switching

Fig. 3 shows the cyclic I-V curve obtained at room temperature ofthe device. The rectifying nature is evident from the asymmetry of the curve. The most salient characteristic is the exhibition of a sharp rise in the current at voltage ~0.95V during forward scan from 0 to1.8V and a sharp dip at 0.78V during reverse scan, forming a loop as shown in the inset-(a) of Fig. 3. It is notable that both forward and reverse switching occurs at same current value of 10.8 mA for this device.The inset-(b) of Fig. 3 is a plot of resistance versus current that shows the discontinuity between a high resistance state(HRS) to a lower resistance state(LRS) near the switching region. Theresistance decreases sharply from 66Ω (HRS) to 45Ω (LRS) showing the resistive nature of the observed current controlled switching.

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Switching in amorphous silicon based devices is an already known phenomenon and has been reported previously by many authors[18, 19, 20]where the formation of metal filament in the amorphous layer is considered to be responsible for switching. This mechanism cannot play the dominant role for switching in our device as the pSi wafer and the a-Si layer are separated by a thick (4.0 ) PS layer through which metal filament cannot develop. The mechanism of this switching phenomenon is explained on the basis of trapped charges at the interface of nanocrystalline core and oxide shellin the PS layer[11]. The schematicstructure of the device is shown in Fig. 4 where the resistive p-type PS layeris sandwiched between the p-Si Substrate and the n-type amorphous silicon layer.Energy band diagram of the device (shown in Fig. 4) is very similar to that of a p-i-n hetero junction[21,22]. In this case the porous Si layer with higher resistivity in between p-type Si substrate and n-type a-Si behaves like intrinsic region. The difference of normal i layer and PS lies in the fact that the PS layer is constituted of a composite of silicon quantum rods surrounded by non-stoichiometric oxide and voids[2, 23]. The interface of the Sinc core and the oxide shell acts as electron and hole traps as calculated by M.V. Wolkinet.al.[24]. We think these traps play crucial role in the switching phenomenon. These traps are likely to be distributed randomly throughout the PS layer. But near the depletion layers due to the presence of immobile charges, the trapped carriers in the Si quantum rods are likely to get polarized (as shown in Fig.4) leading to an effective increase in the barrier height ( ) for the flow of majority carriers. During forward bias, as electrons are injected from n-type a-Si to porous Si, it is likely that the loosely trapped charges get de-trapped through impact excitation[25] and take part in conduction process leading to decrease in resistance of the PS layer. The polar charges remain bound at the interface until a threshold current flows through the device. Above threshold current the extra barrier breaks down due to impact excitation of almost all of the polarized bound charges resulting in a suddendecrease in resistance and consequently increase incurrent.

PS

p-Si

Al

a-Si

Ag

e

Ec

e e

Ev

EF

h

h

Al

Ec

p-Si

PS

Fig. 4. Energyband diagram and schematic structure of the device

Ev

a-Si

Ag

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The I-V characteristics of an ideal diode is given by the Schokley’s equation derived on the assumption that the applied voltage appears completely across the transition region[26]. But in this device, a PS layer with higher resistivity is inserted between p and n layer. So the diode equation is modified as, =

[

− 1](1)

where is the voltage applied, is the resistance of the PS layer and is the ideality factor. The effective carrier concentration of the PS layer is lowered because of trapping of chargecarriersat the oxide related defect states. Assuming impact excitation of the loosely bound carriers at the shallow traps with increasing flow of majority carriers through the device below a certain threshold current ,the resistance can be expressed as a function of current. Denoting the ratio of initial concentration of trapped carriers to the concentration of maximum possible free =

carriers by

[1 +

=

where, =

, we can express the resistance of the PS layer as 1−

]

(2)

is the minimum resistance of the PS layer after switching. Using (2) in (1) we get, 0 [1+

[

1−

ℎ

]

− 1](3)

as the modified diode equation for the device.

So the voltage-current relation becomes =

ln 1 +

+

[1 +

1−

]

(4)

Due to the presence of relatively tightly bound polarized trapped charges near the two interfaces between PS/a-Si and p-Si/PS there will be an additional coulomb potential barrier against the flow of majority carriers. This extra potential vanishes when the current reaches the threshold.This is evident from the discontinuity in current value as shown in the I-V characteristics(Fig. 3). So the potential can be considered as a step function that takes a positive value before switching and goes to zero after switching. Hyperbolic tangent function is a versatile function that is widely used to describe transition between two states. The sharpness of transition can easily be modelled simply by introducing a parameter. This function is widely used in physical systems showing phase transition like in ferromagnetic or Ising systems[27, 28]. It is also used in modelling neural network as activation function[29].So, the potential barrier can be modeled using hyperbolic tangent function as =

2

[1 − tanh

−

whichgoes sharply to zero at = characteristics given as, V =

+

ln 1 +

(5)

]

for suitable high values of . Adding this barrier potential, we get the V-I

+

[1 +

1−

]

for I <

(6)

the trapped electrons will be de-trapped and all the polarized charges near the interface At the threshold current in will be free leading to minimum resistanceof the PS layer. This is due to the fact that the contribution of will vanish at threshold (eqn.(2)). Hence, the expression for the voltage above threshold current becomes

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V =

ln

+

for I ≥

(7)

A plot of combined equations (6) and (7) is shown in Fig. 5(a) Corresponding experimental result is shown in =10.8 mA , = − = 0.14 and = 45Ω. Fig.5(b) showing a nice agreement with the model for

Current (mA)

21 R

V

Theoretical

14

th

F

V

th

Ith

10.8 7 0

(a)

Current (mA)

21

Experimental 14

Ith

10.8 7

(b)

0 0.0

0.3

0.6

0.81 0.9 0.95

1.2

1.5

Voltage (V) Fig. 5. Comparison between I-V characteristic obtained theoretically and experimentally

4. Conclusion Porous Si is synthesized on p-type Si wafer. The PS layer is sandwiched between n-type a-Si layer and p-Si substrate. Ag layer on the n-side and Al layer on the p-side have been deposited to form a p-i-n like device structure. I-V characteristic of the device shows expected rectifying property along with a sharp current controlled switching phenomenon in the forward bias. To explain the switching action a model is proposed on the assumption that the PS layer captures a fraction of free carriers at the Si-nc/SiOx interface. A part of the trapped carriers get polarized and offers an additional potential barrier to the flow of majority carrier. The captured carriers get de-trapped by impactexcitation, leading to the breaking of the barrier after certain threshold current value resulting in the switching. The prediction of this model matches well with the experimental results. The device has the potential to be used as a current controlled switch. As the switching occurs at very low voltages,it will be suitable for low power consuming RAM devices. However,further studies are needed to verify the assumed

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model microscopically. Also, more variation in the experimental parameters are needed to have better control over the switching voltage, current and relative change in resistance before and after switching. Acknowledgements One of the authors, SouravMandal acknowledges University Grant Commission (UGC) for financial support. References [1]L. T. Canham, Appl. Phys. Lett., 57(10) (1990) 1046. [2] O. Bisia , S Ossicini , L. Pavesi,Surface Science Reports 38 (2000) 1-126 [3] G. Korotcenkov,Porous Silicon: From Formation to Application: Formation and Properties, Volume One: Formation and Properties, CRC Press,USA, 2016,pp.403 [4]T-M Tsai, K-C Chang, R Zhang, T-C Chang, J. C. Lou, J-H Chen, T-F Young, B-H Tseng, C-C Shih, Y-C Pan, , M-C Chen, J-H Pan, Y-E Syu and S M. Sze, App. Phys. Lett.102, (2013) 253509 [5]L. Martínez, O.Ocampo, Y. Kumar and V. Agarwal,Nanoscale Research Letters 9 (2014) 437 [6] U. Ghanta, S. Singh, M. Ray, N. R. bandyopadhyay, S. M. Hossain, Nanotechnology 27 (2016) 455702 [7] U. Ghanta, S. Singh, M. Ray, N. R. bandyopadhyay, G. Sambandamurthy, S. M. Hossain, in course of publicat1ion (2016) [8] F. Zhou, Y. F. Chang, B. Fowler, K. Byun, and J. C. Lee, App. Phys. Lett. 106 (2015) 063508. [9] Y. F. Chang, B. Fowler, Y. C. Chen, Y.T. Chen, Y. Wang, F. Xue, F. Zhou, and J. C. Lee , J. Appl. Phys. 116 (2014) 043709 [10] Akihito Sawa,Mater. Today 11 (2008) 28–36 [11] K.R.G.Karthik, R. R. Prabhakar, L. Hai, S. K. batabyal, Y. Z. Huang, S. G. Mhaisalkar, Appl. Phys. Lett. 103 (2013) 123114 [12]S. M. Hossain,J. Das, S. Chakraborty, S. K. Dutta, and H. Saha, Semicond. Sci. Technol., vol. 17, no. 1, pp. 55–59, Jan. 2002 [13]S. K. Dutta, S. M. Hossain, S.Chakraborty, H.Saha, physica status solidi (a) 191 (2) (2002) 535-547 [14]S. M. Hossain, J. Das, S. K. Dutta, H. Saha, Int. J. Nanosci. 05 (2006) 69 [15]S. N. Magonov, V. Elings, and M. H. Whangbo, Surf. Sci.375 (1997) L385 [16] M. Ray, S. Sarkar, N. R. Bandyopadhyay, S. M. Hossain, J. Appl. Phys. 105 (2009) 074301 [17]M. Ray, K. Jana, N. R.Bandyopadhyay, S. M. Hossain, Solid State Communications 149 (9-10) (2009) 352-356 [18]P.G. Lecomber, A.E. Owen, W.E. Spear, J. Hajto, A.J. Snell, W.K. Choi, M.J. Rose, Journal of Non-Crystalline Solids77–78(1985) 1373-1382 [19] A. Avila, R. Asomoza, Solid-State Electronics 44 (2000) 17-27 [20] J. Hu, H. M.Branz, R. S.Crandall, S. Ward, Q. Wang, Thin Solid Films 430 (2003) 249–252 [21] P. Bhattacharya, Semiconductor Optoelectronic Devices, second ed., Pearson Edition Asia, 2001, page 359-360 [22] S.M. Sze, K.K.Ng ,Physics of Semiconductor devices ,third ed., John Wiley & Sons, 2014,pp. 675 [23] M. Ray, N. R. Bandyopadhyay, U. Ghanta, R. F. Klie, A. K. Pramanick, S. Das, Samit K. Ray and S. M. Hossain, J. Appl. Phys. 110, (2011)094309 [24]M. V. Wolkin, J. Jorne, P. M. Fauchet, Phys. Rev. Lett. 82 (1999) 197 [25] S. Prezioso, S. M. Hossain, A. Anopchenko, L. Pavesi, Appl. Phys. Lett. 94(2009) 062108 [26] B.G. Streetman, S.K. Banerjee, Solid State Electronic Devices, seventh ed., PHI Learning Private Limited, Delhi, 2015 ,pp. 185 [27]R.K.Pathria, P.D. Beale, Statistical mechanics, third ed., Elsevier Ltd,2011, pp. 423 [28]K. Huang, Statistical Mechanics, second ed., John Wiley & Sons, USA, 1987, pp. 354 [29] S. Haykin,Neural Networks: A Comprehensive Foundation, second ed.,Pearson Prentice Hall, 2005,pp. 36-37