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Current status and future directions of SOI technology
Solid-State Electronics 46 (2002) 951–958 www.elsevier.com/locate/sse
Current status and future directions of SOI technology Makoto Yoshimi
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System LSI Research & Development Center, System LSI Division, Toshiba Corp., 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan Received 15 May 2001; accepted 20 May 2001
Abstract Current status and future directions of SOI technology are reviewed, by discussing advantages and issues to be solved for MPU, RF, and other low-power applications. The possibility of future MOSFET scaling is also discussed for novel SOI device structures based on modified scaling scenarios. It is recognized that the progress of SOI technology is adding CMOS technology unique flexibility and possibilities, which are both expected to provide useful countermeasures for circumventing the present scaling crisis. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction After a long development history, SOI technology has started to be used as the mainstream technology in CMOS LSIs. Practical applications at present are mostly for MPUs [1–3], but the possibilities are expanding from high-speed/low-power logic LSIs [4–6] to RF/analog LSIs [7–9], DRAMs [10–12], very low-voltage logic LSIs [13,14], imagers [15,16], system on a chip (SoC) [17] and so on. On the other hand, because of the repeated acceleration of the technology roadmap [18], scaling of CMOS is confronting a severe situation where fundamental physical phenomena, such as tunneling current and inversion layer quantization, appear to be limiting factors. Although gate length miniaturization has been proved to be possible down to 30 nm or less [19,20], it is hard to depict a clear scaling scenario applicable to the latter half of this decade. That is, development of high-k materials is still in the phase of material-selection, making their on-schedule debut very unlikely. Moreover, it should be recognized that finite inversion layer thickness as well as gate electrode depletion will make the current gain less than originally expected, even though high-k film is successfully developed.
*
Tel.: +81-45-770-3634; fax: +81-45-770-3571. E-mail address: [email protected] (M. Yoshimi).
In this paper, the current status and future direction of SOI technology are discussed. Consideration is given on the possibility of scaling scenarios that can replace the conventional scaling under the condition where gate insulator thickness is no longer scaled. It is stressed that SOI structure will continue to play important roles respecting extendibility of MOSFET scaling limit, as well as, adaptability to the possible post-scaling era in which more flexible technology will be required to realize a variety of functions, rather than achieving high speed and low power.
2. Current status of SOI technology and LSI applications Leverage of SOI in MPU applications is provided by its junction capacitance which is negligible compared to that in bulk Si. SOI’s high-speed/low-power advantage has been demonstrated by a number of works [1,4, 6]. Circuit instabilities originating from the floatingbody effect, have been analyzed for various critical circuitries, and many countermeasures have been proposed from the circuit technology viewpoint [21,22]. In spite of the controversy respecting the scaling merits of SOI [23, 24] in MPU applications, circuit designers have come to recognize that they can materialize the high-speed/lowpower advantage while controlling the floating-body effects. Increasing availability of practical circuit design tools and literatures on design methodology [25] will contribute to the rapid growth of this field.
0038-1101/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 2 ) 0 0 0 3 0 - 8
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In RF/analog applications, on the other hand, a number of attractive features have been reported. Among them, realization of high-Q inductors using a high-resistivity (>1 kX cm) Si substrate [26] and reduction of digital-to-analog crosstalk [27] are great advantages. Regarding high-resistivity Si substrate made from CZ wafers, suppression of oxygen-originated donor generation [28] while maintaining a sufficient mechanical strength of wafers is important. Most key analog circuits including low-noise amplifier [7,9,29], mixer [7,9], voltage-controlled oscillator [7,9], and integrated power amplifier [8] etc. have already been demonstrated. Reduction of design cost as well as wafer cost will spur growth of these fields, following MPU applications. Regarding low-voltage applications, a 0.5 V operation ALU utilizing gate-to-body connected structure was demonstrated to operate at 200 MHz with 2 mW [13]. Independent control of SOI body potential provides optimum threshold voltage, which brings about an effective solution to the trade-off between leakage suppression and high-speed operation. A watch controller operated at 0.4 V with drain current of 30 nA was also demonstrated [14]. It paves the way to an ultimate lowpower LSI system in the future, for which operation power would be supplied by environment-friendly energy, such as solar cell or human power. In memory applications, advantages and issues of SOI–DRAMs have been extensively studied, mainly by Japanese and Korean DRAM manufacturers [10–12,30– 35] (Table 1). It was confirmed that 20–30% faster access time and lower voltage operation than those of bulk Si DRAMs can be obtained by SOI [10,34]. In addition, SOI–DRAMs are found to be virtually soft-error free [10]. It should be noted that the soft-error hardness gives SOI an added advantage in logic LSIs or imager applications as well. In the case of logic LSIs, the soft-error rate was reported to increase by 2.2 orders of magni-
Table 1 History of SOI DRAM development Year
Company
Results
1987 1992
Fujitsu [30] Sony [31]
1993 1994
Mitsubishi [10] NEC [32]
1994
Sony [33]
1995 1996 1997 1999
Samsung [34] Mitsubishi [35] Hyundai [11] Samsung [12]
64 kb DRAM on bonded SOI Buried capacitor cell using bonded SOI 64 kb DRAM, 2 V operation 6 longer retention time than bulk Si 256 kb DRAM by FD P-ch MOSFET 16 Mb DRAM by SIMOX 16 Mb DRAM, 0.9 V operation 1 Gb DRAM 16 Mb DRAM by SOCa
a
SOC: silicon on capacitors.
tudes per 1 V decrease in operation voltage in conventional technology [36]. In SOI–DRAMs, the dynamic retention issue has been pointed out as a fundamental issue to be solved [34]. Although several countermeasures have been proposed [37], this constitutes one of the impediments to practical introduction of SOI into DRAMs. More immediate reasons might have been (1) costly SOI wafers, (2) less reliable gate oxide than that of bulk Si, and (3) the fact that SOI does not directly contribute to the resolving the capacitor construction issue which is pressing in current DRAM technology. Nevertheless, in view of increasing demand for SoC applications in the future, how to implement DRAM together with logic circuits on SOI will become an important issue. Mixed-substrate implementation in which DRAM is built on partially bulk Si substrate [38] will become one realistic approach, in that bulk Si DRAM technology can be transferred on SOI wafer without any special modification. Compared to DRAMs, flash [39], FeRAM or MRAM [40] implementation is significantly underdeveloped compared with other devices. Non-volatile memories are essential in system LSIs. A high-writing voltage in conventional flash memories is not commensurate with low drain-breakdown voltage in SOI MOSFETs. From the operation voltage point of view, FeRAM or MRAM might be suitable for SOI, because of their potential for operating at a low voltage. Nevertheless, it should be noted that the use of a partially bulk Si substrate will help remove this constraint and widen the degree of freedom in the choice of memory. CCD imagers have also been demonstrated by using a partially bulk Si structure [15]. By using a high-resistivity substrate as a photo-sensor and SOI as a signalprocessing circuit layer, excellent photo-response as well as minimal signal cross-talk has also been obtained in CMOS imager [16]. As shown in this case, the fact that the specification of the substrate can be independently determined opens up various possibilities which are unavailable with bulk Si. As long as current SOI MOSFET technology is driven by partially depleted MOSFETs, it will sooner or later face the same miniaturization limit as bulk Si MOSFETs. Outstanding advantages and flexibility in the SOI structure will help circumvent this crisis and achieve high-performance at the system level which is key in SoC applications. In the following sections, the scaling crisis and the possibility of new device structures are addressed in detail.
3. Scaling crisis and SOI(-like) structure With acceleration of the roadmap, gate oxide thickness becomes thinner and thinner. In accordance with this trend, maximum acceptable gate leakage current in
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Fig. 1. Gate leakage for various gate dielectrics as a function of physical equivalent oxide thickness. Maximum allowable gate leakage current is also shown for MPU and LOP ASIC applications, respectively.
MPU applications has been relaxed year by year [41], which resulted in the extension of the life of silicondioxide system. However, in low-power applications, where the gate leakage is severely limited because of unacceptable increase in power consumption, it is predicted that silicon dioxide or silicon oxynitride gate insulator will have a shorter life than in MPU applications. Fig. 1 shows gate leakage current for various gate insulators including high-k materials [43–51]. Maximum gate leakage currents acceptable for typical MPU, lowoperation power (LOP) ASIC applications are shown in the figure. The calculation of LOP applications is based on the requirement for portable telecommunication equipment. In this application, gate leakage should be strictly suppressed together with junction leakage and subthreshold leakage, because of the limited weight and volume associated with battery use. Still, fast processing speed is required for the purpose of high-level signal processing such as high-quality image processing or knowledge-based computing [52]. For such a severe requirement, development of high-k films is still in the early stage of research where characterizations of various candidate materials are the key theme. Although in recent years the speed of their development has been noteworthy [42–51], there is little prospect of the early development of high-k films, considering numerous requirements to be satisfied, such as thermal stability, low interface state, low fixed charge density, high carrier mobility, and the long period during which data on the Si=SiO2 system has been accumulated. In addition, finite inversion layer capacitance as well as gate electrode depletion will make the current gain by the use of high-k film less than originally expected. It is estimated that, when the technology node reaches around 50 nm, the
equivalent gate oxide thickness becomes roughly equal to the inversion layer thickness (Teq ¼ 0:5 nm). This indicates that the difficulties of high-k film development are not only a matter of their physical capabilities or compatibility with CMOS integration, but also involve the matching with technology timing required by the roadmap. Therefore, it is necessary to prepare a solution for the worst case, based on the assumption that no further current improvement by means of vertical scaling of gate dielectric can be expected.
4. Consideration of modified scaling scenarios The scaling theory has brought (1) higher performance, (2) lower power, and (3) lower cost, at an almost constant pace for more than 20 years [53]. In considering an alternative scaling scenario, the economical aspect of the scaling should be borne in mind quite as much as the performance gain. Table 2 shows possible scaling scenarios for various device structures. With respect to the description below row 2, it is assumed that gate dielectric thickness can no longer be scaled, which as mentioned above is not an unrealistic scenario. Moreover, it is assumed that shrinkage of chip size has a high priority from the viewpoint of economy. 4.1. Scaling in planar structure with constant equivalent oxide thickness (Teq ) If we suppose that only the gate dielectric thickness is not scaled in the conventional scaling, the drain current falls as 1=k 2 . Although, in this case, both gate delay metric and power consumption will improve, the
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Table 2 Conventional scaling (first row) and alternative scenarios (below second row) on the assumption that gate dielectric is no longer scaled Teq Conventional scaling Conventional (constant Teq ) Conventional (constant Teq , V) Delta-type Delta-type (conventional V) Vertical (rectangular) Vertical (rectangular, constant V) Vertical (SGT) Vertical (SGT, constant V)
1=k 1 1 1 1 1 1 1 1
L 1=k 1=k 1=k 1=k 1=k 1=k 1=k 1=k 1=k
W 1=k 1=k 1=k 1 1 1=k 1=k 1 1
V 1=k 1=k 1 1=k 1 1=k 1 1=k 1
I 1=k 1=k 2 1=k 1=k 1 1=k 2 1=k 1=k 1
C 1=k 1=k 2 1=k 2 1=k 1=k 1=k 2 2 1=k 1=k 1=k
CV =I 1=k 1=k 1=k 1=k 1=k 1=k 1=k 1=k 1=k
fCV 2 2
1=k 1=k 3 1=k 1=k 2 1 1=k 3 1=k 1=k 2 1
Area 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2
Chip size shrink is a must from the economical requirement. Gate dielectric thickness is no longer scaled below second row. Asterisk(*) includes doubling of W.
decreased drain current will cause problems in driving local loads due to various parasitic capacitances and heavy interconnects. To maintain the drain current, keeping the voltage constant can be a practical modification (Fig. 2). The result is that excessive decrease of drain current is avoided and the gate delay metric improves. However, since the power consumption decreases only as 1=k, increase of transistor number will be limited. This scenario may appear in a conventional scaling as a practical modification. In order for this scenario to continue, however, the devices should be resistant to the short-channel effect. In this context, fully depleted (FD) MOSFET [54] and double gate (DG) MOSFETs [55,56] can be categorized as the devices relevant to this scaling scenario. In the case of FD MOSFET, very thin (several nm thick) SOI film will be required, whereas DG MOSFET, in view of its better resistance to shortchannel effect, will survive even after FD reaches the limit of SOI thinning [57]. The practical SOI thinning is limited due to the process technology at present, but it should be noted that, on the basis of theoretical con-
siderations, higher mobility is predicted in 3 nm-thick SOI than in bulk Si MOSFET [58]. Electron system in such an ultrathin region is worthy of study in view of both its physical interest and practical importance. It should be added that the possibility of modulating the inversion layer capacitance is also suggested by thinning the silicon layer [59]. 4.2. Scaling of DELTA-type structure 3D structure such as DELTA (Fin) (Fig. 3) [60,61] is attractive in that sidewall channel is effectively utilized for increase of current gain. In DELTA (Fin) MOSFETs, current decrease due to setting Teq constant can be canceled out by keeping the (effective) channel width (W) constant. Since the channel width can be independent of the area occupied, it is possible to downscale the chip area in the same way as in the conventional scaling. The drain current can also be scaled as in the conventional scaling, in addition to doubling of current. The power reduction follows 1=k 2 , keeping power density
Fig. 2. Alternative scaling scenario (1) on the assumption that gate dielectric is no longer scaled. Voltage is kept constant. Shortchannel-effect resistant structures can survive at the cost of increase in power density.
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Fig. 3. Alternative scaling scenario (2). In DELTA (Fin-FET) structure, keeping channel width constant allows for continuation of conventional scaling, even if gate dielectric scaling reaches limitation.
constant (except for a factor of 2). In the formation of gate electrode in DELTA structure, there is no selfalignment issue such as that encountered in DG MOSFETs. The scaling limit of DELTA will be determined by the limit of SOI thinning as in the case of DG MOSFETs. It is true that whether this scenario is realized or not critically depends on process technology. However, it provides an attractive scenario in that the conventional scaling can be continued, while accompanied by the advantages of DG MOSFETs.
Vertical MOSFET [62] is also a candidate because of its good short-channel behavior as well as doubling of drain current (Fig. 4). From the scaling scenario, rectangular shape where the channel width is determined by the lateral length of the channel does not seem to be advantageous in that the drain current decreases as 1=k 2 (except for a factor of 2). It follows that the SGT-type device [63] will be advantageous in this structure in that the effective channel width can be increased while simultaneously shrinking a chip size.
Fig. 4. Alternative scaling scenario (3). In vertical MOSFETs, drain current in rectangular-type structure decreases because of decrease in laterally defined channel width, apart from doubling by the availability of both sidewalls. Keeping channel width constant by SGTtype allows for continuation of scaling.
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Fig. 5. Mobility increase by strained-Si SOI MOSFET offers another promising scenario.
4.3. Other device structures or scaling scheme To offset the decrease due to scaling limit of gate dielectric, increasing mobility using SiGe structure or strained-Si [64] may also be advantageous for achieving a breakthrough. Note that SOI structure is essential in this case for suppressing the short-channel effect [65]. It is predicted theoretically that in strained-Si MOSFETs the saturation velocity can be increased for approximately two generations [66] (see Fig. 5).
5. Summary The current status and future directions of SOI technology has been discussed. While SOI has started to be practically used in a wide range of LSIs, scaling saturation is also a pressing issue. Two approaches have been stressed to overcome this difficulty. One is pursuing a scenario in which conventional scaling is continued, even if the scaling of gate dielectric film reaches saturation. In this case, short-channel resistance and availability of vertical channel structure, both of which are prominent features of SOI, play the important roles in obtaining high performance. The other approach is to utilize the flexibility of SOI and realize a wide range of functions which cannot be achieved by bulk Si technology. The latter is suitable for the coming SoC era, in
which not only memory and logic circuits, but also analog circuits, imagers and so on will be implemented on the same chip.
Acknowledgements The author would like to thank Mr. K. Inoh, Mr. Y. Katsumata, Dr. T. Fuse, Dr. T. Mizuno, Dr. S. Takagi, and Dr. H. Ishiuchi, all of Toshiba Corp., for a lot of suggestive discussions and comments. In addition, he is grateful to Dr. T. Masuhara, ASET, Dr. T. Sugii, Fujitsu Lab., and committee members who have contributed to the Semiconductor Technology Roadmap in Japan (STRJ) for useful discussions.
References [1] Shahidi GG, Ajmera A, Assaderaghi F, Bolam RJ, Leobandung E, Rausch W, et al. Partially-depleted SOI technology for digital logic. Tech Dig ISSCC 1999:426–7. [2] Kim YW, Park SB, Ko YG, Kim KI, Kim IK, Bae KJ, et al. A 0.25 lm 600 MHz 1.5 V SOI 64b ALPHA microprocessor. Tech Dig ISSCC 1999:432–3. [3] Tsai UC. A 1 GHz PA-RISC processor. Tech Dig ISSCC 2001:322–3. [4] Ueda K, Nii K, Wada Y, Takimoto I, Maeda S, Iwamatsu T, et al. A CAD-compatible SOI/CMOS gate array having
M. Yoshimi / Solid-State Electronics 46 (2002) 951–958
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18] [19]
[20]
[21]
body-fixed partially-depleted transistors. Tech Dig ISSCC 1997:288–9. Ohtomo Y, Yasuda S, Nogami M, Inoue J, Yamakoshi K, Sawada H, et al. A 50 Gb/s 8 8 ATM switch LSI using 0.25 lm CMOS/SIMOX. Tech Dig ISSCC 1997:154–5. Adan AO, Naka T, Kaneko S, Urabe D, Higashi K, Kagisawa A. Device Integration of a 0.35 lm CMOS on shallow SIMOX technology for high-speed and low-power applications. Proc IEEE Int SOI Conf 1996:116–7. Harada M, Tsukahara T, Yamada J. 0.5-1 V 2 GHz RF front-end circuits in CMOS/SIMOX. Tech Dig ISSCC 2000:378–9. Kumar M, Tan Y, Sin J, Shi L, Lau J. A 900 MHz SOI fully-integrated RF power amplifier for wireless transceivers. Tech Dig ISSCC 2000:382–3. Dekker R, Baltus P, van Deurzen M, Einden Wvd, Maas H, Wagemans A. An ultra low-power RF bipolar technology on glass. Tech Abst IEDM 1997:921–4. Eimori T, Oashi T, Kimura H, Yamaguchi Y, Iwamatasu T, Tsuruda T, et al. ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation. Tech Abst IEDM 1993:45–8. Koh Y-H, Oh M-R, Lee J-W, Yang J-W, Lee W-C, Park C-K, et al. 1 Giga Bit SOI DRAM with fully bulk compatible process and body-contacted SOI MOSFET structure. Tech Abst IEDM 1997:579–82. Park J-W, Kim Y-G, Kim I-K, Park K-C, Yoon H, Lee KC, et al. Performance characteristics of SOI DRAM for low-power application. Tech Dig ISSCC 1999:434–5. Fuse T, Oowaki Y, Yamada T, Kamoshida M, Ohta M, Shino T, et al. A 0.5 V 200 MHz 1-Stage 32b ALU using a body bias controlled SOI pass-gate logic. Tech Dig ISSCC 1997:286–7. Ebina A, Kadowaki T, Sato Y, Yamaguchi M. Ultra lowpower CMOS IC using partially-depleted SOI technology. Tech Abst CICC 2000:57–60. Suntharalingam V, Burke B, Cooper M, Yost D, Gouker P, Anthony M, et al. Monolithic 3.3V CCD/SOI-CMOS imager technology. Tech Abst IEDM 2000:697–700. Zheng X, Wrigley C, Yang G, Pain B. High responsivity CMOS imager pixel implemented in SOI technology. Proc IEEE Int SOI Conf 2000:138–9. Hirano Y, Matsumoto T, Maeda S, Iwamatsu T, Kunikiyo T, Nii K, et al. Impact of 0.10 lm SOI CMOS with bodytied hybrid trench isolation structure to break through the scaling crisis of silicon technology. Tech Abst IEDM 2000:467–70. International technology roadmap for semiconductors (ITRS), 1999. Deleonibus S, Caillat C, Guegan G, Heitzmann M, Nier ME, Tedesco S, et al. A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets. IEEE Elec Dev Lett 2000;21(4):173–5. Chau R, Kavalieros J, Roberds B, Schenker R, Lionberger D, Barlage D, et al. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays. Tech Abst IEDM 2000:45–8. Canada M, Akrout C, Cawthron D, Corr J, Geissler S, Houle R, et al. A 580 MHz RISC microprocessor in SOI. Tech Dig ISSCC 1999:430–1.
957
[22] Allen DH, Aipperspach AG, Cox DT, Phan NV, Storino SN. A 0.2 lm 1.8 V SOI 550 MHz 64b powerPC microprocessor with copper interconnects. Tech Dig ISSCC 1999:438–9. [23] Chau R, Arghavani R, Alavi M, Douglas D, Greason J, Green R, et al. Scalability of partially depleted SOI technology for sub-0.25 lm logic applications. Tech Abst IEDM 1997:591–4. [24] Leobandung E, Sherony M, Sleight J, Bolam R, Assaderaghi F, Wu S, et al. Scalability of SOI technology into 0.13 lm 1.2V CMOS generation. Tech Abst IEDM 1998:403–6. [25] Bernstein K, Rohrer NJ. SOI circuit design concepts. Dordrecht: Kluwer Academic Publishers; 2000. [26] Maeda S, Wada Y, Yamamoto K, Komurasaki H, Matsumoto T, Hirano Y, et al. Impact of 0.18 lm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded analog applications. Dig Symp VLSI Tech 2000:154–5. [27] Kodate J, Harada M, Tsukahara T. Suppression of substrate crosstalk in mixed analog-digital CMOS circuits by using high-resistivity SIMOX wafers. Ext Abst Int Conf Sol St Mat, 1999. p. 362–63. [28] Abe T, Saito S, Aihara K, Qu W, Hayamizu Y, Kimura M, et al. Creation of bonded SOI substrate with CZ silicon higher than 1000 Xcm in resistivity. Ext Abst Int Conf Sol St Dev Mat (SSDM), 1999. p. 356–57. [29] Harada M, Tsukahara T. Monolithic 2 GHz and 4–6 GHz low noise amplifiers fabricated on a SIMOX wafer. Ext Abst Int Conf Sol St Dev Mat (SSDM), 1997. p. 132–33. [30] Gotou H, Arimoto Y, Ozeki M, Imaoka K. Soft error rate of 64K SOI–DRAM. Tech Abst IEDM 1987:870–1. [31] Nishihara T, Ikeda N, Aozasa H, Miyazawa Y, Ochiai A. A buried capacitor DRAM cell with bonded SOI for 256M and 1 Gbit DRAMs. Tech Abst IEDM 1992:803–6. [32] Tanigawa T, Yoshino A, Koga H, Ohya S. Enhancement of data retention time for Giga-bit DRAMs using SIMOX technology. Dig Symp VLSI Tech 1994:37–8. [33] Nishihara T, Moriya H, Ikeda N, Aozasa H, Miyazawa Y. Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell. Dig Symp VLSI Technol 1994:39–40. [34] Kim H-S, Lee S-B, Choi D-U, Shim J-H, Lee K-C, Lee K-P, et al. A high performance 16M DRAM on a thin film SOI. Dig Symp VLSI Technol 1995:143–4. [35] Oashi T, Eimori T, Morishita F, Iwamatsu T, Yamaguchi Y, Okuda F, et al. 16Mb DRAM/SOI technologies for sub1V operation. Tech Abst IEDM 1996:609–12. [36] Cohen N, Sriram TS, Lelan N, Moyer D, Butler S, Flatley R. Soft error considerations for deep-submicron CMOS circuit applications. Tech Abst IEDM 1999:315–8. [37] Morishita F, Suma K, Hirose M, Tsuruda T, Tamaguchi Y, Eimori T, et al. Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM. Dig Symp VLSI Technol 1995:141–2. [38] Hannon R, Iyer SSK, Sadana D, Rice JP, Ho HL, Khan BA, et al. 0.25 lm merged bulk DRAM and SOI logic using patterned SOI. Dig Symp VLSI Technol 2000:66–7. [39] Tang X, Baie X, Bayot V, de Wiele FV, Colinge J-P. Fabrication, characterization and self-consistent simulation of an SOI nano flash memory device. Tech Abst IEDM 1999:919–21.
958
M. Yoshimi / Solid-State Electronics 46 (2002) 951–958
[40] Durlam M, Naji P, DeHerrera M, Tehrani S, Kerszykowski G, Kyler K. Nonvolatile RAM based on magnetic tunnel junction elements. Tech Dig ISSCC 2000:130–1. [41] Ghani T, Mistry K, Packan P, Thompson S, Stettler M, Tyagi S, et al. Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors. Dig Symp VLSI Tech 2000:174– 5. [42] Lee SJ, Luan HF, Bai WP, Lee CH, Jeon TS, Senzaki Y, et al. High quality ultra thin CVD HfO2 gate stack with poly-Si gate electrode. Tech Abst IEDM 2000:31–4. [43] Osten HJ, Liu JP, Gaworzewski P, Bugiel E, Zaumseil P. High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide. Tech Abst IEDM 2000:653–6. [44] Chin A, Wu YH, Chen SB, Liao CC, Chen WJ. High quality La2 O3 and Al2 O3 gate dielectrics with equivalent . Dig Symp VLSI Technol 2000:16– oxide thickness 5–10 A 7. [45] Qi W-J, Nieh R, Lee BH, Kang L, Jeon Y, Onishi K, et al. MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si. Tech Abst IEDM 1999:145–8. [46] Luan HF, Lee SJ, Lee CH, Song SC, Mao YL, Senzaki Y, et al. High quality Ta2 O5 gate dielectrics with Tox;eq < . Tech Abst IEDM 1999:141–4. 10 A [47] Buchanan DA, Gusev EP, Cartier E, Okorn-Schmidt H, Rim K, Gribelyuk MA, et al. 80 nm poly-silicon gated nFETs with ultra-thin Al2 O3 gate dielectric for ULSI applications. Tech Abst IEDM 2000:223–6. [48] Guo X, Wang X, Luo Z, Ma TP, Tamagawa T. High quality ultra-thin (1.5 nm) TiO2 /Si3 N4 gate dielectric for deep sub-micron CMOS technology. Tech Abst IEDM 1999:137–40. [49] Lee BH, Kang L, Qi W-J, Nieh R, Jeon Y, Onishi K, et al. Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application. Tech Abst IEDM 1999:133–6. [50] Kang L, Jeon Y, Onishi K, Lee BH, Qi W-J, Nieh R, et al. Single-layer thin HfO2 gate dielectric with nþ polysilicon gate. Dig Symp VLSI Technol 2000:44–5. [51] Kang L, Onishi K, Jeon Y, Lee BH, Kang C, Qi W-J, et al. MOSFET devices with polysilicon on single-layer HfO2 high-K dielectrics. Tech Abst IEDM 2000:35–8. [52] Enoki K. i-mode: the mobile internet service of the 21st century. Tech Dig ISSCC 2001:12–5. [53] Gelsinger PP. Microprocessors for the new millennium: challenges, opportunities, and new frontiers. Tech Dig ISSCC 2001:22–5.
[54] Colinge J-P. Slicon-on-insulator technology: material to VLSI. Dordrecht: Kluwer Academic Publishers; 1991. [55] Tanaka T, Horie H, Ando S, Hijiya S. Analysis of Pþ poly Si double-gate thin-film SOI MOSFETs. Tech Abst IEDM 1991:683–6. [56] Lee J-H, Taraschi G, Wei A, Langdo TA, Fitzgerald EA, Antoniadis DA. Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy. Tech Abst IEDM 1999:71–4. [57] Wong H-SP, Frank DJ, Solomon PM. Device design considerations for double-gate, ground-plane, and singlegated ultra-thin SOI MOSFET’s at the 25 nm channel length generation. Tech Abst IEDM 1998:407–10. [58] Takagi S, Koga J, Toriumi A. Mobility enhancement of SOI MOSFETs due to subband modulation in ultra-thin SOI films. Ext Abst Int Conf Sol St Dev Mat, 1997. p. 154. [59] Takagi S. Optimized design of the subband structure in MOS inversion layers for realizing high performance and low power Si MOSFETs. Int J High Speed Electron Syst 2000;10(1):155–70. [60] Hisamoto D, Kaga T, Kawamoto Y, Takeda E. A fully depleted lean-channel transistor (DELTA)—a novel vertical ultra thin SOI MOSFET. Tech Abst IEDM 1989: 833–6. [61] Hisamoto D, Lee W-C, Kedzierski J, Anderson E, Takeuchi H, Asano K, et al. A folded-channel MOSFET for deep-sub-tenth micron era. Tech Abst IEDM 1998:1032– 5. [62] Hergenrother JM, Monroe D, Klemens FP, Kornblit A, Weber GR, Mansfield WM, et al. The vertical replacament-gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length. Tech Abst IEDM 1999:75–8. [63] Takato H, Sunouchi K, Okabe N, Nitayama A, Hieda K, Horiuchi F, et al. High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs. Tech Abst IEDM 1988:222–5. [64] Welser J, Hoyt JL, Takagi S, Gibbons JF. Strain dependence of the performance enhancement in strained-Si n-MOSFETs. Tech Abst IEDM 1994:373–6. [65] Mizuno T, Takagi S, Sugiyama N, Koga J, Tezuka T, Usuda K, et al. High performance strained-Si p-MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology. Tech Abst IEDM 1999:934–6. [66] Hatakeyama T, Matsuzawa K, Takagi S. Impact of strained-Si channel on CMOS circuit performance under the sub-100 nm regime. Ext Abst Int Conf Sol St Dev Mat (SSDM), 2000. p. 62–3.
Current status and future directions of SOI technology Makoto Yoshimi
*
System LSI Research & Development Center, System LSI Division, Toshiba Corp., 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan Received 15 May 2001; accepted 20 May 2001
Abstract Current status and future directions of SOI technology are reviewed, by discussing advantages and issues to be solved for MPU, RF, and other low-power applications. The possibility of future MOSFET scaling is also discussed for novel SOI device structures based on modified scaling scenarios. It is recognized that the progress of SOI technology is adding CMOS technology unique flexibility and possibilities, which are both expected to provide useful countermeasures for circumventing the present scaling crisis. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction After a long development history, SOI technology has started to be used as the mainstream technology in CMOS LSIs. Practical applications at present are mostly for MPUs [1–3], but the possibilities are expanding from high-speed/low-power logic LSIs [4–6] to RF/analog LSIs [7–9], DRAMs [10–12], very low-voltage logic LSIs [13,14], imagers [15,16], system on a chip (SoC) [17] and so on. On the other hand, because of the repeated acceleration of the technology roadmap [18], scaling of CMOS is confronting a severe situation where fundamental physical phenomena, such as tunneling current and inversion layer quantization, appear to be limiting factors. Although gate length miniaturization has been proved to be possible down to 30 nm or less [19,20], it is hard to depict a clear scaling scenario applicable to the latter half of this decade. That is, development of high-k materials is still in the phase of material-selection, making their on-schedule debut very unlikely. Moreover, it should be recognized that finite inversion layer thickness as well as gate electrode depletion will make the current gain less than originally expected, even though high-k film is successfully developed.
*
Tel.: +81-45-770-3634; fax: +81-45-770-3571. E-mail address: [email protected] (M. Yoshimi).
In this paper, the current status and future direction of SOI technology are discussed. Consideration is given on the possibility of scaling scenarios that can replace the conventional scaling under the condition where gate insulator thickness is no longer scaled. It is stressed that SOI structure will continue to play important roles respecting extendibility of MOSFET scaling limit, as well as, adaptability to the possible post-scaling era in which more flexible technology will be required to realize a variety of functions, rather than achieving high speed and low power.
2. Current status of SOI technology and LSI applications Leverage of SOI in MPU applications is provided by its junction capacitance which is negligible compared to that in bulk Si. SOI’s high-speed/low-power advantage has been demonstrated by a number of works [1,4, 6]. Circuit instabilities originating from the floatingbody effect, have been analyzed for various critical circuitries, and many countermeasures have been proposed from the circuit technology viewpoint [21,22]. In spite of the controversy respecting the scaling merits of SOI [23, 24] in MPU applications, circuit designers have come to recognize that they can materialize the high-speed/lowpower advantage while controlling the floating-body effects. Increasing availability of practical circuit design tools and literatures on design methodology [25] will contribute to the rapid growth of this field.
0038-1101/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 2 ) 0 0 0 3 0 - 8
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In RF/analog applications, on the other hand, a number of attractive features have been reported. Among them, realization of high-Q inductors using a high-resistivity (>1 kX cm) Si substrate [26] and reduction of digital-to-analog crosstalk [27] are great advantages. Regarding high-resistivity Si substrate made from CZ wafers, suppression of oxygen-originated donor generation [28] while maintaining a sufficient mechanical strength of wafers is important. Most key analog circuits including low-noise amplifier [7,9,29], mixer [7,9], voltage-controlled oscillator [7,9], and integrated power amplifier [8] etc. have already been demonstrated. Reduction of design cost as well as wafer cost will spur growth of these fields, following MPU applications. Regarding low-voltage applications, a 0.5 V operation ALU utilizing gate-to-body connected structure was demonstrated to operate at 200 MHz with 2 mW [13]. Independent control of SOI body potential provides optimum threshold voltage, which brings about an effective solution to the trade-off between leakage suppression and high-speed operation. A watch controller operated at 0.4 V with drain current of 30 nA was also demonstrated [14]. It paves the way to an ultimate lowpower LSI system in the future, for which operation power would be supplied by environment-friendly energy, such as solar cell or human power. In memory applications, advantages and issues of SOI–DRAMs have been extensively studied, mainly by Japanese and Korean DRAM manufacturers [10–12,30– 35] (Table 1). It was confirmed that 20–30% faster access time and lower voltage operation than those of bulk Si DRAMs can be obtained by SOI [10,34]. In addition, SOI–DRAMs are found to be virtually soft-error free [10]. It should be noted that the soft-error hardness gives SOI an added advantage in logic LSIs or imager applications as well. In the case of logic LSIs, the soft-error rate was reported to increase by 2.2 orders of magni-
Table 1 History of SOI DRAM development Year
Company
Results
1987 1992
Fujitsu [30] Sony [31]
1993 1994
Mitsubishi [10] NEC [32]
1994
Sony [33]
1995 1996 1997 1999
Samsung [34] Mitsubishi [35] Hyundai [11] Samsung [12]
64 kb DRAM on bonded SOI Buried capacitor cell using bonded SOI 64 kb DRAM, 2 V operation 6 longer retention time than bulk Si 256 kb DRAM by FD P-ch MOSFET 16 Mb DRAM by SIMOX 16 Mb DRAM, 0.9 V operation 1 Gb DRAM 16 Mb DRAM by SOCa
a
SOC: silicon on capacitors.
tudes per 1 V decrease in operation voltage in conventional technology [36]. In SOI–DRAMs, the dynamic retention issue has been pointed out as a fundamental issue to be solved [34]. Although several countermeasures have been proposed [37], this constitutes one of the impediments to practical introduction of SOI into DRAMs. More immediate reasons might have been (1) costly SOI wafers, (2) less reliable gate oxide than that of bulk Si, and (3) the fact that SOI does not directly contribute to the resolving the capacitor construction issue which is pressing in current DRAM technology. Nevertheless, in view of increasing demand for SoC applications in the future, how to implement DRAM together with logic circuits on SOI will become an important issue. Mixed-substrate implementation in which DRAM is built on partially bulk Si substrate [38] will become one realistic approach, in that bulk Si DRAM technology can be transferred on SOI wafer without any special modification. Compared to DRAMs, flash [39], FeRAM or MRAM [40] implementation is significantly underdeveloped compared with other devices. Non-volatile memories are essential in system LSIs. A high-writing voltage in conventional flash memories is not commensurate with low drain-breakdown voltage in SOI MOSFETs. From the operation voltage point of view, FeRAM or MRAM might be suitable for SOI, because of their potential for operating at a low voltage. Nevertheless, it should be noted that the use of a partially bulk Si substrate will help remove this constraint and widen the degree of freedom in the choice of memory. CCD imagers have also been demonstrated by using a partially bulk Si structure [15]. By using a high-resistivity substrate as a photo-sensor and SOI as a signalprocessing circuit layer, excellent photo-response as well as minimal signal cross-talk has also been obtained in CMOS imager [16]. As shown in this case, the fact that the specification of the substrate can be independently determined opens up various possibilities which are unavailable with bulk Si. As long as current SOI MOSFET technology is driven by partially depleted MOSFETs, it will sooner or later face the same miniaturization limit as bulk Si MOSFETs. Outstanding advantages and flexibility in the SOI structure will help circumvent this crisis and achieve high-performance at the system level which is key in SoC applications. In the following sections, the scaling crisis and the possibility of new device structures are addressed in detail.
3. Scaling crisis and SOI(-like) structure With acceleration of the roadmap, gate oxide thickness becomes thinner and thinner. In accordance with this trend, maximum acceptable gate leakage current in
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Fig. 1. Gate leakage for various gate dielectrics as a function of physical equivalent oxide thickness. Maximum allowable gate leakage current is also shown for MPU and LOP ASIC applications, respectively.
MPU applications has been relaxed year by year [41], which resulted in the extension of the life of silicondioxide system. However, in low-power applications, where the gate leakage is severely limited because of unacceptable increase in power consumption, it is predicted that silicon dioxide or silicon oxynitride gate insulator will have a shorter life than in MPU applications. Fig. 1 shows gate leakage current for various gate insulators including high-k materials [43–51]. Maximum gate leakage currents acceptable for typical MPU, lowoperation power (LOP) ASIC applications are shown in the figure. The calculation of LOP applications is based on the requirement for portable telecommunication equipment. In this application, gate leakage should be strictly suppressed together with junction leakage and subthreshold leakage, because of the limited weight and volume associated with battery use. Still, fast processing speed is required for the purpose of high-level signal processing such as high-quality image processing or knowledge-based computing [52]. For such a severe requirement, development of high-k films is still in the early stage of research where characterizations of various candidate materials are the key theme. Although in recent years the speed of their development has been noteworthy [42–51], there is little prospect of the early development of high-k films, considering numerous requirements to be satisfied, such as thermal stability, low interface state, low fixed charge density, high carrier mobility, and the long period during which data on the Si=SiO2 system has been accumulated. In addition, finite inversion layer capacitance as well as gate electrode depletion will make the current gain by the use of high-k film less than originally expected. It is estimated that, when the technology node reaches around 50 nm, the
equivalent gate oxide thickness becomes roughly equal to the inversion layer thickness (Teq ¼ 0:5 nm). This indicates that the difficulties of high-k film development are not only a matter of their physical capabilities or compatibility with CMOS integration, but also involve the matching with technology timing required by the roadmap. Therefore, it is necessary to prepare a solution for the worst case, based on the assumption that no further current improvement by means of vertical scaling of gate dielectric can be expected.
4. Consideration of modified scaling scenarios The scaling theory has brought (1) higher performance, (2) lower power, and (3) lower cost, at an almost constant pace for more than 20 years [53]. In considering an alternative scaling scenario, the economical aspect of the scaling should be borne in mind quite as much as the performance gain. Table 2 shows possible scaling scenarios for various device structures. With respect to the description below row 2, it is assumed that gate dielectric thickness can no longer be scaled, which as mentioned above is not an unrealistic scenario. Moreover, it is assumed that shrinkage of chip size has a high priority from the viewpoint of economy. 4.1. Scaling in planar structure with constant equivalent oxide thickness (Teq ) If we suppose that only the gate dielectric thickness is not scaled in the conventional scaling, the drain current falls as 1=k 2 . Although, in this case, both gate delay metric and power consumption will improve, the
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Table 2 Conventional scaling (first row) and alternative scenarios (below second row) on the assumption that gate dielectric is no longer scaled Teq Conventional scaling Conventional (constant Teq ) Conventional (constant Teq , V) Delta-type Delta-type (conventional V) Vertical (rectangular) Vertical (rectangular, constant V) Vertical (SGT) Vertical (SGT, constant V)
1=k 1 1 1 1 1 1 1 1
L 1=k 1=k 1=k 1=k 1=k 1=k 1=k 1=k 1=k
W 1=k 1=k 1=k 1 1 1=k 1=k 1 1
V 1=k 1=k 1 1=k 1 1=k 1 1=k 1
I 1=k 1=k 2 1=k 1=k 1 1=k 2 1=k 1=k 1
C 1=k 1=k 2 1=k 2 1=k 1=k 1=k 2 2 1=k 1=k 1=k
CV =I 1=k 1=k 1=k 1=k 1=k 1=k 1=k 1=k 1=k
fCV 2 2
1=k 1=k 3 1=k 1=k 2 1 1=k 3 1=k 1=k 2 1
Area 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2 1=k 2
Chip size shrink is a must from the economical requirement. Gate dielectric thickness is no longer scaled below second row. Asterisk(*) includes doubling of W.
decreased drain current will cause problems in driving local loads due to various parasitic capacitances and heavy interconnects. To maintain the drain current, keeping the voltage constant can be a practical modification (Fig. 2). The result is that excessive decrease of drain current is avoided and the gate delay metric improves. However, since the power consumption decreases only as 1=k, increase of transistor number will be limited. This scenario may appear in a conventional scaling as a practical modification. In order for this scenario to continue, however, the devices should be resistant to the short-channel effect. In this context, fully depleted (FD) MOSFET [54] and double gate (DG) MOSFETs [55,56] can be categorized as the devices relevant to this scaling scenario. In the case of FD MOSFET, very thin (several nm thick) SOI film will be required, whereas DG MOSFET, in view of its better resistance to shortchannel effect, will survive even after FD reaches the limit of SOI thinning [57]. The practical SOI thinning is limited due to the process technology at present, but it should be noted that, on the basis of theoretical con-
siderations, higher mobility is predicted in 3 nm-thick SOI than in bulk Si MOSFET [58]. Electron system in such an ultrathin region is worthy of study in view of both its physical interest and practical importance. It should be added that the possibility of modulating the inversion layer capacitance is also suggested by thinning the silicon layer [59]. 4.2. Scaling of DELTA-type structure 3D structure such as DELTA (Fin) (Fig. 3) [60,61] is attractive in that sidewall channel is effectively utilized for increase of current gain. In DELTA (Fin) MOSFETs, current decrease due to setting Teq constant can be canceled out by keeping the (effective) channel width (W) constant. Since the channel width can be independent of the area occupied, it is possible to downscale the chip area in the same way as in the conventional scaling. The drain current can also be scaled as in the conventional scaling, in addition to doubling of current. The power reduction follows 1=k 2 , keeping power density
Fig. 2. Alternative scaling scenario (1) on the assumption that gate dielectric is no longer scaled. Voltage is kept constant. Shortchannel-effect resistant structures can survive at the cost of increase in power density.
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Fig. 3. Alternative scaling scenario (2). In DELTA (Fin-FET) structure, keeping channel width constant allows for continuation of conventional scaling, even if gate dielectric scaling reaches limitation.
constant (except for a factor of 2). In the formation of gate electrode in DELTA structure, there is no selfalignment issue such as that encountered in DG MOSFETs. The scaling limit of DELTA will be determined by the limit of SOI thinning as in the case of DG MOSFETs. It is true that whether this scenario is realized or not critically depends on process technology. However, it provides an attractive scenario in that the conventional scaling can be continued, while accompanied by the advantages of DG MOSFETs.
Vertical MOSFET [62] is also a candidate because of its good short-channel behavior as well as doubling of drain current (Fig. 4). From the scaling scenario, rectangular shape where the channel width is determined by the lateral length of the channel does not seem to be advantageous in that the drain current decreases as 1=k 2 (except for a factor of 2). It follows that the SGT-type device [63] will be advantageous in this structure in that the effective channel width can be increased while simultaneously shrinking a chip size.
Fig. 4. Alternative scaling scenario (3). In vertical MOSFETs, drain current in rectangular-type structure decreases because of decrease in laterally defined channel width, apart from doubling by the availability of both sidewalls. Keeping channel width constant by SGTtype allows for continuation of scaling.
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Fig. 5. Mobility increase by strained-Si SOI MOSFET offers another promising scenario.
4.3. Other device structures or scaling scheme To offset the decrease due to scaling limit of gate dielectric, increasing mobility using SiGe structure or strained-Si [64] may also be advantageous for achieving a breakthrough. Note that SOI structure is essential in this case for suppressing the short-channel effect [65]. It is predicted theoretically that in strained-Si MOSFETs the saturation velocity can be increased for approximately two generations [66] (see Fig. 5).
5. Summary The current status and future directions of SOI technology has been discussed. While SOI has started to be practically used in a wide range of LSIs, scaling saturation is also a pressing issue. Two approaches have been stressed to overcome this difficulty. One is pursuing a scenario in which conventional scaling is continued, even if the scaling of gate dielectric film reaches saturation. In this case, short-channel resistance and availability of vertical channel structure, both of which are prominent features of SOI, play the important roles in obtaining high performance. The other approach is to utilize the flexibility of SOI and realize a wide range of functions which cannot be achieved by bulk Si technology. The latter is suitable for the coming SoC era, in
which not only memory and logic circuits, but also analog circuits, imagers and so on will be implemented on the same chip.
Acknowledgements The author would like to thank Mr. K. Inoh, Mr. Y. Katsumata, Dr. T. Fuse, Dr. T. Mizuno, Dr. S. Takagi, and Dr. H. Ishiuchi, all of Toshiba Corp., for a lot of suggestive discussions and comments. In addition, he is grateful to Dr. T. Masuhara, ASET, Dr. T. Sugii, Fujitsu Lab., and committee members who have contributed to the Semiconductor Technology Roadmap in Japan (STRJ) for useful discussions.
References [1] Shahidi GG, Ajmera A, Assaderaghi F, Bolam RJ, Leobandung E, Rausch W, et al. Partially-depleted SOI technology for digital logic. Tech Dig ISSCC 1999:426–7. [2] Kim YW, Park SB, Ko YG, Kim KI, Kim IK, Bae KJ, et al. A 0.25 lm 600 MHz 1.5 V SOI 64b ALPHA microprocessor. Tech Dig ISSCC 1999:432–3. [3] Tsai UC. A 1 GHz PA-RISC processor. Tech Dig ISSCC 2001:322–3. [4] Ueda K, Nii K, Wada Y, Takimoto I, Maeda S, Iwamatsu T, et al. A CAD-compatible SOI/CMOS gate array having
M. Yoshimi / Solid-State Electronics 46 (2002) 951–958
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18] [19]
[20]
[21]
body-fixed partially-depleted transistors. Tech Dig ISSCC 1997:288–9. Ohtomo Y, Yasuda S, Nogami M, Inoue J, Yamakoshi K, Sawada H, et al. A 50 Gb/s 8 8 ATM switch LSI using 0.25 lm CMOS/SIMOX. Tech Dig ISSCC 1997:154–5. Adan AO, Naka T, Kaneko S, Urabe D, Higashi K, Kagisawa A. Device Integration of a 0.35 lm CMOS on shallow SIMOX technology for high-speed and low-power applications. Proc IEEE Int SOI Conf 1996:116–7. Harada M, Tsukahara T, Yamada J. 0.5-1 V 2 GHz RF front-end circuits in CMOS/SIMOX. Tech Dig ISSCC 2000:378–9. Kumar M, Tan Y, Sin J, Shi L, Lau J. A 900 MHz SOI fully-integrated RF power amplifier for wireless transceivers. Tech Dig ISSCC 2000:382–3. Dekker R, Baltus P, van Deurzen M, Einden Wvd, Maas H, Wagemans A. An ultra low-power RF bipolar technology on glass. Tech Abst IEDM 1997:921–4. Eimori T, Oashi T, Kimura H, Yamaguchi Y, Iwamatasu T, Tsuruda T, et al. ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation. Tech Abst IEDM 1993:45–8. Koh Y-H, Oh M-R, Lee J-W, Yang J-W, Lee W-C, Park C-K, et al. 1 Giga Bit SOI DRAM with fully bulk compatible process and body-contacted SOI MOSFET structure. Tech Abst IEDM 1997:579–82. Park J-W, Kim Y-G, Kim I-K, Park K-C, Yoon H, Lee KC, et al. Performance characteristics of SOI DRAM for low-power application. Tech Dig ISSCC 1999:434–5. Fuse T, Oowaki Y, Yamada T, Kamoshida M, Ohta M, Shino T, et al. A 0.5 V 200 MHz 1-Stage 32b ALU using a body bias controlled SOI pass-gate logic. Tech Dig ISSCC 1997:286–7. Ebina A, Kadowaki T, Sato Y, Yamaguchi M. Ultra lowpower CMOS IC using partially-depleted SOI technology. Tech Abst CICC 2000:57–60. Suntharalingam V, Burke B, Cooper M, Yost D, Gouker P, Anthony M, et al. Monolithic 3.3V CCD/SOI-CMOS imager technology. Tech Abst IEDM 2000:697–700. Zheng X, Wrigley C, Yang G, Pain B. High responsivity CMOS imager pixel implemented in SOI technology. Proc IEEE Int SOI Conf 2000:138–9. Hirano Y, Matsumoto T, Maeda S, Iwamatsu T, Kunikiyo T, Nii K, et al. Impact of 0.10 lm SOI CMOS with bodytied hybrid trench isolation structure to break through the scaling crisis of silicon technology. Tech Abst IEDM 2000:467–70. International technology roadmap for semiconductors (ITRS), 1999. Deleonibus S, Caillat C, Guegan G, Heitzmann M, Nier ME, Tedesco S, et al. A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets. IEEE Elec Dev Lett 2000;21(4):173–5. Chau R, Kavalieros J, Roberds B, Schenker R, Lionberger D, Barlage D, et al. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays. Tech Abst IEDM 2000:45–8. Canada M, Akrout C, Cawthron D, Corr J, Geissler S, Houle R, et al. A 580 MHz RISC microprocessor in SOI. Tech Dig ISSCC 1999:430–1.
957
[22] Allen DH, Aipperspach AG, Cox DT, Phan NV, Storino SN. A 0.2 lm 1.8 V SOI 550 MHz 64b powerPC microprocessor with copper interconnects. Tech Dig ISSCC 1999:438–9. [23] Chau R, Arghavani R, Alavi M, Douglas D, Greason J, Green R, et al. Scalability of partially depleted SOI technology for sub-0.25 lm logic applications. Tech Abst IEDM 1997:591–4. [24] Leobandung E, Sherony M, Sleight J, Bolam R, Assaderaghi F, Wu S, et al. Scalability of SOI technology into 0.13 lm 1.2V CMOS generation. Tech Abst IEDM 1998:403–6. [25] Bernstein K, Rohrer NJ. SOI circuit design concepts. Dordrecht: Kluwer Academic Publishers; 2000. [26] Maeda S, Wada Y, Yamamoto K, Komurasaki H, Matsumoto T, Hirano Y, et al. Impact of 0.18 lm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded analog applications. Dig Symp VLSI Tech 2000:154–5. [27] Kodate J, Harada M, Tsukahara T. Suppression of substrate crosstalk in mixed analog-digital CMOS circuits by using high-resistivity SIMOX wafers. Ext Abst Int Conf Sol St Mat, 1999. p. 362–63. [28] Abe T, Saito S, Aihara K, Qu W, Hayamizu Y, Kimura M, et al. Creation of bonded SOI substrate with CZ silicon higher than 1000 Xcm in resistivity. Ext Abst Int Conf Sol St Dev Mat (SSDM), 1999. p. 356–57. [29] Harada M, Tsukahara T. Monolithic 2 GHz and 4–6 GHz low noise amplifiers fabricated on a SIMOX wafer. Ext Abst Int Conf Sol St Dev Mat (SSDM), 1997. p. 132–33. [30] Gotou H, Arimoto Y, Ozeki M, Imaoka K. Soft error rate of 64K SOI–DRAM. Tech Abst IEDM 1987:870–1. [31] Nishihara T, Ikeda N, Aozasa H, Miyazawa Y, Ochiai A. A buried capacitor DRAM cell with bonded SOI for 256M and 1 Gbit DRAMs. Tech Abst IEDM 1992:803–6. [32] Tanigawa T, Yoshino A, Koga H, Ohya S. Enhancement of data retention time for Giga-bit DRAMs using SIMOX technology. Dig Symp VLSI Tech 1994:37–8. [33] Nishihara T, Moriya H, Ikeda N, Aozasa H, Miyazawa Y. Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell. Dig Symp VLSI Technol 1994:39–40. [34] Kim H-S, Lee S-B, Choi D-U, Shim J-H, Lee K-C, Lee K-P, et al. A high performance 16M DRAM on a thin film SOI. Dig Symp VLSI Technol 1995:143–4. [35] Oashi T, Eimori T, Morishita F, Iwamatsu T, Yamaguchi Y, Okuda F, et al. 16Mb DRAM/SOI technologies for sub1V operation. Tech Abst IEDM 1996:609–12. [36] Cohen N, Sriram TS, Lelan N, Moyer D, Butler S, Flatley R. Soft error considerations for deep-submicron CMOS circuit applications. Tech Abst IEDM 1999:315–8. [37] Morishita F, Suma K, Hirose M, Tsuruda T, Tamaguchi Y, Eimori T, et al. Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM. Dig Symp VLSI Technol 1995:141–2. [38] Hannon R, Iyer SSK, Sadana D, Rice JP, Ho HL, Khan BA, et al. 0.25 lm merged bulk DRAM and SOI logic using patterned SOI. Dig Symp VLSI Technol 2000:66–7. [39] Tang X, Baie X, Bayot V, de Wiele FV, Colinge J-P. Fabrication, characterization and self-consistent simulation of an SOI nano flash memory device. Tech Abst IEDM 1999:919–21.
958
M. Yoshimi / Solid-State Electronics 46 (2002) 951–958
[40] Durlam M, Naji P, DeHerrera M, Tehrani S, Kerszykowski G, Kyler K. Nonvolatile RAM based on magnetic tunnel junction elements. Tech Dig ISSCC 2000:130–1. [41] Ghani T, Mistry K, Packan P, Thompson S, Stettler M, Tyagi S, et al. Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors. Dig Symp VLSI Tech 2000:174– 5. [42] Lee SJ, Luan HF, Bai WP, Lee CH, Jeon TS, Senzaki Y, et al. High quality ultra thin CVD HfO2 gate stack with poly-Si gate electrode. Tech Abst IEDM 2000:31–4. [43] Osten HJ, Liu JP, Gaworzewski P, Bugiel E, Zaumseil P. High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide. Tech Abst IEDM 2000:653–6. [44] Chin A, Wu YH, Chen SB, Liao CC, Chen WJ. High quality La2 O3 and Al2 O3 gate dielectrics with equivalent . Dig Symp VLSI Technol 2000:16– oxide thickness 5–10 A 7. [45] Qi W-J, Nieh R, Lee BH, Kang L, Jeon Y, Onishi K, et al. MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si. Tech Abst IEDM 1999:145–8. [46] Luan HF, Lee SJ, Lee CH, Song SC, Mao YL, Senzaki Y, et al. High quality Ta2 O5 gate dielectrics with Tox;eq < . Tech Abst IEDM 1999:141–4. 10 A [47] Buchanan DA, Gusev EP, Cartier E, Okorn-Schmidt H, Rim K, Gribelyuk MA, et al. 80 nm poly-silicon gated nFETs with ultra-thin Al2 O3 gate dielectric for ULSI applications. Tech Abst IEDM 2000:223–6. [48] Guo X, Wang X, Luo Z, Ma TP, Tamagawa T. High quality ultra-thin (1.5 nm) TiO2 /Si3 N4 gate dielectric for deep sub-micron CMOS technology. Tech Abst IEDM 1999:137–40. [49] Lee BH, Kang L, Qi W-J, Nieh R, Jeon Y, Onishi K, et al. Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application. Tech Abst IEDM 1999:133–6. [50] Kang L, Jeon Y, Onishi K, Lee BH, Qi W-J, Nieh R, et al. Single-layer thin HfO2 gate dielectric with nþ polysilicon gate. Dig Symp VLSI Technol 2000:44–5. [51] Kang L, Onishi K, Jeon Y, Lee BH, Kang C, Qi W-J, et al. MOSFET devices with polysilicon on single-layer HfO2 high-K dielectrics. Tech Abst IEDM 2000:35–8. [52] Enoki K. i-mode: the mobile internet service of the 21st century. Tech Dig ISSCC 2001:12–5. [53] Gelsinger PP. Microprocessors for the new millennium: challenges, opportunities, and new frontiers. Tech Dig ISSCC 2001:22–5.
[54] Colinge J-P. Slicon-on-insulator technology: material to VLSI. Dordrecht: Kluwer Academic Publishers; 1991. [55] Tanaka T, Horie H, Ando S, Hijiya S. Analysis of Pþ poly Si double-gate thin-film SOI MOSFETs. Tech Abst IEDM 1991:683–6. [56] Lee J-H, Taraschi G, Wei A, Langdo TA, Fitzgerald EA, Antoniadis DA. Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy. Tech Abst IEDM 1999:71–4. [57] Wong H-SP, Frank DJ, Solomon PM. Device design considerations for double-gate, ground-plane, and singlegated ultra-thin SOI MOSFET’s at the 25 nm channel length generation. Tech Abst IEDM 1998:407–10. [58] Takagi S, Koga J, Toriumi A. Mobility enhancement of SOI MOSFETs due to subband modulation in ultra-thin SOI films. Ext Abst Int Conf Sol St Dev Mat, 1997. p. 154. [59] Takagi S. Optimized design of the subband structure in MOS inversion layers for realizing high performance and low power Si MOSFETs. Int J High Speed Electron Syst 2000;10(1):155–70. [60] Hisamoto D, Kaga T, Kawamoto Y, Takeda E. A fully depleted lean-channel transistor (DELTA)—a novel vertical ultra thin SOI MOSFET. Tech Abst IEDM 1989: 833–6. [61] Hisamoto D, Lee W-C, Kedzierski J, Anderson E, Takeuchi H, Asano K, et al. A folded-channel MOSFET for deep-sub-tenth micron era. Tech Abst IEDM 1998:1032– 5. [62] Hergenrother JM, Monroe D, Klemens FP, Kornblit A, Weber GR, Mansfield WM, et al. The vertical replacament-gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length. Tech Abst IEDM 1999:75–8. [63] Takato H, Sunouchi K, Okabe N, Nitayama A, Hieda K, Horiuchi F, et al. High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs. Tech Abst IEDM 1988:222–5. [64] Welser J, Hoyt JL, Takagi S, Gibbons JF. Strain dependence of the performance enhancement in strained-Si n-MOSFETs. Tech Abst IEDM 1994:373–6. [65] Mizuno T, Takagi S, Sugiyama N, Koga J, Tezuka T, Usuda K, et al. High performance strained-Si p-MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology. Tech Abst IEDM 1999:934–6. [66] Hatakeyama T, Matsuzawa K, Takagi S. Impact of strained-Si channel on CMOS circuit performance under the sub-100 nm regime. Ext Abst Int Conf Sol St Dev Mat (SSDM), 2000. p. 62–3.