- Email: [email protected]
Current topics of silicon germanium devices
Applied Surface Science 254 (2008) 6158–6161
Contents lists available at ScienceDirect
Applied Surface Science journal homepage: www.elsevier.com/locate/apsusc
Current topics of silicon germanium devices Erich Kasper * University of Stuttgart, Institut fu¨r Halbleitertechnik, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
A R T I C L E I N F O
A B S T R A C T
Article history:
Silicon germanium (SiGe) is lattice mismatched to silicon by up to 4% depending on its Ge content. Basic investigations on strained layer growth, interface properties and deviation from equilibrium are done with SiGe/Si heterostructures. Early results are discussed in context with our recent understanding. The main focus of this overview is devoted to the micro- and optoelectronic devices which could be fabricated after solving or understanding the basic interface problems. This includes devices already in production, and those in emerging fields for inclusion in the next generation of integrated circuits, and a selection of device concepts with high merits to be proven in experiment. ß 2008 Published by Elsevier B.V.
Available online 18 March 2008 PACS: 73.21.Fg 73.40 Lq 73.61.Cw 78.66.Db Keywords: Lattice mismatch Strained layer Microelectronics Optoelectronics
1. Introduction Integrated circuits (IC) technology was driven the last 40 years by a steady shrinkage of the device dimensions by that enabling higher number of transistors on chip and higher performances per transistor. This trend is known as dimension scaling and scaling will continue the next decade or more. Long time the choice of materials concentrated on the very well-behaved ones like semiconductor silicon (Si), dielectrics silicon oxide (SiO2) and metal aluminium (Al). Dimension scaling has now reached a stage where more sophisticated material and interface systems are necessary to hold on the high speed of progress. In analogy to dimension scaling this is called material scaling [1]. Material scaling started with back end of line (BEOL) processing with copper interconnect/low-k interdielectrics of the multilayer metallization system. Nearer to the semiconductor is the replacement of the silicon dioxide or silicon oxinitride (Si ON) gate dielectrics by a high-k oxide like hafnium oxide which is announced [2] to get in production soon. The semiconductor body itself is considered to be improved by siliconbased heterostructures. The arrowhead of these heterostructures is given by silicon germanium (SiGe)/silicon interface junctions. In the following main part the material properties and their link with SiGe
* Tel.: +49 711 685 68002; fax: +49 711 685 68044. E-mail address: [email protected]. 0169-4332/$ – see front matter ß 2008 Published by Elsevier B.V. doi:10.1016/j.apsusc.2008.02.149
heterodevices are reviewed and discussed for the already proven applications, the emerging fields and some speculative concepts. 2. Proven advantages of SiGe heterodevices The spread out of commercially available circuits with SiGe/Si heterostructures started with the heterobipolartransistor (HBT) which proved tremendous speed advantages in bipolar and BiCMOS circuits. Integrated NPN transistors are now commercially available with around 200 GHz transit frequency ft [3,4] and maximum oscillation frequency fmax, the research is targeting toward the Terahertz realm (half THz are demonstrated) with NPN transistors and above 100 GHz for PNP transistors. This strained SiGe layer transistor proved the processing possibilities and reliability of SiGe/Si heterostructures. Silicon and germanium are both from the group IV of the periodic table of elements and therefore similar in many respects. The main differences are given by the lattice mismatch (about 4.2% between Si and Ge), the surface energy, the oxidation behaviour and the processing temperatures (the melting point of Ge (1180 K) is about a third lower than that of Si (1700 K)). The lattice mismatch causes either strain or results in generation of misfit dislocations at the interface. The thickness t at which strain is partly relaxed by the first misfit dislocations is called critical thickness tc. Its value is well defined only at the thermal equilibrium whereas at low growth temperatures (e.g. 550 8C) the nucleation and glide of dislocations is kinetically
E. Kasper / Applied Surface Science 254 (2008) 6158–6161
6159
Fig. 1. Stability regimes of lattice mismatched SiGe on Si.
impeded resulting in a rather large metastable region (Fig. 1). By lowering the growth temperature below 550 8C the critical thickness may be further increased, a region which we call ultrametastable [5]. The energetic stability and the reliability of strained SiGe heterostructures paved the way to a widespread, but rather unspectacular application in CMOS circuits [6–8]. The strain in CMOS circuits is easily obtained (in competition with other strain generating methods) with SiGe source/drain (S/D) regions (compressive strain for p-channels) and recently also with Si:C S/D regions (tensile strain for n-channels). Within a few years the attitude has changed from suspicious neglection to eager adoption of strained heterostructures in Si-based microelectronics. A first overview of the electronic properties of a heterostructures is delivered by the band line up (also called band ordering) between the two semiconductors with different bandgaps Eg (Si: Eg = 1.12 eV, Ge: Eg = 0.67 eV, 300 K). The SiGe/Si system is unique in that sense that depending on the strain situation the heterostructure type may be switched. For compressive strained SiGe on unstrained Si (Fig. 2) the nearly flat conduction band (between type I and type II) lets electrons easily cross the interface [9]. In tensile strained Si on unstrained SiGe (Fig. 2) the holes are collected on the SiGe side and the electrons on the large band gap Si side (type II interface). For a more detailed look also higher sub-bands and effective mass changes have to be considered. As an example the electron transport in a tensile strained Si channel [10–12] is considered. By the tensile biaxial strain the degeneracy of the electrons (all six cubic axis are energetically equal in the unstrained indirect semiconductor Si) is lifted with an energetic preference for the vertical direction (Fig. 3). It is easily recognized that for in-plane electron movement the low transverse effective mass is valid (in unstrained Si the resulting effective mass is a mixture of longitudinal and transverse masses). This leads to improved transport properties in channel direction whereas tunnelling in vertical direction (high longitudinal mass) is suppressed.
Fig. 2. Band ordering of SiGe/Si.
Fig. 3. Energy ellipsoids (E = const) as function of wave vector k for tensile strained Si. The symmetric ellipsoid for Skz is not shown (me, mt effective masses in longitudinal and transversal directions).
3. Emerging fields based on SiGe heterostructures Which are the emerging areas that will benefit from this newly gained confidence in heterostructures performance and reliability? Optoelectronic integration, manipulation of elastic strain with strain platforms and germanium-on-insulator (GOI) structures will satisfy the demand for increasing performance and fuel market prospects with system on chip (SOC) applications. Optoelectronic integration (Fig. 4) with microelectronics on Si is especially attractive on silicon-on-insulator (SOI) substrates where low loss optical waveguides, fast photodetectors and modulators and coupling structures for external lasers promise 100 Gb/s on chip systems for the near future. For an overlook see [13–15]. The detector speeds obtained now are around 40 GHz [16] with broad spectral responsivities from around 0.6 mm to 1.6 mm wavelength. A specific spectral sensitivity may be obtained by a resonant cavity enhanced photodiode (RCE PD) where a detecting heterostructure is embedded between an interferometric cavity [17]. First successes with moderately strained channels feed the desire to manipulate the strain in a wider range of magnitude, direction and sign [18]. Structures able to adjust the strain of SiGe and preferentially Si layers on top of a Si substrate are called strain platforms. A universal solution to strain platforms is given by the so-called virtual substrates which are composed of the thick Si substrate and an ultrathin (50–400 nm) strain relaxed buffer layer of a mismatched material system (e.g. SiGe) offering a surface lattice constant different from the underlying Si substrate. Our group [19] managed to adjust the lattice constant in ultrathin SiGe buffers by nucleation of misfit dislocation from supersaturated point defect concentrations. Supersaturation of point defects was
Fig. 4. Scheme of an integrated optoelectronic waveguide circuit on an SOI substrate [8].
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E. Kasper / Applied Surface Science 254 (2008) 6158–6161
Fig. 5. Virtual substrate with strained device layer. The ultrathin buffer was grown under point defect supersaturation.
controlled by Si ion impact (100–1000 eV energy) or very low growth temperature intervals (Fig. 5). Ge would be a very promising candidate [20] for the 30 nm and below CMOS generation because it is the only common semiconductor with a high-hole mobility. The leakage problem with the low band gap material Ge (which was mainly responsible that the first Ge transistors were replaced by Si) is strongly reduced by a dielectric insulation scheme (germanium-on-insulator: silicon substrate/ oxide layer/thin Ge layer). The GOI fabrication (Fig. 6) will benefit from virtual substrate quality and availability. 4. Speculative concepts Speculative concepts appeared which have to prove their functionality. A selection includes spintronics, resonance phase operation, charge injection transistor (CHINT) logic. What are the strongest arguments to push them? Spintronics in SiGe/Si gains profit from isotopically clean Si and Ge which reduces electron–nucleus spin interaction enormously. Both, Si and Ge possess isotopes which have zero nuclear spin.
Fig. 7. Island growth of a lattice mismatched SiGe on Si [26]. Growth temperature 750 8C.
These zero nuclear spin material will allow two-dimensional carrier transport with long spin conservation because of the lack of interaction with the nuclear spin. Resonance phase operation was demonstrated by our group with a modified HBT [21]. Generally it allows operation of a transistor far above the transit frequency within a window given by a phase delay of about 1808. This operation mode could be the key to electronic access to the THz regime. The basic principle is based on a high-phase delay of a signal (around 1808) without degrading the amplitude of the signal. The technical solution is based on a band gap engineered base for coherent transport [22] followed by a transit time region. The CHINT which allows specific logic operations [23] belongs to the real space transistor family [9] which uses transport property modulations for transistor function instead of the capacity modulation of the MOSFET. Therefore it could be superior to MOSFETs in ultralarge scale integration (ULSI) where the load of the capacity via long interconnects increasingly determine the system performance. For the SiGe/Si system the attractiveness for system on chip solutions using a CHINT/HBT integration scheme is enhanced by the same basic structure with pseudomorphic SiGe layers between Si [24]. 5. Historical remarks
Fig. 6. Germanium-on-insulator (GOI) fabrication with relaxed Ge on Si (virtual substrate) bonded to an oxid covered Si wafer. The lower wafer is cut, e.g. by H implantation/anneal (smart cut).
The SiGe/Si material system is now acknowledged as a model for strained layer configurations because the chemical similarity of the partner materials does not mask the pure strain influence. Systematic investigations of this heterostructure couple started in the 1970s. The author of this paper belonged to the first groups and it might be interesting to compare the not easily available old data [25–28] with our recent sophisticated understanding. With molecular beam epitaxy (MBE) SiGe layers and SiGe/Si superlattices have been grown at 750 8C. At this intermediate temperatures the growth mode switched to a Stranski–Krastanov one when the lattice mismatch was larger than 0.8%. Fig. 7 shows the electron micrograph of SiGe islands the appearance of which restricted the Ge content to below 20% for planar technology. These days the island growth is either suppressed by lower temperatures or utilized for quantum dot self-organization phenomena. Above a critical thickness the interface changed from a pseudomorphic one (same in-plane lattice spacing of substrate and compressed SiGe) to a strain relaxed one with misfit dislocations at the interface. Fig. 8 shows a freshly appearing orthogonal misfit dislocation network. At the crossings of the network the dislocations interact
E. Kasper / Applied Surface Science 254 (2008) 6158–6161
6161
tion and movement barriers. The concept of metastable strained layers pushed the SiGe device work in the 1980s when the decrease of growth temperature [29] to 550 8C and below enlarged the metastable regime considerably. 6. Conclusions SiGe heterodevices had a broad impact on our understanding of strained layer and superlattice interfaces and they added significantly to silicon-based concepts of quantum effect devices. Some of the earlier concepts proved their superiority in IC— manufacturing or will do it in emerging fields within the next generations of the manufacturing process. The manufacturing road map is strongly based on planar processing and deterministic pattern formation. Beyond CMOS manufacturing routes which utilize nonplanar elements and self-organization strategies could – and in my personal opinion will – replace the conventional processing by simple cost reasons. SiGe quantum dots and quantum wires with their strain induced tendency to selfarrangement and ordering are prime candidates for the building blocks in silicon-based alternative manufacturing. Acknowledgements
Fig. 8. Misfit dislocation network at the interface between a SiGe/Si superlattice and the Si substrate [26].
The cooperation with co-workers at the institute, here especially with M. Oehme is acknowledged. Special thanks to W. Spitzberg (editor: Wiss. Berichte AEG – Telefunken) who provided early editions of this journal. Financial support is acknowledged from DFG (SiGePIN/Forschergruppe 730), BMBF (SILEM) and EU (Nanosil).
References
Fig. 9. Dislocation spacing vs layer thickness for the different SiGe alloys [28].
because of forces between them depending on the Burgers vector directions. The broad background pattern is caused by slight surface and alloy concentration modulations, a phenomenon preceding the island formation. The dislocation spacing p decreases with increasing thickness (Fig. 9) up to full strain relaxation which is obtained at about 10 times the critical thickness. The strain relaxation was independently measured by X-ray diffraction. A comparison with equilibrium theories (e.g. v.d. Merwe, Matthews-Blakeslee) proved higher critical thicknesses and lower strain relaxations as expected. The brittle materials silicon or SiGe are kinetically limited by high-dislocation nuclea-
[1] H. Grimmeiss, Pers. Comm. [2] M.T. Bohr, R.S. Chau, T. Ghani, K. Mistry, The high-k solution, IEEE Spectrum (October) (2007) 23 (INT). [3] J. Eberhardt, E. Kasper, Solid-State Electron. 45 (2001), 2097. [4] J.D. Cressler, Silicon Heterostructure Handbook, CRC press, New York, 2006. [5] E. Kasper, A. Schuh, G. Bauer, B. Holla¨nder, H. Kibbel, J. Cryst. Growth 157 (1995) 68. [6] Y.C. Yeo, Semicond. Sci. Technol. 22 (2007) 5177. [7] H. Ohta, TEDM Tech. Dig. (2005) 247. [8] Y. Liu, Proc. Symp. VLSI Tech. (2007) 247. [9] E. Kasper, D.J. Paul, Silicon Quantum Integrated Circuits, Silicon–Germanium Heterostructure; Devices: Basics and Realisations, Springer-Verlag, Heidelberg, 2005. [10] S. Olsen, IEEE Trans.-ED 53 (2006) 2296. [11] G. Hadjisavvas, L. Tsetseris, S.T. Pantelides, IEEE-EDL 28 (2007) 1018. [12] J.-S. Wang, P.-N. Chen, C.-H. Shih, C. Lien, P. Su, Y.-M. Sheu, D.Y.-S. Chao, K.-I. Goto, IEEE-EDL 28 (2007) 1040. [13] M. Oehme, J. Werner, E. Kasper, M. Jutzi, M. Berroth, Appl. Phys. Lett. 89 (2006) 071117. [14] W. Martienssen (Ed.), Semiconductor Quantum Structures, Optical Properties, Landolt–Boernstein, New Series, Group III, vol. 34, Springer, 2007 (Chapter 3). [15] M. Oehme, this volume. [16] M. Jutzi, M. Berroth, G. Wohl, M. Oehme, E. Kasper, IEEE Photonic Technol. Lett. 17 (2005) 1510. [17] J. Yu, E. Kasper, M. Oehme, Thin Solid Films 508 (2006) 396. [18] E. Kasper, K. Lyutovich, Properties of silicon germanium and SiGe: carbon, EMIS datareviews series 24, INSPEC (IEE), London, 2000. [19] K. Lyutovich, F. Ernst, E. Kasper, M. Bauer, M. Oehme, Solid State Phenom. 69/70 (1999) 179. [20] C. Claeys, E. Simoen, Germanium-based Technologies: from Materials to Devices, Elsevier, Amsterdam, 2007. [21] E. Kasper, J. Eberhardt, H. Jorke, J.-F. Luy, H. Kibbel, D.W. Dashiell, O.G. Schmidt, M. Stoffel, Solid-State Electron. 48 (2004) 837. [22] A.A. Grinberg, S. Luryi, IEEE Trans. ED-40 1537 (2003). [23] M. Mastrapasqua, C.A. King, P.R. Smith, M.R. Pinto, IEEE Trans. ED-43 1671 (1996). [24] E. Kasper, German Patent, 198 607 01 (1998). [25] E. Kasper, H.J. Herzog, H. Kibbel, Appl. Phys. 8 (1975) 199. [26] E. Kasper, H.J. Herzog, Wiss. Berichte AFG – Telefunken 49 (1976) 213. [27] E. Kasper, W. Pabst, Thin Solid Films 37 (1976) L5. [28] E. Kasper, H.J. Herzog, Thin Solid Films 38 (1977) 357. [29] Q. People, J.C. Bean, Appl. Phys. Lett. 49 (1986) 229.
Contents lists available at ScienceDirect
Applied Surface Science journal homepage: www.elsevier.com/locate/apsusc
Current topics of silicon germanium devices Erich Kasper * University of Stuttgart, Institut fu¨r Halbleitertechnik, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
A R T I C L E I N F O
A B S T R A C T
Article history:
Silicon germanium (SiGe) is lattice mismatched to silicon by up to 4% depending on its Ge content. Basic investigations on strained layer growth, interface properties and deviation from equilibrium are done with SiGe/Si heterostructures. Early results are discussed in context with our recent understanding. The main focus of this overview is devoted to the micro- and optoelectronic devices which could be fabricated after solving or understanding the basic interface problems. This includes devices already in production, and those in emerging fields for inclusion in the next generation of integrated circuits, and a selection of device concepts with high merits to be proven in experiment. ß 2008 Published by Elsevier B.V.
Available online 18 March 2008 PACS: 73.21.Fg 73.40 Lq 73.61.Cw 78.66.Db Keywords: Lattice mismatch Strained layer Microelectronics Optoelectronics
1. Introduction Integrated circuits (IC) technology was driven the last 40 years by a steady shrinkage of the device dimensions by that enabling higher number of transistors on chip and higher performances per transistor. This trend is known as dimension scaling and scaling will continue the next decade or more. Long time the choice of materials concentrated on the very well-behaved ones like semiconductor silicon (Si), dielectrics silicon oxide (SiO2) and metal aluminium (Al). Dimension scaling has now reached a stage where more sophisticated material and interface systems are necessary to hold on the high speed of progress. In analogy to dimension scaling this is called material scaling [1]. Material scaling started with back end of line (BEOL) processing with copper interconnect/low-k interdielectrics of the multilayer metallization system. Nearer to the semiconductor is the replacement of the silicon dioxide or silicon oxinitride (Si ON) gate dielectrics by a high-k oxide like hafnium oxide which is announced [2] to get in production soon. The semiconductor body itself is considered to be improved by siliconbased heterostructures. The arrowhead of these heterostructures is given by silicon germanium (SiGe)/silicon interface junctions. In the following main part the material properties and their link with SiGe
* Tel.: +49 711 685 68002; fax: +49 711 685 68044. E-mail address: [email protected]. 0169-4332/$ – see front matter ß 2008 Published by Elsevier B.V. doi:10.1016/j.apsusc.2008.02.149
heterodevices are reviewed and discussed for the already proven applications, the emerging fields and some speculative concepts. 2. Proven advantages of SiGe heterodevices The spread out of commercially available circuits with SiGe/Si heterostructures started with the heterobipolartransistor (HBT) which proved tremendous speed advantages in bipolar and BiCMOS circuits. Integrated NPN transistors are now commercially available with around 200 GHz transit frequency ft [3,4] and maximum oscillation frequency fmax, the research is targeting toward the Terahertz realm (half THz are demonstrated) with NPN transistors and above 100 GHz for PNP transistors. This strained SiGe layer transistor proved the processing possibilities and reliability of SiGe/Si heterostructures. Silicon and germanium are both from the group IV of the periodic table of elements and therefore similar in many respects. The main differences are given by the lattice mismatch (about 4.2% between Si and Ge), the surface energy, the oxidation behaviour and the processing temperatures (the melting point of Ge (1180 K) is about a third lower than that of Si (1700 K)). The lattice mismatch causes either strain or results in generation of misfit dislocations at the interface. The thickness t at which strain is partly relaxed by the first misfit dislocations is called critical thickness tc. Its value is well defined only at the thermal equilibrium whereas at low growth temperatures (e.g. 550 8C) the nucleation and glide of dislocations is kinetically
E. Kasper / Applied Surface Science 254 (2008) 6158–6161
6159
Fig. 1. Stability regimes of lattice mismatched SiGe on Si.
impeded resulting in a rather large metastable region (Fig. 1). By lowering the growth temperature below 550 8C the critical thickness may be further increased, a region which we call ultrametastable [5]. The energetic stability and the reliability of strained SiGe heterostructures paved the way to a widespread, but rather unspectacular application in CMOS circuits [6–8]. The strain in CMOS circuits is easily obtained (in competition with other strain generating methods) with SiGe source/drain (S/D) regions (compressive strain for p-channels) and recently also with Si:C S/D regions (tensile strain for n-channels). Within a few years the attitude has changed from suspicious neglection to eager adoption of strained heterostructures in Si-based microelectronics. A first overview of the electronic properties of a heterostructures is delivered by the band line up (also called band ordering) between the two semiconductors with different bandgaps Eg (Si: Eg = 1.12 eV, Ge: Eg = 0.67 eV, 300 K). The SiGe/Si system is unique in that sense that depending on the strain situation the heterostructure type may be switched. For compressive strained SiGe on unstrained Si (Fig. 2) the nearly flat conduction band (between type I and type II) lets electrons easily cross the interface [9]. In tensile strained Si on unstrained SiGe (Fig. 2) the holes are collected on the SiGe side and the electrons on the large band gap Si side (type II interface). For a more detailed look also higher sub-bands and effective mass changes have to be considered. As an example the electron transport in a tensile strained Si channel [10–12] is considered. By the tensile biaxial strain the degeneracy of the electrons (all six cubic axis are energetically equal in the unstrained indirect semiconductor Si) is lifted with an energetic preference for the vertical direction (Fig. 3). It is easily recognized that for in-plane electron movement the low transverse effective mass is valid (in unstrained Si the resulting effective mass is a mixture of longitudinal and transverse masses). This leads to improved transport properties in channel direction whereas tunnelling in vertical direction (high longitudinal mass) is suppressed.
Fig. 2. Band ordering of SiGe/Si.
Fig. 3. Energy ellipsoids (E = const) as function of wave vector k for tensile strained Si. The symmetric ellipsoid for Skz is not shown (me, mt effective masses in longitudinal and transversal directions).
3. Emerging fields based on SiGe heterostructures Which are the emerging areas that will benefit from this newly gained confidence in heterostructures performance and reliability? Optoelectronic integration, manipulation of elastic strain with strain platforms and germanium-on-insulator (GOI) structures will satisfy the demand for increasing performance and fuel market prospects with system on chip (SOC) applications. Optoelectronic integration (Fig. 4) with microelectronics on Si is especially attractive on silicon-on-insulator (SOI) substrates where low loss optical waveguides, fast photodetectors and modulators and coupling structures for external lasers promise 100 Gb/s on chip systems for the near future. For an overlook see [13–15]. The detector speeds obtained now are around 40 GHz [16] with broad spectral responsivities from around 0.6 mm to 1.6 mm wavelength. A specific spectral sensitivity may be obtained by a resonant cavity enhanced photodiode (RCE PD) where a detecting heterostructure is embedded between an interferometric cavity [17]. First successes with moderately strained channels feed the desire to manipulate the strain in a wider range of magnitude, direction and sign [18]. Structures able to adjust the strain of SiGe and preferentially Si layers on top of a Si substrate are called strain platforms. A universal solution to strain platforms is given by the so-called virtual substrates which are composed of the thick Si substrate and an ultrathin (50–400 nm) strain relaxed buffer layer of a mismatched material system (e.g. SiGe) offering a surface lattice constant different from the underlying Si substrate. Our group [19] managed to adjust the lattice constant in ultrathin SiGe buffers by nucleation of misfit dislocation from supersaturated point defect concentrations. Supersaturation of point defects was
Fig. 4. Scheme of an integrated optoelectronic waveguide circuit on an SOI substrate [8].
6160
E. Kasper / Applied Surface Science 254 (2008) 6158–6161
Fig. 5. Virtual substrate with strained device layer. The ultrathin buffer was grown under point defect supersaturation.
controlled by Si ion impact (100–1000 eV energy) or very low growth temperature intervals (Fig. 5). Ge would be a very promising candidate [20] for the 30 nm and below CMOS generation because it is the only common semiconductor with a high-hole mobility. The leakage problem with the low band gap material Ge (which was mainly responsible that the first Ge transistors were replaced by Si) is strongly reduced by a dielectric insulation scheme (germanium-on-insulator: silicon substrate/ oxide layer/thin Ge layer). The GOI fabrication (Fig. 6) will benefit from virtual substrate quality and availability. 4. Speculative concepts Speculative concepts appeared which have to prove their functionality. A selection includes spintronics, resonance phase operation, charge injection transistor (CHINT) logic. What are the strongest arguments to push them? Spintronics in SiGe/Si gains profit from isotopically clean Si and Ge which reduces electron–nucleus spin interaction enormously. Both, Si and Ge possess isotopes which have zero nuclear spin.
Fig. 7. Island growth of a lattice mismatched SiGe on Si [26]. Growth temperature 750 8C.
These zero nuclear spin material will allow two-dimensional carrier transport with long spin conservation because of the lack of interaction with the nuclear spin. Resonance phase operation was demonstrated by our group with a modified HBT [21]. Generally it allows operation of a transistor far above the transit frequency within a window given by a phase delay of about 1808. This operation mode could be the key to electronic access to the THz regime. The basic principle is based on a high-phase delay of a signal (around 1808) without degrading the amplitude of the signal. The technical solution is based on a band gap engineered base for coherent transport [22] followed by a transit time region. The CHINT which allows specific logic operations [23] belongs to the real space transistor family [9] which uses transport property modulations for transistor function instead of the capacity modulation of the MOSFET. Therefore it could be superior to MOSFETs in ultralarge scale integration (ULSI) where the load of the capacity via long interconnects increasingly determine the system performance. For the SiGe/Si system the attractiveness for system on chip solutions using a CHINT/HBT integration scheme is enhanced by the same basic structure with pseudomorphic SiGe layers between Si [24]. 5. Historical remarks
Fig. 6. Germanium-on-insulator (GOI) fabrication with relaxed Ge on Si (virtual substrate) bonded to an oxid covered Si wafer. The lower wafer is cut, e.g. by H implantation/anneal (smart cut).
The SiGe/Si material system is now acknowledged as a model for strained layer configurations because the chemical similarity of the partner materials does not mask the pure strain influence. Systematic investigations of this heterostructure couple started in the 1970s. The author of this paper belonged to the first groups and it might be interesting to compare the not easily available old data [25–28] with our recent sophisticated understanding. With molecular beam epitaxy (MBE) SiGe layers and SiGe/Si superlattices have been grown at 750 8C. At this intermediate temperatures the growth mode switched to a Stranski–Krastanov one when the lattice mismatch was larger than 0.8%. Fig. 7 shows the electron micrograph of SiGe islands the appearance of which restricted the Ge content to below 20% for planar technology. These days the island growth is either suppressed by lower temperatures or utilized for quantum dot self-organization phenomena. Above a critical thickness the interface changed from a pseudomorphic one (same in-plane lattice spacing of substrate and compressed SiGe) to a strain relaxed one with misfit dislocations at the interface. Fig. 8 shows a freshly appearing orthogonal misfit dislocation network. At the crossings of the network the dislocations interact
E. Kasper / Applied Surface Science 254 (2008) 6158–6161
6161
tion and movement barriers. The concept of metastable strained layers pushed the SiGe device work in the 1980s when the decrease of growth temperature [29] to 550 8C and below enlarged the metastable regime considerably. 6. Conclusions SiGe heterodevices had a broad impact on our understanding of strained layer and superlattice interfaces and they added significantly to silicon-based concepts of quantum effect devices. Some of the earlier concepts proved their superiority in IC— manufacturing or will do it in emerging fields within the next generations of the manufacturing process. The manufacturing road map is strongly based on planar processing and deterministic pattern formation. Beyond CMOS manufacturing routes which utilize nonplanar elements and self-organization strategies could – and in my personal opinion will – replace the conventional processing by simple cost reasons. SiGe quantum dots and quantum wires with their strain induced tendency to selfarrangement and ordering are prime candidates for the building blocks in silicon-based alternative manufacturing. Acknowledgements
Fig. 8. Misfit dislocation network at the interface between a SiGe/Si superlattice and the Si substrate [26].
The cooperation with co-workers at the institute, here especially with M. Oehme is acknowledged. Special thanks to W. Spitzberg (editor: Wiss. Berichte AEG – Telefunken) who provided early editions of this journal. Financial support is acknowledged from DFG (SiGePIN/Forschergruppe 730), BMBF (SILEM) and EU (Nanosil).
References
Fig. 9. Dislocation spacing vs layer thickness for the different SiGe alloys [28].
because of forces between them depending on the Burgers vector directions. The broad background pattern is caused by slight surface and alloy concentration modulations, a phenomenon preceding the island formation. The dislocation spacing p decreases with increasing thickness (Fig. 9) up to full strain relaxation which is obtained at about 10 times the critical thickness. The strain relaxation was independently measured by X-ray diffraction. A comparison with equilibrium theories (e.g. v.d. Merwe, Matthews-Blakeslee) proved higher critical thicknesses and lower strain relaxations as expected. The brittle materials silicon or SiGe are kinetically limited by high-dislocation nuclea-
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