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DC-to-RF dispersion effects in GaAs- and GaN-based heterostructure FETs: performance and reliability issues
Microelectronics Reliability 45 (2005) 1585–1592 www.elsevier.com/locate/microrel
Invited Paper
DC-to-RF dispersion effects in GaAs- and GaN-based heterostructure FETs: performance and reliability issues G. Verzellesia, *, G. Meneghessob, A. Chinia, E. Zanonib, C. Canalia a
Università di Modena e Reggio Emilia, Dipartimento di Ingegneria dell’Informazione, via Vignolese 905, 41100 Modena, Italy b Università di Padova, Dipartimento di Ingegneria dell’Informazione, via Gradenigo 6/a, 35131 Padova, Italy
Abstract The performance and reliability implications of DC-to-RF dispersion effects are addressed. The proposed physical explanations and technological counteractions are reviewed. GaAs- and GaN-based FET technologies are considered, trying to point out both similar and peculiar aspects. Ó 2005 Elsevier Ltd. All rights reserved. 1. Introduction Trap-induced, DC-to-RF dispersion phenomena, including gate- and drain-lag effects, low-frequency dispersion of transconductance and output conductance, pulsed and RF drain-current collapse, still represent a serious limitation for the performance of field-effect transistors (FETs) based on compound semiconductors. The main application of these transistors is the power amplification at microwave frequencies. In this respect, the most detrimental aspect of dispersion effects is the associated compression of the maximum allowable drain-current and drain-source-voltage RF swings, which in turn results in degradation of RF output power and power-added efficiency (PAE). Moreover, in the presence of surface-trap-related dispersion effects, a trade-off generally exists between RF output power and breakdown voltage, thus hampering high-voltage operation, that would otherwise be highly desirable for the advantages it can
bring in terms of reduced gate periphery and therefore higher device impedances and extended bandwidths. DC-to-RF dispersion effects are also linked to reliability: they are worsened by hot-electron stress as a result of trap generation and/or trapped charge accumulation, and they can therefore be adopted as monitors of device degradation and studied to infer information about degradation mechanisms. This paper addresses DC-to-RF dispersion effects affecting GaAs- and GaN-based FETs. The work is organized as follows. In Section 2, the various dispersion effects are defined and the limitations imposed to the FET performance are analyzed and put in relation with each other. The different physical mechanisms proposed in the literature to explain DCto-RF dispersion are reviewed in Section 3. Reliability implications of DC-to-RF dispersion effects are addressed in Section 4. The most important technological solutions adopted to limit their impact on FET performance are taken into consideration in Section 5. Conclusions are drawn in Section 6.
* Corresponding author. [email protected] Tel: +39 059 205 6160; Fax: +39 059 205 6160. 0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.064
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2. Performance limitations DC-to-RF dispersion effects are a set of intercorrelated phenomena, each having his own definition corresponding to the specific experimental setup that can adopted to identify it and to assess its impact on device performance.
of this type are attributed to the prevailing effect of surface traps. The behaviour shown in Figs. 2 and 3 is however not the only possible one, as one could instead have observed an immediate ID response exceeding the final DC level, followed by slow ID decay. The latter behaviour is generally ascribed to the presence of bulk traps in any of the device layers present under the gate. It can for instance be observed in the presence of DX centers in the AlGaAs barrier layers of GaAs HEMTs.
Fig. 1. Typical experimental setup for gate-lag (left) and drain-lag (right) measurements.
∆Lg1 = 0.1 µm
∆Lg1 = 0 µm
∆Lg1 = 0.23 µm VGS,OFF = - 2V
VDD = 2V VGS,OFF = - 2V ∆Lg1 = 0 µm 0.1 µm
0.8 0.6 0.4 0.2
- 3V 1.0
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92 94 Time [ms]
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Fig. 2. ID vs time waveforms measured from AlGaAs-GaAs HFETs having different gate-drain and gate-source ungated recess widths (∆Lg1 = 0, 0.1µm, and 0.23 µm) in response to a VGS pulse for different off-state VGS values (VGS,OFF) at VDD=2 V. After [4].
The gate lag is a “slow” (i.e., not related with the intrinsic bandwidth limitation of the device) transient which can be observed when recording the draincurrent (ID) waveform obtained in response to an abrupt change in the gate-source voltage (VGS) at constant drain-source voltage (VDS) [1-3]. Fig. 1(left) shows a typical experimental setup. The load resistance is generally chosen small (in the order of some Ω’s), so that VDS changes induced by the ID variation can be neglected (i.e. an almost vertical load line is adopted). Figs. 2 and 3 show the results of gate-lag measurements from an AlGaAs-GaAs doped-channel HFET [4] and from an AlGaN-GaN HEMT [5], respectively. As can be noted, in both cases the ID waveform measured after the application of the turn-on step consists of two components: a prompt increase (taking place simultaneously with the VGS rise) but accounting for only a fraction of the total ID change, followed by a slow increase (the gate lag!) towards the final DC level. As it will be clear after Section 3, gate-lag waveforms
Fig. 3. ID vs time waveforms measured from an AlGaN-GaN HEMT in response to a VGS pulse. After [5].
Strictly correlated with gate lag is the discrepancy between DC and pulsed output characteristics, when the latter are obtained by pulsing VGS from an off-state voltage to on-state values at (almost) constant VDS [same setup of Fig.1(left)] and by sampling the ID values during on-state phase of the VGS pulse. Figs. 4 and 5 show results of this kind of measurements obtained from the same two devices considered in Fig. 2 and 3, respectively. As could easily be expected, the similar gate-lag behaviour of Figs. 2 and 3 reflects into a similar DC-to-pulsed discrepancy in Figs. 4 and 5. In particular, pulsed ID curves are lower, for any given VGS, than the corresponding DC curves. This effect is often referred to as RF current collapse or even simply current collapse, even though the first name should more properly be reserved for actual RF measurements and the latter has historically been adopted to define the DC ID reduction resulting from the application of a high VDS bias [6]. Of course, if the gate-lag waveforms
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were of the opposite type to that shown in Figs. 2 and 3 (i.e. if they were characterized by a prompt ID overshoot followed by a slow ID decay), the DC-topulsed discrepancy would be reversed too (i.e. the pulsed ID values would exceed the corresponding DC values). In this case, no “current collapse” of pulsed characteristics (with respect to DC ones) takes place. HFET ∆Lg1 = 0.23 µm
Drain Current [mA]
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Fig. 4. DC and pulsed output characteristics obtained from an AlGaAs-GaAs HFET (same as that having ∆Lg1 = 0.23 µm in Fig. 2) by pulsing VGS from -3 V (off-state) to 0 V for different pulse widths.
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(gm) frequency dispersion [7-9]. It is measured by superimposing a small-amplitude, sinusoidal signal to the DC gate bias and by monitoring the resulting AC ID signal as a function frequency. Fig. 6 shows typical gm dispersion curves measured from the same AlGaAsGaAs HFET of Figs. 2 and 4. A clear, downward dispersion of gm at increasing frequency can be noted, meaning that ID changes measured at low frequency (corresponding to long times after VGS step application in the time-domain response) is larger than that achievable at high frequency (corresponding to short times after the VGS step in the domain-time response). Relying on the same basic reasoning, it is easy to conclude that upward gm dispersion curves are instead correlated with a DX-center-like gate-lag behaviour. Dually to the gate-lag concept, drain lag is defined as the “slow” transient which can be detected when measuring the ID waveform in response to the application of a step change in VDS at constant VGS [10,11]. Fig. 1(right) reports a sketch of a typical drainlag experimental setup, while Fig. 7 shows drain-lag measurements obtained from an AlGaN-GaN HEMT (same device of Figs. 3 and 5). As can be noted, the ID waveform in response to a positive VDS step is composed by a prompt response exceeding the final DC value followed a slow decay (similarly to what happens for DX-center-like gate lag). In spite drain-lag effects are conventionally attributed to traps located in the buffer/substrate layers underlying the device channel [6], it has been shown that they can be induced by surface traps as well [5,12] (see Section 3).
Fig. 5. DC and pulsed output characteristics obtained from an AlGaNGaN HEMT by pulsing VGS from -5 V (off-state) to 0 V for different pulse widths. After [5].
T=70°C
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Fig. 6. gm vs frequency curves measured at different temperatures from an AlGaAs-GaAs HFET. The device is biased at VGS= 0 V and VDS=2 V. A 100-mV peak-to-peak sinusoidal signal is superimposed to the DC gate bias. The inset shows the Arrhenius plot of the critical frequencies (fT) corresponding to inflection points. After [4].
Another dispersion effect that emerges in response to VGS modulation is the so-called transconductance
Fig. 7. ID vs time waveforms measured from an AlGaN-GaN HEMT in response to a VDS pulse. After [5].
The drain-lag effect controls the FET pulsed characteristics when the latter are obtained by pulsing VDS (at constant VGS). Fig. 8 shows such pulsed characteristics measured from the same device of Fig. 7. Since the ID values measured shortly after the VDSstep application are higher than the corresponding DC
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values (see Fig. 7), then the pulsed I-V curves lie above the corresponding DC characteristics. The drain lag is also at the origin of the frequency dispersion of the output conductance (go). Upward go dispersion curves are in particular correlated with the drain-lag behaviour shown in Fig. 7 and the corresponding VDS-pulsing-mode characteristics of Fig. 8.
Fig. 8. DC and pulsed output characteristics at VGS=0 V obtained from an AlGaN-GaN HEMT by pulsing VDS from 0 V to the x-axis value at different pulse widths. After [5].
Pulsed characteristics can also be measured by pulsing VGS again with the setup shown in Fig. 1(left) but using a relatively large load resistance , resulting in an oblique load line like that typically adopted for RF power operation. In this case, the VDS changes induced by the ID voltage drop on the load resistance can not be neglected, i.e. both VGS and VDS undergo significant excursions during the pulse cycle. Both VGS and VDS changes can therefore contribute to the delayed ID increase, i.e. the “current collapse” can be due to the combined effect of gate- and drain-lag effects. With respect to the main application of GaAs- and GaN-base FETs, i.e. the power amplification at microwave and millimiter-wave frequencies, the most detrimental aspect of dispersion effects like those shown in Figs. 2-5 is the associated compression of the maximum allowable ID and VDS RF swings (this effect being more properly referred to as RF current collapse). As a result, the RF output power can be significantly smaller than that ideally achievable by a FET having no dispersion (and that can be calculated from the device DC characteristics). Since gate lag is induced by surface traps and drain lag can be caused by either surface or substrate/buffer traps and since both effects contribute to the current collapse during RF operation, it descends that RF current collapse can be due to either surface or substrate/buffer traps or to a combination of the two trap types.
3. Physical mechanisms As far as the physical origin of DC-to-RF dispersion effects is concerned, a general consensus exists about these being induced by deep-level traps. The latter may be located virtually in any device layer, at any interlayer interface, as well as at the exposed or (more commonly) passivated device surface. Thanks to the long-established epitaxial growth techniques of GaAs technologies and to vertical structures which effectively isolates the device active layers from the starting material substrate, dispersion effects in GaAs-based FETs are generally induced (if at all present) by surface traps. Owing to the lower maturity of GaN technologies, dispersion effects in GaN FETs, besides being generally more pronounced than those characterizing GaAs-based devices, can in principle be originated from all of the diversely located traps. Current-collapse phenomena and related RF power compression have however been put into relation with only two of the possible trap locations: (1) bulk traps located in the buffer or substrate layers directly underlying the FET channel and (2) surface traps at the exposed or passivated surface. These two are therefore the sources of DC-to-RF dispersion effects that must principally be taken into consideration, with relevance to both GaAs- and GaN-based FETs. 3.1. Substrate/buffer traps The way by which substrate/buffer traps impact the FET performance is well assessed: it involves the capture and emission of channel electrons in response to VDS changes. In particular, electrons injected in the substrate or buffer layers underlying the channel are captured by traps following the application of a positive VDS change, whereas they are emitted in response to a VDS decrease. As a result, ID decreases(increases) during the slow transients following a positive(negative) step change in VDS and drain-lag waveforms of the type shown in Fig. 7 are observed [13]. When the RF power operation along the load line is considered, it is therefore during the half cycle of the RF sweep in which VGS is increased (and owing to load-line constrain VDS is decreased) that drain lag results in delayed device turn-on and consequent RF ID collapse and output-power compression.
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3.2. Surface traps Surface traps are instead believed to make the gate-source and gate-drain surfaces act as “virtual” or “parasitic” gates, controlling the surface potential through changes in the trapped charge density and therefore modulating the conductance of the underlying channel access regions. As the gate and/or drain bias is changed abruptly, these virtual gates respond with the times characteristic of carrier capture/emission phenomena, thus leading to delayed ID switching [1420]. The specific physical mechanism behind surfacetrap-charge modulation is however still controversial and might be device- and/or technology-dependent. 3.2.1. Electron-trap model The explanation which is more conventionally accepted is that surface traps capture (emit) electrons which are provided (collected) by the gate metal or that transfer from gate to drain and source contacts and vice versa via surface conduction mechanisms [14-20]. In the latter case, surface charging/discharging can be modelled as a distributed R-C network connecting the gate to the drain and source contacts, where the resistive elements take into account surface conduction and capacitative ones describe the capacitance between surface and channel or charge storage into traps [14,21]. Within such a framework, gate and drain lag (and consequently the associated pulsed behaviour and RF current collapse phenomenon) are explained as follows. Any voltage change increasing the gate-source and/or gate-drain reverse bias (like a VGS decrease and/or a VDS increase) results in an enhancement of the surface electron leakage current, in an increase in the trapped electrons and therefore in ID slow decaying transients governed by electron capture. Conversely, any voltage change reducing the gate-source and/or gate-drain reverse bias (such as a VGS increase and/or a VDS decrease) leads to a reduced electron leakage current, to a decrease in the trapped electrons and thus it induces ID slow increasing transients governed by electron emission. 3.2.3. Hole-trap model Alternatively, it has been proposed that surface traps interact with holes attracted at the device surface
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by negatively-ionized levels and associated upward band bending, thereby forming a weakly-inverted surface layer. This hole-trap-based model was originally proposed on the basis of two-dimensional numerical device simulations of GaAs MESFETs [22,23] and subsequently tested against experimental data from AlGaAs-GaAs HFETs [4,12,24-26]. Intriguing experimental indications in favour of the hole-trap model in the latter devices are in particular: (i) the observed opposite dependence of gate-lag effects on temperature depending on whether the device is operated below or above the onset of channel impact ionization, pointing out that at least at high VDS surface traps interact dominantly with surface accumulated holes [4]; (ii) the light sensitivity of dispersion effects and its non-straightforward dependence on temperature, that, only within the framework of the hole-trap model, have a rather natural explanation descending from the temperature dependence of ionized trap concentration and surface hole density [25,26]. Within the framework of the hole-trap model, gateand drain-lag effects are explained as follows. Owing to the presence of deep-level traps with energy relatively close to the valance-band edge (and therefore behaving as hole traps), the device surface can be regarded as an effective p-type region electrically connected with the gate. The role of the doping of this p region is played by the trap density, while the free carrier charge is represented by the hole sheet forming at the surface. Now, any voltage change increasing the gate-source and/or gate-drain reverse bias (like a VGS decrease and/or a VDS increase) tends to deplete both sides of this p-n junction. In particular, it enhances the ionized trap density by detrapping holes from surface traps (the p side of the junction). This induces ID slow decaying transients governed by hole emission. Conversely, any voltage change reducing the gatesource and/or gate-drain reverse bias (such as a VGS increase and/or a VDS decrease) leads to weakened depletion, i.e. it reduces the ionized trap density, by inducing hole capture by surface traps. This leads to ID slow increasing transients governed by hole capture. It is evident that the hole-trap model is completely equivalent, from an electrical point of view, to the electron-trap-based one, the effect on channel conductivity and therefore on ID produced by electron capture or emission being the same as that induced by hole emission and capture, respectively. Regardless of the actual underlying mechanism, it is also clear from the above considerations that even
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surface traps can induce RF ID collapse and consequent output-power compression, as, during the positive halfcycle of the RF sweep, they delay the device turn-on as a combined effect of the simultaneous VGS increase and VDS decrease. 4. Reliability aspects It is widely known that hot electrons are one of the most important issues for the reliability of field-effect transistors. In the past two decades, following the example of studies in Si devices, hot-electron reliability has become one of the most important concerns for GaAs based HEMTs. What is commonly observed after hot-carrier degradation is an increase in the series resistances, a decrease in gm (sometimes accompanied by a threshold-voltage shift), the so-called breakdown walkout, the appearance of DC-to-RF dispersion effects or their worsening if they are already present in virgin devices. All these phenomena have been linked to electron injection and/or to trap generation in the region between gate and drain contacts in the barrier layer, in the buffer or substrate, and/or at the semiconductor/passivation interface and even under the gate region [27-32]. As a result of this, DC-to-RF dispersions effects can be adopted as monitors of hotelectron degradation and studied to infer information about physical mechanisms of degradation. In a work on hot-electron degradation of AlGaAsGaAs HFETs [33], it has been shown that additional information about the degradation mechanism can be inferred by correlating the typical hot-carrier degradation modes reported above with the changes induced by hot-electron stress on the impact-ionizationrelated, bell-shaped gate leakage current. The latter is expected to decrease at increasing hot-electron stress if the dominant degradation mechanism is the surface damage (either creation of surface traps or electron injection into surface traps or into passivation), the associated negative trapped charge increase attenuating the gate-drain peak electric field and reducing channel impact ionization (the same effect is at the origin of the breakdown walk-out, i.e. the increase in the off-state gate-drain breakdown voltage with increasing hotelectron stress). In case the gate-current bell is instead amplified by hot-electron stress (and the typical degradation modes related to surface damage, such as resistance series increase, gm peak degradation, as well as gate-lag enhancement are still observed), one must conclude that trap creation and/or electron injection must take place both at the surface and in the buffer
layer underlying the device channel. Numerical device simulations have shown that the simultaneous channel depletion from the surface and from the bottom squeezes the electron flow at the gate edge, increasing the local channel resistance and the electric field, hence the higher energy and impact ionization rate [33]. More recently, the attention on hot-electron issues passed to AlGaN/GaN HEMTs. Even if many analogies can be found with GaAs HEMTs, there are some aspects that make this issue in GaN HEMTs more problematic. First, in many cases, GaN HEMTs present significant dispersion effects even in “virgin” condition, i.e. before any hot-electron stress. Hotelectron stress induces or enhances these dispersion phenomena especially in unpassivated devices, while passivation of the device surface with SiN has a healthy effect on hot-electron degradation, diminishing the stress effect [34-37]. The observed degradation is sometimes not permanent and the original condition can be restored via UV lighting or with an unbiased room temperature storage. Second, in GaN HEMTs, the gate leakage current can not be used as a hotelectron indicator. In fact, in these devices, many parasitic contributions add to the gate leakage current, making hole generated by impact-ionization only a small portion of the total gate current.
5. Technological counteractions As already mentioned, a fundamental step towards to minimization of DC-to-RF dispersion effects has been done for GaAs- and, more recently, also for GaNbased technologies, thanks to the optimization of epitaxial growth techniques. As far as surface-induced dispersion effects are concerned, a technique that has proven to be very effective in minimizing them in both GaAs- and GaNbased FET technologies is SiN surface passivation [3437]. However, a trade-off generally exists between surface-related dispersion effects and breakdown voltage [15,38]. When the channel is off, surface traps are in fact negatively charged, which effectively reduces the electric field peak at the drain edge of the gate, resulting in a high gate-drain breakdown voltage. Since avoiding RF power compression requires surface-trap density to be minimized, a trade-off exists also between RF output power and breakdown voltage, ultimately hampering high-voltage operation, that would otherwise be highly desirable for the advantages it brings in terms of reduced gate periphery and
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therefore higher device impedances and extended bandwidths, as well as improved PAE. In GaAs-based devices, double-recess gate structures, with gate footprint defined by the inferior recess etch (and therefore characterized by as narrow as possible ungated surfaces) and doped cap layers screening the channel from the surface charge, has profitably been adopted to relax this trade-off, allowing gate-drain electric-field attenuation and dispersioneffect reduction to be achieved in the same device [15]. As far as GaN HEMTs are concerned, different solutions have been devised to achieve the goal of 2DEG screening from surface potential fluctuations induced by traps, including the introduction in the epitaxial structure of a thin GaN cap layer with [39] and without [40] overlying SiN passivation, as well as of a thick GaN cap with SiO2 recess sidewall coverage for gate leakage current minimization [41]. A major step towards dispersion-free GaN-based HEMTs has however been the recent introduction of the field-plate (also called field-modulating plate) into the FET structure. The field plate is essentially a MIS electrode that is located onto the surface passivation layer between the gate and the drain and is connected with the gate. The beneficial effect of the field plate on the FET power performance is twofold: 1) it reduces the electric field strength at the drain edge of the gate, thus increasing the gate-drain breakdown voltage; 2) it suppresses or strongly attenuates DC-to-RF dispersion effects thanks to more efficient surface-trap modulation and/or reduced electron injection into surface traps. Firstly applied to an AlGaAs-GaAs HFET [42], it is in AlGaN-GaN HEMTs that the field plate has yielded striking power performance improvements [43-47], allowing, in force of benefits 1) and 2) above, impressive RF output-power densities to be attained along with excellent PAE and power gain at high operating voltages.
6. Conclusions DC-to-RF dispersion effects are a set of intertwined phenomena induced by deep-level traps and still limiting the performance of both GaAs- and GaN-based power microwave FETs. Traps located at the device surface and in the buffer/substrate layer underlying the device channel are in particular responsible for the so-called RF current collapse and the associated RF output power compression. Dispersion effects are linked with hot-electron
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reliability, in that they are generally enhanced by hotelectron stress and represent therefore one of the most evident degradation modes of compoundsemiconductor microwave power FETs. Technological solutions that have been adopted also or exclusively to reduce dispersion effects to manageable levels include: surface dielectric passivation, double recess gate structures, surfacecharge control layers, field-plated gate structures. References [1] M. Rocchi, Physica B, 129, pp. 119-138, 1985. [2] J. M. Dumas, F. Garat, D. Lecrosnier, Electron. Lett., vol. 23, pp. 139-141, 1987. [3] R. Yeats et al., IEDM Tech. Dig., pp. 842-845, 1988. [4] G. Verzellesi et al., IEEE Trans. Electr. Dev., vol. 50(8), pp. 1733-1740, 2003. [5] G.Meneghesso et al., IEEE Trans. Electr. Dev., vol. 51(10), pp. 1554-1561, 2004. [6] S.C. Binari, P.B. Klein, T.E. Kazior, Proc. of the IEEE, vol. 90(6), pp. 1048-1058, 2002. [7] O. Wada, S. Yanagisawa, H. Takanashi, Jpn. J. Appl. Phys., vol. 12, no. 1, pp. 157-158, 1975. [8] P.H. Ladbrooke, S.R. Blight, IEEE Trans. Electr. Dev., vol. 35(3), pp. 257-267, 1988. [9] W. Kruppa, J.B. Boos, IEEE Trans. Electr. Dev., vol. 44(5), pp. 687-692, 1997. [10]W. Mickanin et al., Proc of GaAs IC Symp., pp. 211214, 1989. [11]N. Saysset et al., Proc. of ESREF’95, pp. 389-394, 1995. [12]A. Mazzanti et al., IEEE Electr. Dev. Lett., vol. 23(7), pp. 383-385, 2002. [13]S. C. Binary et al., IEEE Trans. Electron. Dev., vol. 48(3), pp. 465-471, 2001. [14]S.R. Blight, R.H. Wallis, H. Thomas, IEEE Trans. Electr. Dev., vol. 33(10), pp. 1447-1453, 1986. [15] J.C. Huang et al., IEEE Trans. Microwave Theory Tech., vol. 41(5), pp. 752-759, 1993. [16]V.R. Balakrishnan, V. Kumar, S. Ghosh, IEEE Trans. Electr. Dev., vol. 44(7), pp. 1060-1065, 1997. [17] K.J. Choi, J.-L. Lee, IEEE Trans. Electr. Dev., vol. 48(2), pp. 190-195, 2001. [18]R. Vetury et al., IEEE Trans. Electr. Dev., vol. 48(3), pp. 560-566, 2001. [19]E. Kohn et al., IEEE Trans. on Microwave Theory and Tech., vol. 51(2), pp. 634-642, 2003. [20]B.M. Green et al., IEEE Trans. on Microwave Theory and Tech., vol. 51(2), pp. 618-623, 2003. [21]J.P. Harrang et al., J. Appl. Phys., vol. 61, pp. 19311936, 1987. [22]S.-H. Lo, C.-P. Lee, IEEE Trans. Electr. Dev., vol. 41(9), pp. 1504-1512, 1994. [23]K. Horio, T. Yamada, IEEE Trans. Electr. Dev., vol. 46(4), pp. 648-655, 1999. [24]A. Cavallini et al., J. Appl. Phys., vol. 94, no. 8, pp.
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Invited Paper
DC-to-RF dispersion effects in GaAs- and GaN-based heterostructure FETs: performance and reliability issues G. Verzellesia, *, G. Meneghessob, A. Chinia, E. Zanonib, C. Canalia a
Università di Modena e Reggio Emilia, Dipartimento di Ingegneria dell’Informazione, via Vignolese 905, 41100 Modena, Italy b Università di Padova, Dipartimento di Ingegneria dell’Informazione, via Gradenigo 6/a, 35131 Padova, Italy
Abstract The performance and reliability implications of DC-to-RF dispersion effects are addressed. The proposed physical explanations and technological counteractions are reviewed. GaAs- and GaN-based FET technologies are considered, trying to point out both similar and peculiar aspects. Ó 2005 Elsevier Ltd. All rights reserved. 1. Introduction Trap-induced, DC-to-RF dispersion phenomena, including gate- and drain-lag effects, low-frequency dispersion of transconductance and output conductance, pulsed and RF drain-current collapse, still represent a serious limitation for the performance of field-effect transistors (FETs) based on compound semiconductors. The main application of these transistors is the power amplification at microwave frequencies. In this respect, the most detrimental aspect of dispersion effects is the associated compression of the maximum allowable drain-current and drain-source-voltage RF swings, which in turn results in degradation of RF output power and power-added efficiency (PAE). Moreover, in the presence of surface-trap-related dispersion effects, a trade-off generally exists between RF output power and breakdown voltage, thus hampering high-voltage operation, that would otherwise be highly desirable for the advantages it can
bring in terms of reduced gate periphery and therefore higher device impedances and extended bandwidths. DC-to-RF dispersion effects are also linked to reliability: they are worsened by hot-electron stress as a result of trap generation and/or trapped charge accumulation, and they can therefore be adopted as monitors of device degradation and studied to infer information about degradation mechanisms. This paper addresses DC-to-RF dispersion effects affecting GaAs- and GaN-based FETs. The work is organized as follows. In Section 2, the various dispersion effects are defined and the limitations imposed to the FET performance are analyzed and put in relation with each other. The different physical mechanisms proposed in the literature to explain DCto-RF dispersion are reviewed in Section 3. Reliability implications of DC-to-RF dispersion effects are addressed in Section 4. The most important technological solutions adopted to limit their impact on FET performance are taken into consideration in Section 5. Conclusions are drawn in Section 6.
* Corresponding author. [email protected] Tel: +39 059 205 6160; Fax: +39 059 205 6160. 0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.064
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2. Performance limitations DC-to-RF dispersion effects are a set of intercorrelated phenomena, each having his own definition corresponding to the specific experimental setup that can adopted to identify it and to assess its impact on device performance.
of this type are attributed to the prevailing effect of surface traps. The behaviour shown in Figs. 2 and 3 is however not the only possible one, as one could instead have observed an immediate ID response exceeding the final DC level, followed by slow ID decay. The latter behaviour is generally ascribed to the presence of bulk traps in any of the device layers present under the gate. It can for instance be observed in the presence of DX centers in the AlGaAs barrier layers of GaAs HEMTs.
Fig. 1. Typical experimental setup for gate-lag (left) and drain-lag (right) measurements.
∆Lg1 = 0.1 µm
∆Lg1 = 0 µm
∆Lg1 = 0.23 µm VGS,OFF = - 2V
VDD = 2V VGS,OFF = - 2V ∆Lg1 = 0 µm 0.1 µm
0.8 0.6 0.4 0.2
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92 94 Time [ms]
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Fig. 2. ID vs time waveforms measured from AlGaAs-GaAs HFETs having different gate-drain and gate-source ungated recess widths (∆Lg1 = 0, 0.1µm, and 0.23 µm) in response to a VGS pulse for different off-state VGS values (VGS,OFF) at VDD=2 V. After [4].
The gate lag is a “slow” (i.e., not related with the intrinsic bandwidth limitation of the device) transient which can be observed when recording the draincurrent (ID) waveform obtained in response to an abrupt change in the gate-source voltage (VGS) at constant drain-source voltage (VDS) [1-3]. Fig. 1(left) shows a typical experimental setup. The load resistance is generally chosen small (in the order of some Ω’s), so that VDS changes induced by the ID variation can be neglected (i.e. an almost vertical load line is adopted). Figs. 2 and 3 show the results of gate-lag measurements from an AlGaAs-GaAs doped-channel HFET [4] and from an AlGaN-GaN HEMT [5], respectively. As can be noted, in both cases the ID waveform measured after the application of the turn-on step consists of two components: a prompt increase (taking place simultaneously with the VGS rise) but accounting for only a fraction of the total ID change, followed by a slow increase (the gate lag!) towards the final DC level. As it will be clear after Section 3, gate-lag waveforms
Fig. 3. ID vs time waveforms measured from an AlGaN-GaN HEMT in response to a VGS pulse. After [5].
Strictly correlated with gate lag is the discrepancy between DC and pulsed output characteristics, when the latter are obtained by pulsing VGS from an off-state voltage to on-state values at (almost) constant VDS [same setup of Fig.1(left)] and by sampling the ID values during on-state phase of the VGS pulse. Figs. 4 and 5 show results of this kind of measurements obtained from the same two devices considered in Fig. 2 and 3, respectively. As could easily be expected, the similar gate-lag behaviour of Figs. 2 and 3 reflects into a similar DC-to-pulsed discrepancy in Figs. 4 and 5. In particular, pulsed ID curves are lower, for any given VGS, than the corresponding DC curves. This effect is often referred to as RF current collapse or even simply current collapse, even though the first name should more properly be reserved for actual RF measurements and the latter has historically been adopted to define the DC ID reduction resulting from the application of a high VDS bias [6]. Of course, if the gate-lag waveforms
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were of the opposite type to that shown in Figs. 2 and 3 (i.e. if they were characterized by a prompt ID overshoot followed by a slow ID decay), the DC-topulsed discrepancy would be reversed too (i.e. the pulsed ID values would exceed the corresponding DC values). In this case, no “current collapse” of pulsed characteristics (with respect to DC ones) takes place. HFET ∆Lg1 = 0.23 µm
Drain Current [mA]
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Fig. 4. DC and pulsed output characteristics obtained from an AlGaAs-GaAs HFET (same as that having ∆Lg1 = 0.23 µm in Fig. 2) by pulsing VGS from -3 V (off-state) to 0 V for different pulse widths.
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(gm) frequency dispersion [7-9]. It is measured by superimposing a small-amplitude, sinusoidal signal to the DC gate bias and by monitoring the resulting AC ID signal as a function frequency. Fig. 6 shows typical gm dispersion curves measured from the same AlGaAsGaAs HFET of Figs. 2 and 4. A clear, downward dispersion of gm at increasing frequency can be noted, meaning that ID changes measured at low frequency (corresponding to long times after VGS step application in the time-domain response) is larger than that achievable at high frequency (corresponding to short times after the VGS step in the domain-time response). Relying on the same basic reasoning, it is easy to conclude that upward gm dispersion curves are instead correlated with a DX-center-like gate-lag behaviour. Dually to the gate-lag concept, drain lag is defined as the “slow” transient which can be detected when measuring the ID waveform in response to the application of a step change in VDS at constant VGS [10,11]. Fig. 1(right) reports a sketch of a typical drainlag experimental setup, while Fig. 7 shows drain-lag measurements obtained from an AlGaN-GaN HEMT (same device of Figs. 3 and 5). As can be noted, the ID waveform in response to a positive VDS step is composed by a prompt response exceeding the final DC value followed a slow decay (similarly to what happens for DX-center-like gate lag). In spite drain-lag effects are conventionally attributed to traps located in the buffer/substrate layers underlying the device channel [6], it has been shown that they can be induced by surface traps as well [5,12] (see Section 3).
Fig. 5. DC and pulsed output characteristics obtained from an AlGaNGaN HEMT by pulsing VGS from -5 V (off-state) to 0 V for different pulse widths. After [5].
T=70°C
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Fig. 6. gm vs frequency curves measured at different temperatures from an AlGaAs-GaAs HFET. The device is biased at VGS= 0 V and VDS=2 V. A 100-mV peak-to-peak sinusoidal signal is superimposed to the DC gate bias. The inset shows the Arrhenius plot of the critical frequencies (fT) corresponding to inflection points. After [4].
Another dispersion effect that emerges in response to VGS modulation is the so-called transconductance
Fig. 7. ID vs time waveforms measured from an AlGaN-GaN HEMT in response to a VDS pulse. After [5].
The drain-lag effect controls the FET pulsed characteristics when the latter are obtained by pulsing VDS (at constant VGS). Fig. 8 shows such pulsed characteristics measured from the same device of Fig. 7. Since the ID values measured shortly after the VDSstep application are higher than the corresponding DC
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values (see Fig. 7), then the pulsed I-V curves lie above the corresponding DC characteristics. The drain lag is also at the origin of the frequency dispersion of the output conductance (go). Upward go dispersion curves are in particular correlated with the drain-lag behaviour shown in Fig. 7 and the corresponding VDS-pulsing-mode characteristics of Fig. 8.
Fig. 8. DC and pulsed output characteristics at VGS=0 V obtained from an AlGaN-GaN HEMT by pulsing VDS from 0 V to the x-axis value at different pulse widths. After [5].
Pulsed characteristics can also be measured by pulsing VGS again with the setup shown in Fig. 1(left) but using a relatively large load resistance , resulting in an oblique load line like that typically adopted for RF power operation. In this case, the VDS changes induced by the ID voltage drop on the load resistance can not be neglected, i.e. both VGS and VDS undergo significant excursions during the pulse cycle. Both VGS and VDS changes can therefore contribute to the delayed ID increase, i.e. the “current collapse” can be due to the combined effect of gate- and drain-lag effects. With respect to the main application of GaAs- and GaN-base FETs, i.e. the power amplification at microwave and millimiter-wave frequencies, the most detrimental aspect of dispersion effects like those shown in Figs. 2-5 is the associated compression of the maximum allowable ID and VDS RF swings (this effect being more properly referred to as RF current collapse). As a result, the RF output power can be significantly smaller than that ideally achievable by a FET having no dispersion (and that can be calculated from the device DC characteristics). Since gate lag is induced by surface traps and drain lag can be caused by either surface or substrate/buffer traps and since both effects contribute to the current collapse during RF operation, it descends that RF current collapse can be due to either surface or substrate/buffer traps or to a combination of the two trap types.
3. Physical mechanisms As far as the physical origin of DC-to-RF dispersion effects is concerned, a general consensus exists about these being induced by deep-level traps. The latter may be located virtually in any device layer, at any interlayer interface, as well as at the exposed or (more commonly) passivated device surface. Thanks to the long-established epitaxial growth techniques of GaAs technologies and to vertical structures which effectively isolates the device active layers from the starting material substrate, dispersion effects in GaAs-based FETs are generally induced (if at all present) by surface traps. Owing to the lower maturity of GaN technologies, dispersion effects in GaN FETs, besides being generally more pronounced than those characterizing GaAs-based devices, can in principle be originated from all of the diversely located traps. Current-collapse phenomena and related RF power compression have however been put into relation with only two of the possible trap locations: (1) bulk traps located in the buffer or substrate layers directly underlying the FET channel and (2) surface traps at the exposed or passivated surface. These two are therefore the sources of DC-to-RF dispersion effects that must principally be taken into consideration, with relevance to both GaAs- and GaN-based FETs. 3.1. Substrate/buffer traps The way by which substrate/buffer traps impact the FET performance is well assessed: it involves the capture and emission of channel electrons in response to VDS changes. In particular, electrons injected in the substrate or buffer layers underlying the channel are captured by traps following the application of a positive VDS change, whereas they are emitted in response to a VDS decrease. As a result, ID decreases(increases) during the slow transients following a positive(negative) step change in VDS and drain-lag waveforms of the type shown in Fig. 7 are observed [13]. When the RF power operation along the load line is considered, it is therefore during the half cycle of the RF sweep in which VGS is increased (and owing to load-line constrain VDS is decreased) that drain lag results in delayed device turn-on and consequent RF ID collapse and output-power compression.
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3.2. Surface traps Surface traps are instead believed to make the gate-source and gate-drain surfaces act as “virtual” or “parasitic” gates, controlling the surface potential through changes in the trapped charge density and therefore modulating the conductance of the underlying channel access regions. As the gate and/or drain bias is changed abruptly, these virtual gates respond with the times characteristic of carrier capture/emission phenomena, thus leading to delayed ID switching [1420]. The specific physical mechanism behind surfacetrap-charge modulation is however still controversial and might be device- and/or technology-dependent. 3.2.1. Electron-trap model The explanation which is more conventionally accepted is that surface traps capture (emit) electrons which are provided (collected) by the gate metal or that transfer from gate to drain and source contacts and vice versa via surface conduction mechanisms [14-20]. In the latter case, surface charging/discharging can be modelled as a distributed R-C network connecting the gate to the drain and source contacts, where the resistive elements take into account surface conduction and capacitative ones describe the capacitance between surface and channel or charge storage into traps [14,21]. Within such a framework, gate and drain lag (and consequently the associated pulsed behaviour and RF current collapse phenomenon) are explained as follows. Any voltage change increasing the gate-source and/or gate-drain reverse bias (like a VGS decrease and/or a VDS increase) results in an enhancement of the surface electron leakage current, in an increase in the trapped electrons and therefore in ID slow decaying transients governed by electron capture. Conversely, any voltage change reducing the gate-source and/or gate-drain reverse bias (such as a VGS increase and/or a VDS decrease) leads to a reduced electron leakage current, to a decrease in the trapped electrons and thus it induces ID slow increasing transients governed by electron emission. 3.2.3. Hole-trap model Alternatively, it has been proposed that surface traps interact with holes attracted at the device surface
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by negatively-ionized levels and associated upward band bending, thereby forming a weakly-inverted surface layer. This hole-trap-based model was originally proposed on the basis of two-dimensional numerical device simulations of GaAs MESFETs [22,23] and subsequently tested against experimental data from AlGaAs-GaAs HFETs [4,12,24-26]. Intriguing experimental indications in favour of the hole-trap model in the latter devices are in particular: (i) the observed opposite dependence of gate-lag effects on temperature depending on whether the device is operated below or above the onset of channel impact ionization, pointing out that at least at high VDS surface traps interact dominantly with surface accumulated holes [4]; (ii) the light sensitivity of dispersion effects and its non-straightforward dependence on temperature, that, only within the framework of the hole-trap model, have a rather natural explanation descending from the temperature dependence of ionized trap concentration and surface hole density [25,26]. Within the framework of the hole-trap model, gateand drain-lag effects are explained as follows. Owing to the presence of deep-level traps with energy relatively close to the valance-band edge (and therefore behaving as hole traps), the device surface can be regarded as an effective p-type region electrically connected with the gate. The role of the doping of this p region is played by the trap density, while the free carrier charge is represented by the hole sheet forming at the surface. Now, any voltage change increasing the gate-source and/or gate-drain reverse bias (like a VGS decrease and/or a VDS increase) tends to deplete both sides of this p-n junction. In particular, it enhances the ionized trap density by detrapping holes from surface traps (the p side of the junction). This induces ID slow decaying transients governed by hole emission. Conversely, any voltage change reducing the gatesource and/or gate-drain reverse bias (such as a VGS increase and/or a VDS decrease) leads to weakened depletion, i.e. it reduces the ionized trap density, by inducing hole capture by surface traps. This leads to ID slow increasing transients governed by hole capture. It is evident that the hole-trap model is completely equivalent, from an electrical point of view, to the electron-trap-based one, the effect on channel conductivity and therefore on ID produced by electron capture or emission being the same as that induced by hole emission and capture, respectively. Regardless of the actual underlying mechanism, it is also clear from the above considerations that even
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surface traps can induce RF ID collapse and consequent output-power compression, as, during the positive halfcycle of the RF sweep, they delay the device turn-on as a combined effect of the simultaneous VGS increase and VDS decrease. 4. Reliability aspects It is widely known that hot electrons are one of the most important issues for the reliability of field-effect transistors. In the past two decades, following the example of studies in Si devices, hot-electron reliability has become one of the most important concerns for GaAs based HEMTs. What is commonly observed after hot-carrier degradation is an increase in the series resistances, a decrease in gm (sometimes accompanied by a threshold-voltage shift), the so-called breakdown walkout, the appearance of DC-to-RF dispersion effects or their worsening if they are already present in virgin devices. All these phenomena have been linked to electron injection and/or to trap generation in the region between gate and drain contacts in the barrier layer, in the buffer or substrate, and/or at the semiconductor/passivation interface and even under the gate region [27-32]. As a result of this, DC-to-RF dispersions effects can be adopted as monitors of hotelectron degradation and studied to infer information about physical mechanisms of degradation. In a work on hot-electron degradation of AlGaAsGaAs HFETs [33], it has been shown that additional information about the degradation mechanism can be inferred by correlating the typical hot-carrier degradation modes reported above with the changes induced by hot-electron stress on the impact-ionizationrelated, bell-shaped gate leakage current. The latter is expected to decrease at increasing hot-electron stress if the dominant degradation mechanism is the surface damage (either creation of surface traps or electron injection into surface traps or into passivation), the associated negative trapped charge increase attenuating the gate-drain peak electric field and reducing channel impact ionization (the same effect is at the origin of the breakdown walk-out, i.e. the increase in the off-state gate-drain breakdown voltage with increasing hotelectron stress). In case the gate-current bell is instead amplified by hot-electron stress (and the typical degradation modes related to surface damage, such as resistance series increase, gm peak degradation, as well as gate-lag enhancement are still observed), one must conclude that trap creation and/or electron injection must take place both at the surface and in the buffer
layer underlying the device channel. Numerical device simulations have shown that the simultaneous channel depletion from the surface and from the bottom squeezes the electron flow at the gate edge, increasing the local channel resistance and the electric field, hence the higher energy and impact ionization rate [33]. More recently, the attention on hot-electron issues passed to AlGaN/GaN HEMTs. Even if many analogies can be found with GaAs HEMTs, there are some aspects that make this issue in GaN HEMTs more problematic. First, in many cases, GaN HEMTs present significant dispersion effects even in “virgin” condition, i.e. before any hot-electron stress. Hotelectron stress induces or enhances these dispersion phenomena especially in unpassivated devices, while passivation of the device surface with SiN has a healthy effect on hot-electron degradation, diminishing the stress effect [34-37]. The observed degradation is sometimes not permanent and the original condition can be restored via UV lighting or with an unbiased room temperature storage. Second, in GaN HEMTs, the gate leakage current can not be used as a hotelectron indicator. In fact, in these devices, many parasitic contributions add to the gate leakage current, making hole generated by impact-ionization only a small portion of the total gate current.
5. Technological counteractions As already mentioned, a fundamental step towards to minimization of DC-to-RF dispersion effects has been done for GaAs- and, more recently, also for GaNbased technologies, thanks to the optimization of epitaxial growth techniques. As far as surface-induced dispersion effects are concerned, a technique that has proven to be very effective in minimizing them in both GaAs- and GaNbased FET technologies is SiN surface passivation [3437]. However, a trade-off generally exists between surface-related dispersion effects and breakdown voltage [15,38]. When the channel is off, surface traps are in fact negatively charged, which effectively reduces the electric field peak at the drain edge of the gate, resulting in a high gate-drain breakdown voltage. Since avoiding RF power compression requires surface-trap density to be minimized, a trade-off exists also between RF output power and breakdown voltage, ultimately hampering high-voltage operation, that would otherwise be highly desirable for the advantages it brings in terms of reduced gate periphery and
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therefore higher device impedances and extended bandwidths, as well as improved PAE. In GaAs-based devices, double-recess gate structures, with gate footprint defined by the inferior recess etch (and therefore characterized by as narrow as possible ungated surfaces) and doped cap layers screening the channel from the surface charge, has profitably been adopted to relax this trade-off, allowing gate-drain electric-field attenuation and dispersioneffect reduction to be achieved in the same device [15]. As far as GaN HEMTs are concerned, different solutions have been devised to achieve the goal of 2DEG screening from surface potential fluctuations induced by traps, including the introduction in the epitaxial structure of a thin GaN cap layer with [39] and without [40] overlying SiN passivation, as well as of a thick GaN cap with SiO2 recess sidewall coverage for gate leakage current minimization [41]. A major step towards dispersion-free GaN-based HEMTs has however been the recent introduction of the field-plate (also called field-modulating plate) into the FET structure. The field plate is essentially a MIS electrode that is located onto the surface passivation layer between the gate and the drain and is connected with the gate. The beneficial effect of the field plate on the FET power performance is twofold: 1) it reduces the electric field strength at the drain edge of the gate, thus increasing the gate-drain breakdown voltage; 2) it suppresses or strongly attenuates DC-to-RF dispersion effects thanks to more efficient surface-trap modulation and/or reduced electron injection into surface traps. Firstly applied to an AlGaAs-GaAs HFET [42], it is in AlGaN-GaN HEMTs that the field plate has yielded striking power performance improvements [43-47], allowing, in force of benefits 1) and 2) above, impressive RF output-power densities to be attained along with excellent PAE and power gain at high operating voltages.
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reliability, in that they are generally enhanced by hotelectron stress and represent therefore one of the most evident degradation modes of compoundsemiconductor microwave power FETs. Technological solutions that have been adopted also or exclusively to reduce dispersion effects to manageable levels include: surface dielectric passivation, double recess gate structures, surfacecharge control layers, field-plated gate structures. References [1] M. Rocchi, Physica B, 129, pp. 119-138, 1985. [2] J. M. Dumas, F. Garat, D. Lecrosnier, Electron. Lett., vol. 23, pp. 139-141, 1987. [3] R. Yeats et al., IEDM Tech. Dig., pp. 842-845, 1988. [4] G. Verzellesi et al., IEEE Trans. Electr. Dev., vol. 50(8), pp. 1733-1740, 2003. [5] G.Meneghesso et al., IEEE Trans. Electr. Dev., vol. 51(10), pp. 1554-1561, 2004. [6] S.C. Binari, P.B. Klein, T.E. Kazior, Proc. of the IEEE, vol. 90(6), pp. 1048-1058, 2002. [7] O. Wada, S. Yanagisawa, H. Takanashi, Jpn. J. Appl. Phys., vol. 12, no. 1, pp. 157-158, 1975. [8] P.H. Ladbrooke, S.R. Blight, IEEE Trans. Electr. Dev., vol. 35(3), pp. 257-267, 1988. [9] W. Kruppa, J.B. Boos, IEEE Trans. Electr. Dev., vol. 44(5), pp. 687-692, 1997. [10]W. Mickanin et al., Proc of GaAs IC Symp., pp. 211214, 1989. [11]N. Saysset et al., Proc. of ESREF’95, pp. 389-394, 1995. [12]A. Mazzanti et al., IEEE Electr. Dev. Lett., vol. 23(7), pp. 383-385, 2002. [13]S. C. Binary et al., IEEE Trans. Electron. Dev., vol. 48(3), pp. 465-471, 2001. [14]S.R. Blight, R.H. Wallis, H. Thomas, IEEE Trans. Electr. Dev., vol. 33(10), pp. 1447-1453, 1986. [15] J.C. Huang et al., IEEE Trans. Microwave Theory Tech., vol. 41(5), pp. 752-759, 1993. [16]V.R. Balakrishnan, V. Kumar, S. Ghosh, IEEE Trans. Electr. Dev., vol. 44(7), pp. 1060-1065, 1997. [17] K.J. Choi, J.-L. Lee, IEEE Trans. Electr. Dev., vol. 48(2), pp. 190-195, 2001. [18]R. Vetury et al., IEEE Trans. Electr. Dev., vol. 48(3), pp. 560-566, 2001. [19]E. Kohn et al., IEEE Trans. on Microwave Theory and Tech., vol. 51(2), pp. 634-642, 2003. [20]B.M. Green et al., IEEE Trans. on Microwave Theory and Tech., vol. 51(2), pp. 618-623, 2003. [21]J.P. Harrang et al., J. Appl. Phys., vol. 61, pp. 19311936, 1987. [22]S.-H. Lo, C.-P. Lee, IEEE Trans. Electr. Dev., vol. 41(9), pp. 1504-1512, 1994. [23]K. Horio, T. Yamada, IEEE Trans. Electr. Dev., vol. 46(4), pp. 648-655, 1999. [24]A. Cavallini et al., J. Appl. Phys., vol. 94, no. 8, pp.
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