Deep trap states relaxation in CaCu3Ti4O12

Journal of Alloys and Compounds 814 (2020) 152185

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Deep trap states relaxation in CaCu3Ti4O12 X.J. Luo a, *, S. Yang a, X.R. Su a, Y.Y. Zhu a, Y. Wang a, S.L. Tang b, C.P. Yang c, Y.S. Liu a, **, €rner d K. Ba a

Shanghai Key Laboratory of Materials Protection and Advanced Materials in Electric Power, Shanghai, 200090, PR China Nanjing National Laboratory of Microstructures, Jiangsu Provincial Laboratory for Nanotechnology and Department of Physics, Nanjing University, Nanjing, 210093, People's Republic of China c Faculty of Physics and Electronic Technology, Hubei University, Wuhan, 430062, PR China d €ttingen, F. Hund Platz 1, 37077, Germany University of Go b

a r t i c l e i n f o

a b s t r a c t

Article history: Received 29 April 2019 Received in revised form 4 September 2019 Accepted 5 September 2019 Available online 6 September 2019

The abnormal dielectric behaviors of the perovskite oxide CaCu3Ti4O12 (CCTO) ceramics were discussed. The hysteretic dc current e voltage (IeV) curves that change hysteresis degree with voltage sweeping rate suggest that there is a slow trap charge transfer process between deep trap sites, which at the same time involve a defect dipole movement, leading to hysteretic capacitance vs. dc voltage (CeV) curve that also change hysteresis degree with voltage sweeping rate. Then, the polarization of the defect dipoles in the deep trap sites is further proved by the frequency dependent CeV relation as well as capacitancetime (C-t) relation. At last, the dynamic processes for the trap charge transfer and the corresponding defect dipoles polarization in a specific boundary was provided. The model suggests that the permittivity (or capacitance) is dependent on the number of trap charges participating the transfer process, which was confined by the energy levels of trap sites. © 2019 Elsevier B.V. All rights reserved.

Keywords: Hysteresis CeV Deep traps Defect dipole

1. Introduction The perovskite-related material CaCu3Ti4O12 (CCTO) is a typical colossal dielectric constant (up to105) material with good temperature stability in a range of 100e300 K and good frequency stability in a range of 102e106 Hz [1]. Such properties make it potential for the miniaturization of electronic capacitor components. Besides the good dielectric properties, CCTO has a remarkably nonlinear coefficient of more than 900, which can be used as the varistor for the surge protector [2]. The excellent characteristics has aroused wide interest for researchers in recent years [3e10]. People always think, why CCTO has so large permittivity and nonlinear coefficient? Why the permittivity could keep stable within a wide temperature or frequency range? Researchers try to find kinds of evidences to disclose the mechanisms, but they always could not reach a unanimous conclusion. There are two basic experimental facts that: first, CCTO is not a ferroelectric but with a stable centrosymmetric crystal structure persisting down to 35 K [1]. Second, the

* Corresponding author. ** Corresponding author. E-mail addresses: [email protected] (X.J. Luo), [email protected] (Y.S. Liu). https://doi.org/10.1016/j.jallcom.2019.152185 0925-8388/© 2019 Elsevier B.V. All rights reserved.

impedance spectra and the Kelvin probe force microscopy measurements of currentevoltage character show that the grains are ntype semiconducting, and the grain boundaries are insulating [2]. Thus, the extrinsic relaxation mechanisms such as the barrier layer capacitor (BLC) which based on the spatial inhomogeneity distribution are widely accepted as the dielectric origin [3,11e18]. However, the BLC model could not explain the abnormal dielectric behaviors, for example, the sharply decrease of permittivity below 100 K, the middle temperature permittivity plateau, the capacitance peaks at high temperature [19e21] or in CeV curves [22,23]. Then, what should be our next concerns to discover the abnormal dielectric behaviors? We know that though the colossal permittivity in CCTO had been found for near 20 years, the high dielectric loss factor (>0.1) always limit its application. Many attempts have been made to reduce the dielectric loss, but at the same time the dielectric constant decreased [24e29]. The reason may be that the polarization process of CCTO is always accompanied by a strong leaky conduction [30], which may be related to the oxygen vacancy related defects, as the dielectric behavior in CCTO is very sensitive to sintering atmospheres in the preparation process. Therefore, we should consider the polarization and conduction behaviors of defects in CCTO. The defects are very common in the dielectric layer of the device

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that can highly influence the transport behaviors of the related devices, as defects can manifest as deep trap states that participate in the charge trapping and limit the electron mobility efficiency. According to kinds of characterization methods, there are many papers reports that the CCTO ceramic is a defective material with vacancies or acceptor and donor ions impurities. However, very few people analyze the roles of these defects to the dielectric or electric transport properties. In this work, we try to analyze the dielectric or electric behaviors from the angle of defects, especially the trap defects. On one hand, the defects in the boundaries may introduce a Schottky barrier, contributing to barrier layer capacitance. On the other hand, the defects may influence the conduction behavior or the nonlinear characteristic. Especially, if the conduction of the defects may involve the defect dipole moment [31e35], the defects can contribute to the polarization, too. In this way, we can simultaneously explain the large permittivity and high leaky conduction in CCTO. 2. Experiments CCTO ceramics were synthesized by traditional solid-state reaction method using analytically pure raw materials of CaCO3 (99.99%), CuO (99%), and TiO2 (99.5%). The materials were weighed according to the stoichiometric ratios and mixed thoroughly. The mixed power was first presintered at 900
C for 10 h and then pressed into disks and sintered at 1000
C for 12 h. At last, the disks were reground again and then pressed into disks with a diameter of 1 cm for the last sintering at 1100
C for 24 h. Silver paste were coated on both sides of the disks and sintered at 580
C for 10 min as electrodes. The dielectric response and the capacitance e dc voltage (CeV) character were measured using a WK6500 (Taiwan, China) impedance analyzer together with a Janis closed-cyclerefrigerator. The cycling current e dc voltage character (IeV) was measured by an electrometer Keithley 2400 with a computercontrolled program. The X-Ray diffraction patterns and scanning electron microscope images of the three samples were shown in our previous work [36]. 3. Results 3.1. The hysteresis behaviors in CCTO In the experiments we found that both the electric transport and dielectric behaviors will show hysteresis at some conditions. In the dc electric transport measurement, if we sweep the voltage in the way of 0 / þVmax / 0 / -Vmax / 0 of dc bias, the currentevoltage (IeV) curve show a strong hysteresis when the voltage sweeping rate is 4.2 V/s. However, if we slow down the voltage sweeping rate to 0.42 V/s, the hysteresis almost disappears, as shown in Fig. 1, which is taken at a low temperature 150 K. At 150 K, we need a large maximum voltage Vmax ¼ 200 V and a high voltage sweeping rate to get the hysteresis. However, at a higher temperature such as 420 K, we only need a lower Vmax ¼ 20 V to get the hysteresis. In addition, if we sweep the voltage continuously for several cycles, the non-linear IeV curve can gradually become near linear under numbers of voltage cycles [37], suggesting a slow cutting down of boundary barrier according to the charge carriers release or capture from the trap sites. As to the reason for the hysteresis which is easier to occur at high temperatures or higher voltage sweeping rate, we think the high temperature is favorable to the thermal activation of carriers from deep trap sites. The high voltage sweeping rate actually suggests a change of dc voltage at a low frequency. The hysteresis can also happen in the capacitance e dc voltage (CeV) relation, in which the line shape also depends on the test

temperature, electric field and voltage sweeping rate. When we sweep the dc bias circularly from -V / 0 / þVmax/ 0/ -Vmax/ 0 at a voltage sweeping rate of 0.2 V/s, as shown in Fig. 2(a), the CeV curve at 420 K and 1 kHz show an obvious hysteresis and the capacitance rises with increasing dc bias. However, if we decrease the voltage sweeping rate to 0.05 V/s, as shown in Fig. 2(b), the hysteresis disappears and the capacitance still rises with increasing dc bias. If we decrease the temperature to 250 K, as shown in Fig. 2(c), at 1 kHz, whenever the voltage sweeping rate is 0.05 V/s or 0.25 V/s, we could not observe the hysteresis. But unlike the rise of capacitance at 420 K, we only see the capacitance decreases with increasing dc bias at 250 K. However, our additional experiments found that, also with the voltage sweeping rate 0.05 V/s, if we decrease the measuring frequency to 20 Hz, we can also see a capacitance rise at 250 K. The presence of hysteresis in CeV curve is always considered as an indicator of interface defect traps. Researchers have used the hysteresis in CeV to estimate the defect density in dielectrics, where the magnitude of hysteresis is proportional to the defect density [38e44]. The hysteresis appear in Figs. 1 and 2 seems have common characteristics: all of them appear easily at high temperature, high electric field and high voltage sweeping rate, suggesting a thermal or electric field activated carriers from deep trap sites. The hysteresis in Fig. 1 is contributed by the charge transfer between deep trap sites, while the hysteresis in Fig. 2 is contributed by the polarization of trap charges from deep trap sites. That is, the trap charges transfer between deep trap sites simultaneously contribute to the conduction and polarization. As to the way of the trap charge polarization, we think the carriers trapping may introduce a misalignment of the positive and negative charge centers in trap sites, forming defect dipoles and leading to the polarization of the crystal matrix. In our previous work, we called this process the trap charge repositioning process [30]. The detailed image of the formation of defect dipole could be seen in Fig. 8 in discussion section. The hysteresis can also appear in the polarization e electric field (P-E) curves, which had already found by several researchers. In our experiment, we reproduced the P-E loops again in Fig. 3. There are obvious ferroelectric-like P-E loops but could not achieve saturation with increasing electric field. The maximum polarization intensity increases when we increase the maximum voltage. However, unlike others, we mainly see a large positive remnant polarization intensity. The negative remnant polarization intensity

Fig. 1. IeV curves measured at 150 K at different voltage sweeping rate.

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Fig. 2. The CeV curves at (a) 420 K with voltage sweeping rate of 0.2 V/s, (b) 420 K voltage sweeping rate of 0.05 V/s and (c) 250 K voltage sweeping rate of 0.05 V/s and 0.25 V/s.

is very small in the negative voltage load. Therefore, it is different from the switching of the spontaneous polarization of dipoles in ferroelectrics, but it is the polarization behavior of defect dipoles. The hysteresis is similar to the hysteresis appears in CeV curves that the polarization is mainly contributed by the deep trap dipoles which are pinned in the external filed. Due to the slow relaxation time of the deep trap defects, the defect dipoles could not timely orientate under the opposite electric filed, we can only see a positive polarization intensity dominate in the negative electric field.

3.2. The frequency dependent CeV relation Another method to verify the trap charges related conduction and polarization is the investigation of frequency dependent CeV relation. The interface traps can modify the CeV curves of the studied structures, which represent as the stretch-out or a voltage shift of the curves with the measuring frequency [39,45e48]. The reason may be that, during the CeV sweep, the interface traps with corresponding time constant will respond to the ac signal at a certain frequency, while these traps will contribute to the measured capacitance, leading to a frequency dispersion in CeV curves due to the different time constants of traps [48]. In order to analyze the relation between polarization and conduction, in Fig. 4 we plotted CeV curves and dielectric loss tand-V curves together, as the ac conductivity is proportional to the dielectric loss factor tand. In Fig. 4(a), we see that both the capacitance and dielectric loss increase with dc bias at 100 Hz, indicating that the polarization is built in the carriers’ electric transport process. When

Fig. 3. The P-E loops measured under different maximum electric field.

we increase the frequency to 1 kHz ((Fig. 4(b)), the capacitance rises (the first rise) transitorily as the applied dc bias increase from negative bias -3 V to about 1 V, and then quickly decreases with the further increase of dc bias. After a minimum capacitance, the capacitance begins to rise again (the second rise) at a higher applied bias. The CeV also shown a hysteresis under the circularly sweeping of dc bias from -V / 0 / þVmax/ 0/ -Vmax/ 0. However, at 1 kHz, the loss factor still increases monotonically with dc bias, without any decrease. When we increase the frequency to 10 kHz, as shown in Fig. 4 (c), the second rise of capacitance

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disappears, only the first rise exists, which followed by a capacitance decrease with the further increase of dc bias. At this time, the loss factor shows a small step from 1 V/ 4 V and the line shape of the tand-V is like the line shape of CeV curve at 1 kHz shown in Fig. 4 (b). It seems that, the change of conductivity falls behind the change of capacitance at middle frequency. If we increase the frequency to 1 MHz, the line shapes of the CeV and tand-V are the same, as shown in Fig. 4 (d), after the first rise, both of them decrease with dc voltages. According to the comparative analysis of the line shape evolution with frequencies for both CeV and tand-V curves, we see that both the polarization and conduction is confined by the relaxation time of trap charges. Hu et al. also observed a capacitance rise with dc bias in their perovskite solar cell device. In addition, they found the capacitance peak increases and moves to a higher dc bias with increasing light illumination time [41]. They think the accumulation of photogenerated charge carriers at electrode interfaces lead to the increased capacitance with the applied bias [41]. After the capacitance peak, the charge injection and recombination at higher applied bias can occur, leading to a capacitance decrease [41]. In our case, we think the external field will activate the trap charges, which accumulate at the interface and lead to the capacitance rise. The first rise of capacitance within 0e1 V seems independent on frequencies, as it appears both at 100 Hz and 1 MHz. In addition, it always accompanied by a rise of dielectric loss factor in the same dc bias range. We think it originate from the polarization of defect dipole from shallow trap sites, which response fast under the electric filed. The second rise of capacitance can only be observed at a higher dc voltage and a low frequency, and is also accompanied by

a strong conductivity rise. We think it is due to the polarization of defect dipoles with longer relaxation time from deep trap sites. Yang's group found that the hysteresis occurs easily for the sample sintered under vacuum atmosphere [49], suggesting that the defect dipoles may come from the oxygen vacancy related deep trap sites. We should mention that both the capacitance rise should not come from the back to back Schottky barrier layer capacitance, which firstly shows a decrease once the external field is applied [3]. Note that at low frequencies, for example, at 100 Hz in Fig. 4 (a), both capacitance and loss factor increase monotonously with increasing dc bias. Here, there may be a superposition of the first and the second rises of capacitance. This suggests that only at low frequencies, the deep trap charges with long relaxation time activated at higher dc bias can timely supplement their contribution to capacitance and conductance. Therefore, we think only at higher frequencies, we can observe the barrier layer capacitance which decrease with increasing dc bias. As there is a depletion of shallow trap sites and a cease working of deep trap charges. 3.3. The abnormal relaxation processes after electrical conditioning The two relaxation processes (the two rises of capacitance) observed in CeV curves could also reappear in the capacitance e time (C-t) curves after the electrical conditioning. The electric conditioning means (EC) that, let the sample undergo cycling dc voltage sweeping in the way of 0 / þVmax / 0 / -Vmax and at the same time monitor the change of current [37,50]. Under EC, the initial non-linear current e voltage (IeV) curves of CCTO will gradually become near linear, suggesting a decrease or even

Fig. 4. The CeV curves for the sample sintered at vacuum at (a) 100 Hz, (b) 1 kHz, (c) 10 kHz and (d) 1 MHz.

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disappearance of the boundary barrier. Then, we remove the dc voltage immediately (operation time 3 s), and measure the response of capacitance with recovery time at different experimental parameters. Fig. 5 shows the response of capacitance (Fig. 5(a)) and conductivity (Fig. 5(b)) with recovery time at different temperatures. We see that at 420 K, the capacitance firstly shows a peak (peak 1) and then recover to a capacitance plateau (plateau 1), while the conductivity gradually recovers to its normal state. At lower temperature such as 250 K, peak 1 and plateau 1 also appear. However, after plateau 1, the capacitance gradually decreases to another lower plateau 2. if we increase the ac signal frequencies, as shown in Fig. 6(a) and (b), peak 1 gradually disappears both at 250 K and 420 K. However, at 250 K, at higher frequencies such as 80 kHz and 100 kHz, the capacitance peak 2 comes out, which followed by the plateau 2. In our previous work, we had successfully explained the capacitance peak by the model of trap charge repositioning between different trap sites [37]. We think the capacitance peak may represent the largest occupation imbalance of defect dipoles at the interface after the trap charge repositioning under the electric filed, which is metastable that can only survive for a while. Two capacitance peaks suggest that the dynamic relaxation processes occur at two different locations, or between trap sites with two different energy levels. While two capacitance plateaus may represent two polarization balance of related trap charges after the dynamic relaxation processes. In addition, from Figs. 5 and 6 we can obtain more information: 1) peak 1 disappears at high frequencies, suggesting that it comes from the polarization of deep trap charges; peak 2 can be observed clearly at low temperatures and can survive at high frequencies, suggesting that it comes from the polarization of shallow trap charges. 2) The height of plateau 1 decreases with increasing frequencies, see Fig. 6 (a), but the height of plateau 2 show litter changes with frequencies, see Fig. 6(b). Thus, we deduce that plateau 1 represent the polarization balance state of the deep trap charges, which can keep a long time at high temperatures such as 420 K, while plateau 2 may represent the polarization balance state of the shallow trap charges that can appear at lower temperatures such as 250 K. 3) As the EC process may activate almost all

5

Fig. 6. The time dependent capacitance at different frequencies after electric conditioning, with (a) 420 K and (b) 250 K.

the charges from deep trap sites even at low temperatures, the height of plateaus 1 are almost at the same capacitance scale and independent on the temperature change. However, the height of plateaus 2 are different when we change temperatures, suggests that there are different numbers of shallow trap charges participating in the polarization at different temperatures. Actually, according to the characteristics shown in the capacitance vs. temperature curves, we can further understand the two polarization balance states represented as platforms 1 and 2. As shown in Fig. 7, there is a broad capacitance plateau within a lower temperature range of 100 Ke200 K and a short capacitance plateau within a lower temperature range of 250 Ke280 K, which are corresponding to the polarization balance state of the shallow trap charges and deep trap charges, respectively. Before the capacitance plateaus, there are two sharp rises of capacitance in a lower temperatures range of 53 Ke100 K and a higher temperatures range of 200 Ke230 K, respectively. The capacitance rise in the lower temperature range may be due to the dynamic relaxation of shallow trap charges, while the capacitance rise at the higher temperature may be due to the dynamic relaxation of deep trap charges. Correspondingly, the two relaxation processes show two loss factor peaks at 53 K and 230 K, respectively.

4. Discussion 4.1. The different trap levels in CCTO Fig. 5. The time dependent dielectric response of (a) capacitance and (b) ac conductivity after electric conditioning at different temperatures.

By visible light absorption analysis, Rosseinsky el al found two

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X.J. Luo et al. / Journal of Alloys and Compounds 814 (2020) 152185

gaps of 2.21 and 1.39 eV in the visible region in sol-gel synthesized CCTO. The results were analyzed combining with the LSDA þ U electronic structure calculations. They think there is a localized unoccupied narrow Cu 3d band located within the gap [51], creating localized states which can trap electrons and facilitate recombination. This narrow band also facilitate the oxidization and reduction of transition metal ions Ti4þ and Cu2þ. Tsuji et al. observed three peaks from 100 to 350 K in charge-based deep level transition spectroscopy (DLTS), and the corresponding trap energy is 0.15, 0.79, and 0.66eV [52]. In our work, by the Arrhenius fitting of the relaxation peaks in Fig. 7 at different frequencies, we got an activation energy of about 0.07e0.09 eV from the low temperature peaks (at about 60 K) and of 0.6 eV from the higher temperature peaks (about 250 K), respectively. We think 0.07e0.09 eV is corresponding to the activation energy of charges from shallow trap sites, and 0.6 eV is corresponding to the activation energy of charges from the deep trap sites. However, what may these trap sites be? In our previous work we found that both conductivity and permittivity of CCTO is sensitive to the oxygen content. Particularly, the sample sintered under vacuum has the largest permittivity and conductivity. Thus, the trap sites might come from oxygen vacancy related defects. When the ceramics were sintered in the oxygen deficient sintering atmosphere, the acceptor ions Cu1þ and Ti3þ in ceramics may generate [53,54], which was compensated by oxygen vacancies and form metal-oxygen vacancy defect complexes like,  0   ðCuCu 0  V  o Þ or ðTiTi  V o Þ (with a dot representing a positive charge and a single quote representing a negative charge) [33,35]. These defect complexes may capture electrons or as a recombination center. The charge transfer between these defect complexes may create the polaron electronic transport, at the same time, the trapping of carriers may introduce a misalignment of the positive and negative charge centers of the defect complex, forming defect dipoles as shown in Fig. 8(c). On one hand, the charge hopping between defect complexes lead to the conduction; on the other hand, the charge transfer between different trap sites may be accompanied by the movement of the defect dipoles, introducing a large polarization [30,37]. Different defect complexes may form trap sites with different energies for charge carriers. The same defect complex at different locations may also introduce different trap energy levels in the crystal. 4.2. Repositioning dynamics for the defect complexes The trap charge repositioning between defect complexes could

happen when the energy states of the charge carriers changed under external field or the thermal enviroment. In our previous work we had provided the detailed modle for the trap charge repositioning between different defect trap sites [55]. Here we add the detailed dynamic processes for the trap charge repositioning in a specific boundary. The Kelvin probe of the IeV curves for the single grain or grain boudary suggests that the grains are n-type and the boundaries are insulating [2]. As the defect complexes mainly inhabited in the boundaries will absorb the carriers from the n-type grains, introducing two back to back space charge layer (on A and B sides) with two inverse internal fields Ei , froming a Schottky barrier layer in the center of the boundary. Thus, there will be a barrier layer capaciatance provided here. But besides the barrier layer capacitance, we should consider the polarization of defect dipoles. Fig. 8(c) shows the detailed image of the formation of a defect dipole. In Fig. 8 (a) and (b), the peak like lines show the height of barriers, and the ellipsis show the defect dipoles. Compared with the fixed Schottky barrier model, the defect dipoles are not fixed but can move to other locations according to trap carriers repositioning under the action of an external field E0 . As shown in Fig. 8(a), under zero electric field, as the aborption of the carriers from the bulk is equal, the numbers of defect dipoles with opposite orientations on A side and B side respectively are also equal. Therefore, both the boundary perpendicular to the external field (“fs” boundary) and the boundary parallel to the external field (“fp” boundary) show a zero polarization. If we apply an dc bias as shown in Fig. 8(b), the external field will adjust the width of the space charge layers on A side and B side differently. As shown in Fig. 8(b), the potential will increase on the A side of “fs” boundary, and on the both sides of “fp” boundary. Thus, the charges on the A side of the “fs” boundary and the B side of the “fp” boundary will hop to the B side of the “fs” boundary. Then, due to the advantage of the charge carrier's occupation on the B side of the “fs” boundary, there will be a large imbalanced occupation of the defect dipoles in “fs” boundary, which will make a large polarization in the “fs” boundary. The situation is similar to the thermion's relaxation polarization. When the charged particles in a weak bound of the matrix migrate directionally under the external filed, it will cause a remnant of the charged particles in a local region of the crystal matrix. If the remnant charges lead to an asymmetry of the positive and negative charge centers, the electric moments form and the matrix is polarized. The charged particles always come from the defects that can be easily activated by the thermal environment or electric filed. In CCTO, the charge carriers may be activated from the oxygen vacancy related defect complex. The dynamic repositioning process allows us to calculate the reversible temperature and field dependent excess of the defect dipoles under the assumption that there are always enough complexes available, NC [N, with NC the concentration of defect complexes, and N the concentration of hopping carriers. For a three-dimensional space the number is N/3 for each dimension. Considering the charge carriers hopping at “fs” boundary, before the hopping, the number of carriers both at A and B sides are N/6. When the thermal motion energy is larger than the barrier layer height fb , for the nearest hopping the carriers can get over the barrier and hop from A side to B side or vice versa. A and B sides are two equilibrium position under zero external field. Assuming that the hopping frequency is n, the charges that hop from A to B side and from B to A side are equal [56]:

NBA ¼ NAB ¼

Fig. 7. The temperature dependence of capacitance and loss factor of CCTO at 20 Hz.

N fb =kT ne 6

(1)

If we add an external filed with and electric energy Df, as shown in Fig. 8(b). The barrier height from A to B is fb  Df, and from B to

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Fig. 8. The schematic diagram for the trap charge repositioning (TCR) process in the back to back np junctions, with (a) the external field E0 ¼ 0 and (b) the external field E0 s 0 [45].(c) shows the schematic diagram of the formation of a defect dipole.

  Ea N0 exp  kT , with N0 the initial numbers of carriers and Ea the activation energy. We get,

A is fb þ Df, then the charge transition rate from A to B side is

gAB ¼ neðfb DfÞ=kT

(2a)

which is larger than that of from B to A side: ðfb þDfÞ=kT

gBA ¼ ne

ε0 ¼ (2b)

Under electric field, if the number of the hopping carriers is DN, then at A side the carrier number is reduced to N6  DN, and at B sides is increased to N6 þ DN. We can get the dipole moment per unit volume caused by the residual hopping carriers (or the defect dipoles as a result of carrier trapping):

PT ¼ DNqd

(3)

Where q is the charge of the hopping carrier and d is the hopping distance between A and B sides. In the steady state, the charge distribution reach to balance and no longer change, we get [56]:



   N N  DN neðfb DfÞ=kT ¼ þ DN neðfb þDfÞ=kT 6 6

(4)

Then,

  N eDf=kT  eDfb =kT
DN ¼ 6 eDf=kT þ eDfb =kT

(5)

Then the polarization intensity is [56],

  Nqd eDf=kT  eDfb =kT
PT ¼ DNqd ¼ 6 eDf=kT þ eDfb =kT

(6)

If the external field applied on each grain boundary is weak, and the electric energy fulfilsDf≪kT, then e±Df=kT z1±Df=kT. As Df ¼ 1 qdE , the polarization intensity can be write as [56]: 0 2

PT ¼ DNqd ¼

Nqd E 12kT 0

(7)

As PT ¼ ε0 ðε0  1ÞE0 , with ε0 the permittivity of vacuum, ε0 the permittivity obtained from the polarization, we get,

ε0 ¼

2

Nq2 d þ1 12kTε0

(8)

At low temperature, N ¼ 0 and ε' ¼ 1. In the thermal activation of carriers from trap defects, the charge carriers may increase exponentially with temperature. If N ¼

  2 Ea q2 d N0 exp  kT 12kTε0

þ1

(9)

Assuming the hopping distance d is a constant, which may only depend on the location of trap sites in a localized region that almost do not change once created under a high temperature sintering process. Then the permittivity will sharp rise with temperature, which shown as the temperature regions 53 Ke100 K and 200 Ke230 K in Fig. 7. After the thermal activation of the charge carriers, there is a stable charge carrier reserve region. Then, the number N of the carriers ionized from the defects should be near constant or show small change with temperature. Assuming that, N ¼ bT; ð0 < b < 1Þ, we can get:

ε0 ¼

bq2 d2 12kε0

þ1

(10)

Then the permittivity will keep constant with temperature, which shown as the temperature regions 100 Ke200 K and 250 Ke280 K in Fig. 7. We see that the permittivity is dependent on the number of trap charges activated. According to eq. (8) we can explain the capacitance rises and plateaus in Fig. 7. However, when the temperature is constant, the polarization of defect dipoles is more dependent on the frequencies of the ac signal due to the slow relaxation of deep traps, as shown in Figs. 4 and 6. Of cause the external field will change the space barrier layer height for charge transfer, especially at the interface between the surface and electrode where there is a large load voltage. In addition, as the capture is always faster than the slow release process charges from deep trap sites, though the external field change signs, the Schottky barrier height in fs boundary can gradually decrease under EC. The capture of carriers will make the number of defect dipoles at B sides much larger than that at A side, and then the capacitance will slowly rise. Then, if there are more EC cycles followed, the empty trap sites on A side is also gradually occupied, and then the occupation imbalance will gradually decrease. At that time, we could not observe the defect dipole polarization any more, only the barrier layer polarization left. 5. Conclusion In summary, according to the investigation of the hysteresis

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behaviors appear in the conduction and polarization processes, and the frequency dependent CeV relation, as well as the time response of capacitance and conduction after the electric conditioning, we think the conduction and polarization in CCTO ceramics are related to the deep traps at the interface. The trap charge transfer (or repositioning) between trap sites under electric field may cause a hopping conduction, which at the same time involve dipole movements and form defect dipoles, contributing to the polarization. As the charge transfer between deep trap sites is slow, we can observe hysteretic IeV and CeV curves, as well as the frequency dependent CeV and C-t relations. The thermal activation of these trap sites may cause the fast rise of permittivity with temperature, while the charge localization in the trap sites with a certain energy level may cause the permittivity plateaus in the permittivity temperature curves. In conclusion, we think the trap charge repositioning between trap defect complexes is the key factor for the high conduction and high dielectric loss in CCTO, as well as the abnormal dielectric behaviors. Thus, it is always hard to increase the dielectric constant significantly and at the same time decrease the dielectric loss. Acknowledgments This work is supported by the National Natural Science Foundation of China (Grant Nos. 11504227, 51672172, 51502168, 11674215), and the project of the Science & Technology Committee of Shanghai Municipality (No. 19020501000). References [1] M.A. Subramanian, D. Li, N. Duan, B.A. Reisner, A.W. Sleight, High dielectric constant in ACu3Ti4O12 and ACu3Ti3FeO12 phases, J. Solid State Chem. 151 (2) (2000) 323e325. [2] S.Y. Chung, I.D. Kim, S.J. Kang, Strong nonlinear current-voltage behaviour in perovskite-derivative calcium copper titanate, Nat. Mater. 3 (11) (2004) 774e778. [3] T.B. Adams, D.C. Sinclair, A.R. West, Characterization of grain boundary impedances in fine- and coarse-grained CaCu3Ti4O12 ceramics, Phys. Rev. B 73 (9) (2006), 094124. [4] Y. Liu, R.L. Withers, X.Y. Wei, Structurally frustrated relaxor ferroelectric behavior in CaCu3Ti4O12, Phys. Rev. B 72 (13) (2005), 134104. [5] S.V. Kalinin, J. Shin, G.M. Veith, A.P. Baddorf, M.V. Lobanov, H. Runge, M. Greenblatt, Real space imaging of the microscopic origins of the ultrahigh dielectric constant in polycrystalline CaCu3Ti4O12, Appl. Phys. Lett. 86 (10) (2005), 102902. [6] S.Y. Chung, Lattice distortion and polarization switching in calcium copper titanate, Appl. Phys. Lett. 87 (5) (2005), 052901. [7] C.C. Homes, T. Vogt, S.M. Shapiro, S. Wakimoto, M.A. Subramanian, A.P. Ramirez, Charge transfer in the high dielectric constant materials CaCu3Ti4O12 and CdCu3Ti4O12, Phys. Rev. B 67 (9) (2003), 092106. [8] L. He, J.B. Neaton, D. Vanderbilt, M.H. Cohen, Lattice dielectric response of CdCu3Ti4O12 and CaCu3Ti4O12 from first principles, Phys. Rev. B 67 (1) (2003), 012103. [9] L. He, J.B. Neaton, M.H. Cohen, D. Vanderbilt, C.C. Homes, First-principles study of the structure and lattice dielectric response of CaCu3Ti4O12, Phys. Rev. B 65 (21) (2002), 214112. [10] C.C. Homes, T. Vogt, S.M. Shapiro, S. Wakimoto, A.P. Ramirez, Optical response of high-dielectric-constant perovskite-related oxide, Science 293 (5530) (2001) 673e676. [11] G. Cao, L. Feng, C. Wang, Grain-boundary and subgrain-boundary effects on the dielectric properties of CaCu3Ti4O12 ceramics, J. Phys. D Appl. Phys. 40 (9) (2007) 2899e2905. [12] C.C. Wang, L.W. Zhang, Surface-layer effect in CaCu3Ti4O12, Appl. Phys. Lett. 88 (4) (2006), 042906. [13] L. Zhang, Electrode and grain-boundary effects on the conductivity of CaCu3Ti4O12, Appl. Phys. Lett. 87 (2) (2005), 022907. [14] G. Zang, J. Zhang, P. Zheng, J. Wang, C. Wang, Grain boundary effect on the dielectric properties of CaCu3Ti4O12 ceramics, J. Phys. D Appl. Phys. 38 (11) (2005) 1824e1827. [15] J. Liu, C.-g. Duan, W.N. Mei, R.W. Smith, J.R. Hardy, Dielectric properties and Maxwell-Wagner relaxation of compounds ACu3Ti4O12 (A¼Ca,Bi2/3,Y2/3,La2/ 3), J. Appl. Phys. 98 (9) (2005), 093703. [16] P. Lunkenheimer, R. Fichtl, S.G. Ebbinghaus, A. Loidl, Nonintrinsic origin of the colossal dielectric constants in CaCu3Ti4O12, Phys. Rev.B 70 (17) (2004), 172102.

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