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GaAs interface grown by MBE-interruption growth technique
Materials Science and Engineering C 27 (2007) 1069 – 1073 www.elsevier.com/locate/msec
Deep traps at GaAs/GaAs interface grown by MBE-interruption growth technique M. Kaniewska a,⁎, O. Engström b a
Department of Analysis of Semicoductor Nanostructures, Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw, Poland b Department of Microtechnology and Nanoscience, Chalmers University of Technology, SE-412 96 Göteborg, Sweden Received 6 September 2006; accepted 9 September 2006 Available online 19 October 2006
Abstract Electron trapping centers at the GaAs/GaAs interface grown by molecular beam epitaxy (MBE)-interruption growth technique have been studied by capacitance versus voltage (C–V) measurements and deep level transient spectroscopy (DLTS). Two main electron traps have been revealed with activation energies at 0.16 eV and 0.52 eV from the conduction band. Inhomogeneous spatial distributions of the traps, obtained by DLTS profiling, indicate that they are agglomerated at the interrupted interface on a concentration level of (2–3) × 1015 cm− 3 at their maximum. Their behaviour is typical of acceptor-like traps when investigating by C–V profiling as a function of temperature. Based on a comparison made with electron traps in MBE-GaAs as well as with the traps in InAs/GaAs quantum dot/quantum well (QD/QW) structures, we conclude they are the well-known EL10 and EL4 defects, respectively, and their concentrations are growth condition dependent. They may be point defect-impurity complexes. Their presence may cause interpretation and application problems of the low-dimensional InAs/GaAs structures. © 2006 Elsevier B.V. All rights reserved. Keywords: MBE-GaAs/GaAs growth-interrupted interface; Defects; DLTS; C–V profiling
1. Introduction In order to benefit from the advantages obtained by quantum dot systems in photonic and electronic devices, it is important to keep the crystal in the vicinity of the quantum dots (QDs) free from defects and impurities. Accordingly, a recently growing activity has appeared in the literature for studying intrinsic InAs/ GaAs QD phenomena and QD related defects by electrical methods like deep level transient spectroscopy (DLTS) and capacitance versus voltage (C–V) measurements [1–5]. For InAs/ GaAs QDs, a large difference in optimum ramping growth temperatures for the InAs layer (480–510 °C) and the GaAs buffer and cap layers (580–630 °C), respectively, is necessary to grow the sandwiched InAs/GaAs structure. This leads to poorer crystal perfection of the GaAs layers at the InAs/GaAs interface, which together with the strain present in the structures may be responsible for deep-level defect formation. Therefore, in order to ⁎ Corresponding author. Tel.: +48 22 5487793; fax: +48 22 8470631. E-mail address: [email protected] (M. Kaniewska). 0928-4931/$ - see front matter © 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.msec.2006.09.012
suit the growth conditions, the QDs structures are usually fabricated with the growth interruption technique under an excess of As. It is considered as a method, which enables to improve the quality of the InAs/GaAs interfaces, by performing the growth at a reduced temperature. In a recent DLTS study of InAs/GaAs QD structures we discovered the presence of several deep traps, accumulated in the vicinity of the QD plane [4]. This tendency of traps to agglomerate at the InAs/GaAs interface may cause difficulties in differentiating them from intrinsic QD levels. Therefore, to make the interpretation easier, it is important to have information on trap-related levels in reference samples. This paper reports results of an electrical study on deep states in layered GaAs reference structures designed as Schottky diodes, without any InAs insertion, but otherwise prepared under typical of QD growth conditions. 2. Experimental The GaAs buffer and cap layers were grown by solid source MBE at a substrate temperature of 580 °C and were intentionally
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doped with Si to approximately 1 × 1016 cm− 3. The substrates were (001)-oriented GaAs wafers. The epitaxial procedure was performed as similar as possible to the cycle used when preparing QDs [2]. In that process, prior to growth of the cap layer, the substrate temperature is decreased to 510 °C, followed by a deposition of 3–4 monolayers (MLs) InAs. The InAs growth is done under a repeated sequence of 0.1 ML InAs followed by a 2-s growth interruption under an excess of As2 until the InAs layer reaches the target thickness where QDs are shaped by the Stranski-Krastanov effect. In the present reference samples, the same procedure was performed with the exception that the In source of the MBE facility was never opened. This resulted in a GaAs cap layer grown on a GaAs buffer layer produced under the same conditions as when preparing QD samples. AuGeNi ohmic contacts were fabricated by annealing at 400 °C for 1 min. Schottky contacts were fabricated by evaporating gold dots of 1 mm diameter. C–V and DLTS measurements were performed by means of a lock-in type DLS-83E system (Semitrap, Hungary) operated at 1 MHz in temperature and frequency scan modes. 3. Results and discussion C–V measurements were performed at 1 MHz signal frequency and the carrier concentration profile was calculated using the depletion approximation formula: −1 2 d 1 NCV ðW Þ ¼ 2 ; ð1Þ A qe dV C 2 where ε is the dielectric constant, q is the electron charge, and A is the area of the Schottky barrier. NC–V(W) is the apparent free electron concentration at the edge of the space charge layer with thickness W. A typical dependence of capacitance and shallow dopant concentration on the reverse bias voltage for the samples studied at 119 K is shown in Fig. 1. The dip followed by a peak, seen in the profile of Fig. 1, is very similar to that observed by Kimerling [6] in proton bombarded n-type Si and indicates the
Fig. 1. C–V characteristics and shallow doping concentration as a function of the reverse bias voltage of a structure used to study states at the GaAs/GaAs growth-interrupted interface.
Fig. 2. Apparent free-carrier concentration vs. distance into the structure from the surface. Measurement temperatures are indicated for each profile.
presence of an acceptor-like trap with an inhomogenous distribution. The characteristic peak is observed for measurement condition such that, ω(ΔVosc) N en N ω(ΔVc), i.e. the frequency of the oscillating voltage, ω(ΔVosc), employed in the capacitance measurement, is fast compared with the thermal emission rate of carriers from traps, en, while the latter, in turn, is fast compared with the frequency of the variation in bias voltage, ω(ΔVc). The conditions governing the data shown in Fig. 1 fulfill these relations. For this case, not only uncovered charge at the edge of the depletion region but also charge in traps located at a distance of λ from the edge, where the Fermi level crosses the deep level, contribute to the differential capacitance. The calculated carrier profile nearly reflects a triangular shape [6] for the acceptor distribution, and in addition it exhibits the overshoot in carrier concentration when the down slope of the trap distribution is reached while changing the bias voltage. The peak is an indicator that acceptors at high concentration and with a sharp distribution are present. Since en is thermally activated, the anomaly should disappear when measurements are performed at low temperature, where ω(ΔVc) N en. The free-carrier depth profile was studied as a function of temperature and data were obtained for various temperatures with results as shown in Fig. 2. C–V data were used to convert the voltage-axis to spatial scale from the differential diode capacitance and the depth W was calculated using W = εA/C. When measuring at 119 K, the peak is located at 0.92 μm, followed by a shift to about 0.84 μm at 250 K, which is accompanied by a new peak appearing at about 1.02 μm. This indicates the presence of a second, acceptor-like trap. As the temperature is lowered to 25 K, the frequencies fulfill the condition ω(ΔCc) N en. The two peaks disappear and an accurate profile is obtained as a result of the combined compensation effect of the two traps. A typical DLTS spectrum obtained in the temperature scan mode is presented in Fig. 3. Two main traps, labeled A and B, were revealed. Due to a non-homogenous depth distribution, appropriate measurement conditions had to be determined. For this purpose, DLTS in the frequency mode was used and DLTS signal height as a function of the pulse repetition frequency, f,
M. Kaniewska, O. Engström / Materials Science and Engineering C 27 (2007) 1069–1073
Fig. 3. Typical DLTS spectrum obtained with the samples in the temperature scan mode. The steady-state bias, VR, and voltage level of carrier-filling pulse, V1, were equal to VR = 4V and V1 = 0, respectively. The emission rate window, en was 543 s− 1.
was studied at constant temperature for various reverse bias voltages and various pulse amplitudes as well. The 119 K frequency spectra for trap A with the reverse bias voltage as a parameter are shown in Fig. 4. As seen in Fig. 5, the peak frequency decreases with increasing VR up to VR = 4.3 V and turns back to higher values when VR is further increased. At the same time, the relative change in DLTS signal capacitance, ΔC/CR, goes through a maximum as VR is varied (Fig. 5). The
Fig. 4. DLTS signal height as a function of pulse repetition frequency at T = 119 K for various reverse bias voltages, VR. The voltage level of carrier filling pulse was kept constant and equal to 0.
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Fig. 5. Peak frequency and relative peak height vs. reverse bias voltage. Data extracted from Fig. 4 for trap A.
peak at lower biases seems to be influenced by a second shallower energy level recognized in Fig. 4 as a non-symmetry introduced at higher frequencies. The decrease in peak frequency for the lower VR values indicates that trap A has a certain spread in energy levels, while the increase of this quantity at higher VR is expected to occur due to an increased emission rate influenced by electric field effects. Furthermore, for the lowest voltage levels, the DLTS signals might be underestimated due to the so-called transition region effect [7,8]. However, in agreement with the C–V data shown in Figs. 1 and 2, further results obtained by double correlated DLTS (DDLTS) profiling [9], allowing to avoid the transition region effect, show that the trap has a strong inhomogeneous depth distribution. The measurements were done at relatively low biases to avoid the influence of the electric field. Fig. 6 shows the 119 K DLTS spectra for trap A with the voltage level of filling pulse as a parameter. A growing signal is observed when keeping the emission bias voltage, VR, fixed at 5 V and increasing the filling pulse amplitude. Here, the peak frequencies are constant due to the constant VR value, which empties electrons captured by the trap level distribution equally in the DLTS measurement. More detailed data for various pulse
Fig. 6. DLTS signal height as a function of pulse repetition frequency at T = 119 K for various voltage levels of filling pulse, V1. The reverse bias voltage, VR, was kept constant and equal to 5 V.
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amplitudes are gathered in Fig. 7. For the highest pulse amplitudes the signal saturates, again indicating that electron emission takes place at defects strongly localized in space. The results of C–V profiling and DLTS measurements presented above as well as data obtained in similar experiments with trap B were used to suit measurement conditions for determining emission properties and spatial distributions of the traps. An additional determination of the concentration profiles measured by DDLTS technique is shown in Fig. 8. Two pulses of different voltage levels, V1 and V2, were applied to charge the traps in a part of the space charge region and the defect concentrations were calculated using the method developed by Lefevre and Schulz [9]. The spatial profiles in Fig. 8 show that traps A and B accumulate at a depth of 0.76 μm. The maximum deficit of free carriers given by the profile in Fig. 2 occurs at about 0.79 μm. However, it should be mentioned that in spite of a quite good correspondence between the profiles determined by DLTS and C–V technique, the abruptness of the profiles as well as positions of extreme values are determined with a spatial resolution equal at least to the Debye length, LD = 0.03 μm [10]. The maximum values of A and B concentrations were found to be 2 × 1015 cm− 3 and 3 × 1015 cm− 3, respectively. Arrhenius plots, shown in Fig. 9, give activation energies at 0.16 eV for trap A and 0.52 eV for trap B. This is close to deep traps at 0.16–0.17 eV and 0.48–0.49 eV found in both InAs/ GaAs QD structures and reference samples containing an InAs QW inserted into a GaAs matrix [3]. Similar traps were also found in samples containing InAs QW/QD investigated by the present authors [11]. They correspond to traps labelled EL10 (0.17 eV) and EL4 (0.51 eV) which were found in MBE bulk GaAs and interpreted as related to chemical impurities, characteristic for GaAs growth under As-rich conditions [12,13]. However, the latter were found at a much lower concentration, of the low 1013 cm− 3 range, as compared to concentration of our defects. An arsenic overpressure in our experiment strongly suggests that increased gallium vacancy concentration may be responsible for the formation of these defects. The statement is in the agreement with the conclusion of Biswas et al. [14], which was based on an increase in electron trap concentration after annealing in an arsenic overpressure.
Fig. 7. Peak frequency and relative peak height for trap A vs. filling pulse amplitude.
Fig. 8. Depth profiles of traps A and B.
More recently, Lin et al. [3] have found that the traps are coexisting with the InAs layer. Considering the traps as defectimpurity complexes, the authors propose that the strain field, induced by the lattice mismatch between the GaAs and InAs, may enhance their creation and localize them by inducing their migration from neighboring layers. Another explanation, proposed by the same authors, is that the energy levels are related with point defects caused by the strain during the InAs/GaAs growth process. This is probably not consistent with our results, obtained from a material where strain would not be expected. The behaviour of trap A is similar to published observations for quantum confined energy levels related to QDs [1]. This similarity, nearly the same activation energies, and the tendency of defects to agglomerate at the interrupted interface, makes it difficult to differentiate between the defect-related levels and the ground state of QDs. Most data reported for the ground state of InAs/GaAs QDs are in the range 0.16–0.19 eV [1–3]. However, an exceptional high value of 0.45 eV for the activation energy was also reported together with a requirement of a high barrier of
Fig. 9. Semi-logarithmic plot of en/T2 as a function of 1/T for traps A and B in samples with GaAs/GaAs interface grown by MBE-interruption growth technique. The data obtained are indicated by experimental points and solid lines. The thermal emission rates were calculated from positions of peaks in frequency scan DLTS spectra at different temperatures. Also, included in the figure are data for the 0.48–0.49 eV and 0.16–0.17 eV traps revealed in InAs/ GaAs low dimensional structures [3]. The latter is indicated by dashed lines. Solid lines represent traps EL4 (0.51 eV) and EL10 (0.17 eV) found in as-grown MBE GaAs [13].
M. Kaniewska, O. Engström / Materials Science and Engineering C 27 (2007) 1069–1073
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0.30 eV for electron capture by the InAs/GaAs QDs [15]. Taking data from Fig. 1(a) in Ref. [15], a position of the associated level in the Arrhenius plot and the energy of 0.45 eV correspond to defect B that was observed at a lower energy of 0.46 eV as studied in samples containing InAs [11].
for preparing the samples. This work was supported by Polish Ministry of Science and Education (project nos. 3T11B00729 and 2.12.118) and by the Swedish Foundation for Strategic Research (Nanodev Centre of Excellence).
4. Conclusions
References
Two main electron traps A and B were identified at the GaAs/ GaAs interface grown under conditions typical for InAs/GaAs QD growth. Both traps are acceptor-like with activation energies of 0.16 and 0.52 eV below the conduction band edge, respectively. They agglomerate at the GaAs/GaAs interrupted interface and have a concentration of (2–3) × 1015 cm− 3 at their maxima, comparable to the net background doping concentration. The present study shows that even if the traps are commonly found in InAs/GaAs QD/QW structures, one must conclude that strain is not a pre-requisite. Instead an excess of As seems to be the main reason for their origin. As trap A has an energy level often appearing in InAs/GaAs QD samples, it may cause difficulties in identifying quantum confined levels. However, comparing the apparent capture cross sections for trap A [11] with the corresponding quantity obtained experimentally [5] and needed to simulate DLTS data from the QDs [16], one finds a difference of about 5 orders of magnitude, which can be used to differentiate the two emission sources from each other. Acknowledgements The authors would like to thank M. Sadeghi, H. Frederiksen and J. Halonen of the Chalmers MC2 Nanofabrication Facility
[1] C. M. A. Kapteyn, F. Heinrichsdorff, O. Stier, R. Heitz, M. Grudmann, N. D. Zakharov, D. Bimberg, Pys. Rev. B 60 (1999-II) 14 265. [2] O. Engström, M. Malmkvist, Y. Fu, H.Ö. Olafsson, E.Ö. Sveinbjörnsson, Appl. Phys. Lett. 83 (2003) 3575. [3] S.W. Lin, C. Balocco, M. Missous, A.R. Peaker, A.M. Song, Phys. Rev., B 72 (2005) 165302. [4] M. Kaniewska, O. Engström, A. Barcz, M. Pacholak-Cybulska, Mater. Sci. Semicond. Process. 9 (2006) 36. [5] O. Engström, M. Kaniewska, Y. Fu, J. Piscator, M. Malmkvist, Appl. Phys. Lett. 85 (2004) 2908. [6] L.C. Kimerling, J. Appl. Phys. 45 (1974) 1839. [7] D. Pons, J. Appl. Phys. 55 (1984) 3644. [8] D. Darwich, B. Massarani, J. Appl. Phys. 88 (2000) 794. [9] H. Lefevre, M. Schultz, Appl. Phys. 12 (1977) 45. [10] W.C. Johnson, P.T. Panousis, IEEE Trans. Electron Devices ED-18 (1971) 965. [11] M. Kaniewska, O. Engström, M. Pacholak-Cybulska, M. Sadeghi, 8th Int. Conf. On Expert Evaluation and Control of Compound Semicond. Mat., May 14-17, 2006, Cadiz, Spain (in press in Physica Status Solidi). [12] D.V. Lang, A.Y. Cho, A.C. Gossard, M. Ilegems, W. Wiegmann, J. Appl. Phys. 47 (1976) 2558. [13] G.M. Martin, A. Mitonneau, A. Mircea, Electron. Lett. 13 (1977) 191. [14] D. Biswas, P.R. Berger, U. Das, J.E. Oh, P.K. Battacharya, J. Electron. Mater. 18 (1989) 137. [15] H.L. Wang, D. Ning, H.J. Zhu, F. Chen, H. Wang, X.D. Wang, S.L. Feng, J. Cryst. Growth 208 (2000) 107. [16] O. Engström, A. Eghtedari, M. Kaniewska, J. Appl. Phys (submitted for publication).
Deep traps at GaAs/GaAs interface grown by MBE-interruption growth technique M. Kaniewska a,⁎, O. Engström b a
Department of Analysis of Semicoductor Nanostructures, Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw, Poland b Department of Microtechnology and Nanoscience, Chalmers University of Technology, SE-412 96 Göteborg, Sweden Received 6 September 2006; accepted 9 September 2006 Available online 19 October 2006
Abstract Electron trapping centers at the GaAs/GaAs interface grown by molecular beam epitaxy (MBE)-interruption growth technique have been studied by capacitance versus voltage (C–V) measurements and deep level transient spectroscopy (DLTS). Two main electron traps have been revealed with activation energies at 0.16 eV and 0.52 eV from the conduction band. Inhomogeneous spatial distributions of the traps, obtained by DLTS profiling, indicate that they are agglomerated at the interrupted interface on a concentration level of (2–3) × 1015 cm− 3 at their maximum. Their behaviour is typical of acceptor-like traps when investigating by C–V profiling as a function of temperature. Based on a comparison made with electron traps in MBE-GaAs as well as with the traps in InAs/GaAs quantum dot/quantum well (QD/QW) structures, we conclude they are the well-known EL10 and EL4 defects, respectively, and their concentrations are growth condition dependent. They may be point defect-impurity complexes. Their presence may cause interpretation and application problems of the low-dimensional InAs/GaAs structures. © 2006 Elsevier B.V. All rights reserved. Keywords: MBE-GaAs/GaAs growth-interrupted interface; Defects; DLTS; C–V profiling
1. Introduction In order to benefit from the advantages obtained by quantum dot systems in photonic and electronic devices, it is important to keep the crystal in the vicinity of the quantum dots (QDs) free from defects and impurities. Accordingly, a recently growing activity has appeared in the literature for studying intrinsic InAs/ GaAs QD phenomena and QD related defects by electrical methods like deep level transient spectroscopy (DLTS) and capacitance versus voltage (C–V) measurements [1–5]. For InAs/ GaAs QDs, a large difference in optimum ramping growth temperatures for the InAs layer (480–510 °C) and the GaAs buffer and cap layers (580–630 °C), respectively, is necessary to grow the sandwiched InAs/GaAs structure. This leads to poorer crystal perfection of the GaAs layers at the InAs/GaAs interface, which together with the strain present in the structures may be responsible for deep-level defect formation. Therefore, in order to ⁎ Corresponding author. Tel.: +48 22 5487793; fax: +48 22 8470631. E-mail address: [email protected] (M. Kaniewska). 0928-4931/$ - see front matter © 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.msec.2006.09.012
suit the growth conditions, the QDs structures are usually fabricated with the growth interruption technique under an excess of As. It is considered as a method, which enables to improve the quality of the InAs/GaAs interfaces, by performing the growth at a reduced temperature. In a recent DLTS study of InAs/GaAs QD structures we discovered the presence of several deep traps, accumulated in the vicinity of the QD plane [4]. This tendency of traps to agglomerate at the InAs/GaAs interface may cause difficulties in differentiating them from intrinsic QD levels. Therefore, to make the interpretation easier, it is important to have information on trap-related levels in reference samples. This paper reports results of an electrical study on deep states in layered GaAs reference structures designed as Schottky diodes, without any InAs insertion, but otherwise prepared under typical of QD growth conditions. 2. Experimental The GaAs buffer and cap layers were grown by solid source MBE at a substrate temperature of 580 °C and were intentionally
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doped with Si to approximately 1 × 1016 cm− 3. The substrates were (001)-oriented GaAs wafers. The epitaxial procedure was performed as similar as possible to the cycle used when preparing QDs [2]. In that process, prior to growth of the cap layer, the substrate temperature is decreased to 510 °C, followed by a deposition of 3–4 monolayers (MLs) InAs. The InAs growth is done under a repeated sequence of 0.1 ML InAs followed by a 2-s growth interruption under an excess of As2 until the InAs layer reaches the target thickness where QDs are shaped by the Stranski-Krastanov effect. In the present reference samples, the same procedure was performed with the exception that the In source of the MBE facility was never opened. This resulted in a GaAs cap layer grown on a GaAs buffer layer produced under the same conditions as when preparing QD samples. AuGeNi ohmic contacts were fabricated by annealing at 400 °C for 1 min. Schottky contacts were fabricated by evaporating gold dots of 1 mm diameter. C–V and DLTS measurements were performed by means of a lock-in type DLS-83E system (Semitrap, Hungary) operated at 1 MHz in temperature and frequency scan modes. 3. Results and discussion C–V measurements were performed at 1 MHz signal frequency and the carrier concentration profile was calculated using the depletion approximation formula: −1 2 d 1 NCV ðW Þ ¼ 2 ; ð1Þ A qe dV C 2 where ε is the dielectric constant, q is the electron charge, and A is the area of the Schottky barrier. NC–V(W) is the apparent free electron concentration at the edge of the space charge layer with thickness W. A typical dependence of capacitance and shallow dopant concentration on the reverse bias voltage for the samples studied at 119 K is shown in Fig. 1. The dip followed by a peak, seen in the profile of Fig. 1, is very similar to that observed by Kimerling [6] in proton bombarded n-type Si and indicates the
Fig. 1. C–V characteristics and shallow doping concentration as a function of the reverse bias voltage of a structure used to study states at the GaAs/GaAs growth-interrupted interface.
Fig. 2. Apparent free-carrier concentration vs. distance into the structure from the surface. Measurement temperatures are indicated for each profile.
presence of an acceptor-like trap with an inhomogenous distribution. The characteristic peak is observed for measurement condition such that, ω(ΔVosc) N en N ω(ΔVc), i.e. the frequency of the oscillating voltage, ω(ΔVosc), employed in the capacitance measurement, is fast compared with the thermal emission rate of carriers from traps, en, while the latter, in turn, is fast compared with the frequency of the variation in bias voltage, ω(ΔVc). The conditions governing the data shown in Fig. 1 fulfill these relations. For this case, not only uncovered charge at the edge of the depletion region but also charge in traps located at a distance of λ from the edge, where the Fermi level crosses the deep level, contribute to the differential capacitance. The calculated carrier profile nearly reflects a triangular shape [6] for the acceptor distribution, and in addition it exhibits the overshoot in carrier concentration when the down slope of the trap distribution is reached while changing the bias voltage. The peak is an indicator that acceptors at high concentration and with a sharp distribution are present. Since en is thermally activated, the anomaly should disappear when measurements are performed at low temperature, where ω(ΔVc) N en. The free-carrier depth profile was studied as a function of temperature and data were obtained for various temperatures with results as shown in Fig. 2. C–V data were used to convert the voltage-axis to spatial scale from the differential diode capacitance and the depth W was calculated using W = εA/C. When measuring at 119 K, the peak is located at 0.92 μm, followed by a shift to about 0.84 μm at 250 K, which is accompanied by a new peak appearing at about 1.02 μm. This indicates the presence of a second, acceptor-like trap. As the temperature is lowered to 25 K, the frequencies fulfill the condition ω(ΔCc) N en. The two peaks disappear and an accurate profile is obtained as a result of the combined compensation effect of the two traps. A typical DLTS spectrum obtained in the temperature scan mode is presented in Fig. 3. Two main traps, labeled A and B, were revealed. Due to a non-homogenous depth distribution, appropriate measurement conditions had to be determined. For this purpose, DLTS in the frequency mode was used and DLTS signal height as a function of the pulse repetition frequency, f,
M. Kaniewska, O. Engström / Materials Science and Engineering C 27 (2007) 1069–1073
Fig. 3. Typical DLTS spectrum obtained with the samples in the temperature scan mode. The steady-state bias, VR, and voltage level of carrier-filling pulse, V1, were equal to VR = 4V and V1 = 0, respectively. The emission rate window, en was 543 s− 1.
was studied at constant temperature for various reverse bias voltages and various pulse amplitudes as well. The 119 K frequency spectra for trap A with the reverse bias voltage as a parameter are shown in Fig. 4. As seen in Fig. 5, the peak frequency decreases with increasing VR up to VR = 4.3 V and turns back to higher values when VR is further increased. At the same time, the relative change in DLTS signal capacitance, ΔC/CR, goes through a maximum as VR is varied (Fig. 5). The
Fig. 4. DLTS signal height as a function of pulse repetition frequency at T = 119 K for various reverse bias voltages, VR. The voltage level of carrier filling pulse was kept constant and equal to 0.
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Fig. 5. Peak frequency and relative peak height vs. reverse bias voltage. Data extracted from Fig. 4 for trap A.
peak at lower biases seems to be influenced by a second shallower energy level recognized in Fig. 4 as a non-symmetry introduced at higher frequencies. The decrease in peak frequency for the lower VR values indicates that trap A has a certain spread in energy levels, while the increase of this quantity at higher VR is expected to occur due to an increased emission rate influenced by electric field effects. Furthermore, for the lowest voltage levels, the DLTS signals might be underestimated due to the so-called transition region effect [7,8]. However, in agreement with the C–V data shown in Figs. 1 and 2, further results obtained by double correlated DLTS (DDLTS) profiling [9], allowing to avoid the transition region effect, show that the trap has a strong inhomogeneous depth distribution. The measurements were done at relatively low biases to avoid the influence of the electric field. Fig. 6 shows the 119 K DLTS spectra for trap A with the voltage level of filling pulse as a parameter. A growing signal is observed when keeping the emission bias voltage, VR, fixed at 5 V and increasing the filling pulse amplitude. Here, the peak frequencies are constant due to the constant VR value, which empties electrons captured by the trap level distribution equally in the DLTS measurement. More detailed data for various pulse
Fig. 6. DLTS signal height as a function of pulse repetition frequency at T = 119 K for various voltage levels of filling pulse, V1. The reverse bias voltage, VR, was kept constant and equal to 5 V.
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amplitudes are gathered in Fig. 7. For the highest pulse amplitudes the signal saturates, again indicating that electron emission takes place at defects strongly localized in space. The results of C–V profiling and DLTS measurements presented above as well as data obtained in similar experiments with trap B were used to suit measurement conditions for determining emission properties and spatial distributions of the traps. An additional determination of the concentration profiles measured by DDLTS technique is shown in Fig. 8. Two pulses of different voltage levels, V1 and V2, were applied to charge the traps in a part of the space charge region and the defect concentrations were calculated using the method developed by Lefevre and Schulz [9]. The spatial profiles in Fig. 8 show that traps A and B accumulate at a depth of 0.76 μm. The maximum deficit of free carriers given by the profile in Fig. 2 occurs at about 0.79 μm. However, it should be mentioned that in spite of a quite good correspondence between the profiles determined by DLTS and C–V technique, the abruptness of the profiles as well as positions of extreme values are determined with a spatial resolution equal at least to the Debye length, LD = 0.03 μm [10]. The maximum values of A and B concentrations were found to be 2 × 1015 cm− 3 and 3 × 1015 cm− 3, respectively. Arrhenius plots, shown in Fig. 9, give activation energies at 0.16 eV for trap A and 0.52 eV for trap B. This is close to deep traps at 0.16–0.17 eV and 0.48–0.49 eV found in both InAs/ GaAs QD structures and reference samples containing an InAs QW inserted into a GaAs matrix [3]. Similar traps were also found in samples containing InAs QW/QD investigated by the present authors [11]. They correspond to traps labelled EL10 (0.17 eV) and EL4 (0.51 eV) which were found in MBE bulk GaAs and interpreted as related to chemical impurities, characteristic for GaAs growth under As-rich conditions [12,13]. However, the latter were found at a much lower concentration, of the low 1013 cm− 3 range, as compared to concentration of our defects. An arsenic overpressure in our experiment strongly suggests that increased gallium vacancy concentration may be responsible for the formation of these defects. The statement is in the agreement with the conclusion of Biswas et al. [14], which was based on an increase in electron trap concentration after annealing in an arsenic overpressure.
Fig. 7. Peak frequency and relative peak height for trap A vs. filling pulse amplitude.
Fig. 8. Depth profiles of traps A and B.
More recently, Lin et al. [3] have found that the traps are coexisting with the InAs layer. Considering the traps as defectimpurity complexes, the authors propose that the strain field, induced by the lattice mismatch between the GaAs and InAs, may enhance their creation and localize them by inducing their migration from neighboring layers. Another explanation, proposed by the same authors, is that the energy levels are related with point defects caused by the strain during the InAs/GaAs growth process. This is probably not consistent with our results, obtained from a material where strain would not be expected. The behaviour of trap A is similar to published observations for quantum confined energy levels related to QDs [1]. This similarity, nearly the same activation energies, and the tendency of defects to agglomerate at the interrupted interface, makes it difficult to differentiate between the defect-related levels and the ground state of QDs. Most data reported for the ground state of InAs/GaAs QDs are in the range 0.16–0.19 eV [1–3]. However, an exceptional high value of 0.45 eV for the activation energy was also reported together with a requirement of a high barrier of
Fig. 9. Semi-logarithmic plot of en/T2 as a function of 1/T for traps A and B in samples with GaAs/GaAs interface grown by MBE-interruption growth technique. The data obtained are indicated by experimental points and solid lines. The thermal emission rates were calculated from positions of peaks in frequency scan DLTS spectra at different temperatures. Also, included in the figure are data for the 0.48–0.49 eV and 0.16–0.17 eV traps revealed in InAs/ GaAs low dimensional structures [3]. The latter is indicated by dashed lines. Solid lines represent traps EL4 (0.51 eV) and EL10 (0.17 eV) found in as-grown MBE GaAs [13].
M. Kaniewska, O. Engström / Materials Science and Engineering C 27 (2007) 1069–1073
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0.30 eV for electron capture by the InAs/GaAs QDs [15]. Taking data from Fig. 1(a) in Ref. [15], a position of the associated level in the Arrhenius plot and the energy of 0.45 eV correspond to defect B that was observed at a lower energy of 0.46 eV as studied in samples containing InAs [11].
for preparing the samples. This work was supported by Polish Ministry of Science and Education (project nos. 3T11B00729 and 2.12.118) and by the Swedish Foundation for Strategic Research (Nanodev Centre of Excellence).
4. Conclusions
References
Two main electron traps A and B were identified at the GaAs/ GaAs interface grown under conditions typical for InAs/GaAs QD growth. Both traps are acceptor-like with activation energies of 0.16 and 0.52 eV below the conduction band edge, respectively. They agglomerate at the GaAs/GaAs interrupted interface and have a concentration of (2–3) × 1015 cm− 3 at their maxima, comparable to the net background doping concentration. The present study shows that even if the traps are commonly found in InAs/GaAs QD/QW structures, one must conclude that strain is not a pre-requisite. Instead an excess of As seems to be the main reason for their origin. As trap A has an energy level often appearing in InAs/GaAs QD samples, it may cause difficulties in identifying quantum confined levels. However, comparing the apparent capture cross sections for trap A [11] with the corresponding quantity obtained experimentally [5] and needed to simulate DLTS data from the QDs [16], one finds a difference of about 5 orders of magnitude, which can be used to differentiate the two emission sources from each other. Acknowledgements The authors would like to thank M. Sadeghi, H. Frederiksen and J. Halonen of the Chalmers MC2 Nanofabrication Facility
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