Defect annealing processes for polycrystalline silicon thin-film solar cells

Materials Science and Engineering B 178 (2013) 670–675

Contents lists available at SciVerse ScienceDirect

Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb

Short communication

Defect annealing processes for polycrystalline silicon thin-film solar cells S. Steffens a,∗ , C. Becker a , J.-H. Zollondz b , A. Chowdhury c , A. Slaoui c , S. Lindekugel d , U. Schubert e , R. Evans e , B. Rech a a

Helmholtz-Zentrum Berlin, Berlin, Germany CSG Solar AG, Thalheim, Germany L’Institut d’Électronique du Solide et des Systèmes, Strasbourg, France d Fraunhofer-Institut für Solare Energiesysteme, Freiburg, Germany e Suntech R&D Australia Pty Ltd, Sydney, Australia b c

a r t i c l e

i n f o

Article history: Received 2 July 2012 Received in revised form 30 October 2012 Accepted 2 November 2012 Available online 15 November 2012 Keywords: Rapid thermal processing Annealing Defects Silicon Solar cells

a b s t r a c t A variety of defect healing methods was analyzed for optimization of polycrystalline silicon (poly-Si) thin-film solar cells on glass. The films were fabricated by solid phase crystallization of amorphous silicon deposited either by plasma enhanced chemical vapor deposition (PECVD) or by electron-beam evaporation (EBE). Three different rapid thermal processing (RTP) set-ups were compared: A conventional rapid thermal annealing oven, a dual wavelength laser annealing system and a movable two sided halogen lamp oven. The two latter processes utilize focused energy input for reducing the thermal load introduced into the glass substrates and thus lead to less deformation and impurity diffusion. Analysis of the structural and electrical properties of the poly-Si thin films was performed by Suns-VOC measurements and Raman spectroscopy. 1 cm2 cells were prepared for a selection of samples and characterized by I–V-measurements. The poly-Si material quality could be extremely enhanced, resulting in increase of the open circuit voltages from about 100 mV (EBE) and 170 mV (PECVD) in the untreated case up to 480 mV after processing. © 2012 Elsevier B.V. All rights reserved.

1. Introduction Polycrystalline silicon thin-film technologies are a promising option for cost-effective solar module production, with the potential to exceed the current photovoltaic efficiency limitations of existing silicon based thin-film technologies, and combine the advantages of crystalline silicon (no degradation, high electrical quality) with the advantages of thin film technologies (low cost, low material consumption). Fabrication is done by deposition of less than 2 ␮m thin silicon layers and a subsequent solid phase crystallization (SPC) process. Necessary prerequisites are excellent electronic properties of these poly-Si films. In order to tap the full potential of poly-Si material, the application of defect healing processes such as rapid thermal processing and hydrogen passivation (HP) is indispensable after deposition and crystallization [1]. Before RTP and HP the material suffers from high defect densities reducing the lifetime of the minority carriers thus limiting the maximum achievable open circuit voltage. This work investigates the influence of three different rapid thermal processing techniques on the performance of polycrystalline silicon thin film solar cells.

Rapid thermal processing has been extensively used over the last two decades for the annealing of point-like and extended defects and activation of dopants in polycrystalline silicon-based solar cells [1–5]. While for these experiments halogen lamp powered ovens and furnaces have been used, new approaches utilize focused energy input to anneal the silicon thin films [6,7]. In this work we explore the potential of new annealing techniques like laser treatment and annealing by focused halogen lamp power compared to a conventional rapid thermal annealing furnace. These methods were applied to polycrystalline silicon thin films deposited by plasma enhanced chemical vapor deposition and electron beam evaporation. Compared to PECVD the latter, being an emerging technology in silicon photovoltaics [8,9], comprises two main advantages, i.e. high deposition rates and the absence of toxic process gases. All annealing experiments presented in this work have been done in the framework of the European project “PolySiMode” (Improved Polycrystalline-Silicon Modules on Glass Substrates).

2. Material and methods 2.1. Substrate

∗ Corresponding author. Tel.: +49 30 8062 41385. E-mail addresses: [email protected] (S. Steffens), [email protected] (J.-H. Zollondz). 0921-5107/$ – see front matter © 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mseb.2012.11.002

SiN-coated borosilicate glass was used as a substrate for the deposition of polycrystalline silicon thin films. 100 nm thick SiN

S. Steffens et al. / Materials Science and Engineering B 178 (2013) 670–675

671

layers have been deposited on Schott Borofloat (BF) 33 glass (3.3 mm) by CSG Solar in an industrial PECVD reactor. The SiN serves as anti-reflection coating and diffusion barrier preventing impurities from the glass substrate reaching the silicon films during high-temperature treatments. 2.2. Deposition of silicon On these BF/SiN substrates a stack of silicon layers was deposited, consisting of a highly phosphorous doped 30 nm thick n+ emitter layer, a lightly boron doped 1.6 ␮m thick p− absorber layer and a highly boron doped 50 nm thick p+ layer which serves as a back surface field, leading to a sample structure as follows: BF glass/SiN/n+ -Si/p− -Si/p+ -Si. Deposition of the n+ layer was done by PECVD, the boron doped layers were deposited either by PECVD using a gas mixture of diborane and silane or by electron beam evaporation of silicon material with co-deposition from a boron effusion cell. Three different combinations of substrate and deposition method were manufactured for this work: (1) Electron beam evaporation on smooth BF/SiN/n+ substrates (2) Plasma enhanced CVD on smooth BF/SiN substrates (3) Plasma enhanced CVD on rough BF/SiN substrates Roughening of the substrates was done by abrading the deposition side of the Borofloat glass prior to the deposition of the SiN layer. The abrasion etch process involves dry blasting with SiC grit and a subsequent HF etching process as described in [10]. While in PECVD the film’s growth is conformal, EBE is a physical vapor deposition method with a directional flux of the silicon atoms. Due to the directionality of the silicon deposition during EBE, rough substrates are non-compatible with this method leading to minor electrical quality [11]. That is why this combination has not been considered here. The silicon layers were deposited in the amorphous phase at a substrate temperature of about 300 ◦ C for both deposition techniques. Finally, the samples were cut into pieces with sizes from of 2.5 cm × 2.5 cm to 5 cm × 5 cm. 2.3. Post-deposition treatments Crystallization of the amorphous layers was done by a solid phase crystallization process at 600 ◦ C with slow heating and cooling rates (1 K/s) under nitrogen atmosphere, leading to grain sizes of up to 5 ␮m [12,13]. The crystallized samples were then subject to different defect annealing techniques as described below. After annealing all samples were processed in a hydrogen-plasma passivation tool in order to further reduce the amount of electrically active defects [14–16]. An industrial custom-built prototype inline remote plasma system was used where the samples are exposed to atomic hydrogen for 4 min at 610 ◦ C and during 14 min of cooling down to a temperature of 300 ◦ C. Three different RTP techniques were applied to the above described silicon stacks on smooth and rough glass substrates: A conventional rapid thermal annealing (RTA) oven, a laser annealing (LA) setup and a zone melting recrystallization (ZMR) tool. 2.3.1. Rapid thermal annealing The RTA system used in this work is the Heatpulse 210T from AG Associates. It consists of a quartz chamber, two banks (upper and lower) of tungsten-halogen lamps and a microcontroller unit. The samples are placed on a 4 graphite carrier, which is situated between the upper and lower row of halogen lamps. There are 13 lamps with a power of 1.5 kW each. Temperatures up to 1050 ◦ C are possible. The maximum and minimum heating rate is 200 K/s and 0.7 K/s, respectively. A thermocouple is installed right next to the

Fig. 1. RTA temperature profiles for 900 ◦ C and 950 ◦ C and a plateau time of 60 s. It involves slow heating through the transformation regime (1), fast heating (2) to the plateau temperature (3) and slow cooling through the transformation regime.

sample carrier to monitor the temperature. Its signal is processed by the microcontoller to regulate the temperature profiles. During annealing the chamber is under nitrogen atmosphere. For the rapid thermal processing of silicon coated glass samples a temperature profile was chosen that takes into account the transformation range of Borofloat 33. The transformation temperature of Borofloat 33 is 525 ◦ C, the transformation range lies within its strain point (518 ◦ C) and its annealing point (560 ◦ C) [17]. Below the strain point the thermal expansion coefficient of the borosilicate glass of 3.3 × 10−6 /K matches that of silicon (2.6 × 10−6 /K). Within the transformation range the thermal expansion properties of the two materials diverge. The non-linear behavior of the glass’ expansion coefficient necessitates slow heating and cooling rates in order to avoid cracking. Above 560 ◦ C the glass softens rendering fast temperature ramps possible. The samples were treated with temperatures from 900 ◦ C to 1050 ◦ C. The plateau time was varied from 30 s to 150 s. A plot of typical temperature profiles for our annealing experiments at 60 s is depicted in Fig. 1. Note that the plateau time for the thermocouple is 100 s which results in an effective plateau time of 60 s for the 3.3 mm thick Borofloat samples. The thermal mass of the glass substrate also assures that the sample will not follow the overshoots at the beginning of the plateau. The heating phase is divided in two parts: First there is a slow heating ramp (1) through the transformation range. At temperatures well beyond the transformation range, a very fast ramp (2) of more than 150 K/s is applied for heating the system to the desired plateau temperature within a few seconds. This maximum temperature is held constant for the chosen plateau time (3). At the end of the plateau the halogen lamps are shut down to let the system cool down (4) to below 250 ◦ C when the chamber is opened and the samples are removed from the carrier. The cooling rate when passing the transformation range is around ∼1 K/s. 2.3.2. Laser annealing Laser induced annealing was carried out by a dual wavelength set-up (808 nm and 940 nm) manufactured by LASERLINE Inc. with a maximum total power of 3 kW. Prior to the annealing process the samples were preheated to temperatures around 430 ◦ C by a hot plate substrate holder. During laser treatment, the sample holder is moved perpendicular to the line shaped focus. The dimensions of the laser focal line are 0.8 cm × 10 cm. The scan speed of the sample was varied from 40 mm/min to 100 mm/min. Irradiation of the silicon films was done through the glass side with a maximum laser

672

S. Steffens et al. / Materials Science and Engineering B 178 (2013) 670–675

output power of 3 kW, but it should be noticed that there is always a ∼50% optical laser power loss before reaching the glass surface. 2.3.3. Zone-melting recrystallization In silicon photovoltaics zone-melting recrystallization is a method commonly employed for grain enlargement through liquid phase crystallization, where a small molten zone is scanned across the thin film [18–20]. For this work the ZMR set-up was used as a substitution for a conventional RTA oven, applying local temperatures comparable to the ones of the RTA process (<1100 ◦ C). Dealing with temperatures well below the melting point of silicon (Tm = 1414 ◦ C) the expression zone-melting recrystallization is somewhat misleading. ZMR in this work means using the ZMR set-up for annealing processes in the solid phase. The principle of this technique is also based on tungsten halogen lamps as heat sources: An array of linear halogen lamps underneath the sample, and a single linear lamp in an elliptical reflector above the sample were used. In this work the ZMR 100 system developed at Fraunhofer ISE was used [7]. The lower heater array consists of 15 halogen lamps providing 4.5 kW power each, producing a heated area of approximately 24 cm × 28 cm. The upper heater is a 2 kW halogen lamp with a small coil diameter of 1.5 mm positioned in the first focal line of the elliptical reflector. The second focal line lies within the silicon film plane. The samples were placed inside a quartz tube under nitrogen atmosphere. During the annealing process the tube and the sample stay fixed while the heater is moved by a gearless motor resulting in a line scan of the focused halogen lamp power across the silicon thin film. At a constant sample speed of 40 mm/min the power of the focus lamp and the lamp field was varied. The lamp field is used to pre-heat the sample to temperatures between 700 ◦ C and 800 ◦ C. The rapid processing is then done by the scanning of the focused halogen lamp power. 2.4. Characterization methods 2.4.1. Suns-VOC analysis This method was introduced by Sinton and Cuevas in 2000 [21] and is used in this work to obtain the open circuit voltage (VOC ) of the silicon layer stacks. Suns-VOC is a quasi-steady state measurement for determining the electrical properties of semiconductors and an established method for solar cell characterization. The setup used in this work consists of a xenon flash lamp, an inbuilt reference solar cell which measures the light intensity and two metal probes to contact the samples. For our thin film solar cell on glass configuration we used a superstrate sample holder allowing for illumination from the glass side while contacting the silicon from the rear side. In order to contact the buried n+ emitter a wet chemical etch process was applied to partially etch the polycrystalline silicon down to the n+ -layer. The etch solution contains HF (50%), H3 PO4 (85%), HNO3 (65%) and deionized water. A duration of about 5 min is needed to expose the buried n+ -layer. Contacting the samples can be done without metallization by simply placing one needle on the n+ -layer and one on the p+ -layer (since the open circuit voltage is measured current-free). The contacted sample is placed beneath the xenon lamp. Both the sample and the reference cell are illuminated by a single flash. Simultaneously the open circuit voltage of the sample and the light intensity given by the calibrated reference cell are measured time-dependent. Since the time constant of the light intensity decay is around ∼2 ms while the life-time of the minority carriers in polycrystalline silicon is in the range of nanoseconds one lamp flash represents a series of measurements at different light intensities. From the respective intensity-voltage data points a pseudo-I–V-curve can be calculated. For this work the open circuit voltage Suns-VOC was derived characterizing the electronic material quality of the cell. To take into

Fig. 2. Overview of Suns-VOC values reached with the applied annealing parameters. The RTA plateau temperature and plateau time were varied. The scan speed of the laser-annealed sample was tuned at a fixed laser power. Variation of the focus lamp power was done during ZMR processing while keeping the scan speed constant.

account local inhomogeneities the position of the p+ needle was varied across the films surface. The Suns-VOC values given in this work correspond to the average of 4 measurements. 2.4.2. Raman spectroscopy Raman spectroscopy was used to determine the crystallinity of the silicon layers by measuring the FWHM of the characteristic transverse optical (TO) phonon peak of crystalline silicon at 520 cm−1 . The spectra were measured with an excitation wavelength of  = 632.8 nm. A penetration depth of 3 ␮m includes Raman contributions from both the surface and the bulk. 2.5. Fabrication of solar cells and I–V-measurements A selection of samples was chosen for solar cell device fabrication using a device structure developed by CSG Solar [22]. It involves a white back reflector and a patented rear side contacting scheme that removes the necessity of contacts at the glass interface thus excluding losses at the front side of the solar cell. Cell areas of 1 cm × 2 cm are defined by laser structuring. After processing, I–Vcharacteristics of the cells were measured in a solar simulator under illumination of an AM1.5 spectrum with 100 mW/cm2 . 3. Results and discussion 3.1. Suns-VOC measurements Fig. 2 shows the Suns-VOC values after hydrogen passivation versus the applied annealing parameters for all three combinations of substrate and deposition method. On the left hand side the open circuit voltages of the samples are plotted which were processed using the RTA oven. The right hand side shows the results of the laser-annealed samples. PECVD samples on abrasion etch substrates treated with the ZMR tool at various focus lamp intensities lead to the results depicted in the center of the Fig. 2. Open circuit voltages of up to 480 mV are reached with PECVD samples on abrasion etch substrates upon annealing in the RTA oven and the ZMR tool. The highest values for laser-treated samples are attained for electron beam evaporated films by applying low scan speeds (up to 472 mV).

S. Steffens et al. / Materials Science and Engineering B 178 (2013) 670–675

673

Fig. 4. Suns-VOC versus the full width at half maximum of the transverse optical phonon peak of crystalline silicon at 520 cm−1 (inset). Lines are drawn to guide the eye. Fig. 3. Open-circuit voltage as a function of RTA temperature for all three layer configurations in the post-annealing case (RTA only) and after hydrogen passivation (RTA+HP). Also depicted are the VOC regimes for non-annealed EBE samples right after crystallization (no defect healing) and when only hydrogen passivation is applied (HP only).

A correlation between the energy introduced into the sample and the obtained open circuit voltage can be observed for all three annealing techniques. In the case of RTA processing, an increase in plateau temperature and plateau time leads to higher VOC values. With increasing focus lamp power of the ZMR set-up the open circuit voltage is enhanced. In the case of laser annealing this corresponds to a reduced scan speed, resulting in higher temperatures and increasing the time a certain area is exposed to these elevated temperatures. This trend is observed for all investigated substrates and deposition techniques. It should be noted that even for the highest annealing temperatures no thermal damage was observed in the films using optical microscopy. Due to the careful heating and cooling through the transformation regime and the short exposure times to temperatures beyond 900 ◦ C cracking or flaking of the silicon film was successfully avoided. In more detail the correlation between temperature and open circuit voltage is shown in Fig. 3 for the RTA temperature variation. Keeping the plateau time constant (60 s), the plateau temperature was varied between 900 ◦ C and 1050 ◦ C. The respective open circuit voltages for the three kinds of samples before hydrogen passivation (RTA only) and after hydrogen passivation (RTA+HP) are shown. In addition, the VOC regimes for EBE samples are sketched when no defect annealing process was applied after crystallization (no defect healing) and when only hydrogen passivation is applied (HP only). Starting from the post-crystallization regime, rapid thermal annealing increases the open circuit voltage to values between 125 mV and 225 mV. Applying a hydrogen passivation process on the annealed samples (RTA + HP) boosts the VOC up to values between 390 mV and 470 mV. A comparison of the two different deposition methods PECVD and EBE on smooth substrates right after RTA shows that the open circuit voltages of the PECVD layers are much higher than the voltages of the electron beam evaporated layers, which stay below 150 mV. However, after hydrogen passivation the VOC values of the e-beam samples even exceed the ones reached with the PECVD material. Furthermore, the voltage difference of the three material configurations is less pronounced in the post-hydrogenation state than right after the annealing step, implying that compared to the PECVD material the EBE silicon layers contain larger

numbers of a defect species that are effectively passivated by the hydrogenation process and which are not annealed by the RTA process. After hydrogenation a significant increase of the Suns-VOC with increasing RTA temperature, can be observed indicating to reach even better results when going to temperatures beyond 1050 ◦ C. In contrast, before HP this clear dependency cannot be seen.

3.2. Raman spectroscopy The structural properties of the resulting poly-Si layers were characterized by Raman spectroscopy. The width of the Raman peak of the transverse optical (TO) phonon of crystalline silicon at 520 cm−1 indicates to what extent the periodic structure of the lattice is disturbed by defects or grain boundaries. These disturbances result in a broad FWHM of the respective peak curve. This peak width can be narrowed by the defect annealing processes. Raman spectra were measured for layer stacks on smooth glass substrates. In Fig. 4 the open circuit voltages are plotted against the respective FWHM of the TO peak. For comparison, the Raman spectrum for a monocrystalline silicon wafer was also determined leading to a FWHM value of 3.0 cm−1 . The highest VOC values correspond to the lowest peak widths. Intra-grain defects are effectively annealed and contributions from the amorphous regions at grain boundaries decrease resulting in a higher crystallinity shown by a small FWHM. This correlation was found to be independent of the applied rapid thermal processing technique RTA, LA or ZMR (indicated by squares, diamonds or triangles, respectively), implying that the structural evolution upon these techniques is similar when comparing the conventional oven annealing (RTA) with the novel concepts using a focused energy input (LA and ZMR). However, a dependency from the respective deposition method was found: We observed a shift of about 0.4 cm−1 between the EBE results (closed symbols) and the PECVD results (open symbols) indicating that EBE grown material possesses a better crystallinity in the post-RTP state than the PECVD material. A second interpretation is possible when looking at a fixed VOC level: Even though the peak width is smaller for EBE, the same open circuit voltage is reached like a PECVD sample with a broad TO peak giving rise to the assumption that in e-beam evaporated silicon the nature of the VOC limiting defects is not reflected in the Raman spectra.

674

S. Steffens et al. / Materials Science and Engineering B 178 (2013) 670–675

Fig. 5. I–V-curves of the three different substrate-material-configurations treated with an RTA temperature of 1050 ◦ C and a plateau time of 60 s.

3.3. I–V-measurements Solar cells were fabricated for a selection of samples. Fig. 5 shows the measured I–V-characteristics of the samples processed in the RTA oven for 60 s at a plateau temperature of 1050 ◦ C. In Fig. 6 the I–V-curve of a laser-annealed sample on smooth glass is depicted. When comparing the open circuit voltages of the I–Vcharacteristics (Fig. 5) with the Suns-VOC values before cell structuring a decrease is observed for all three kinds of sample, although a small increase in VOC was expected due to its logarithmic dependency from the cell’s current which is enhanced by the implementation of a back reflector during device processing. For the PECVD sample on abrasion etch substrate the open circuit voltage of 453 mV is significantly smaller than the Suns-VOC value of 480 mV measured before the cell structuring. Also the open circuit voltage of the EBE sample dropped from 466 mV down to a value of 449 mV, while the PECVD sample on smooth glass shows only a small loss from 450 mV to 447 mV. These losses may be attributed to shunts introduced during device processing when contacting the buried n+ layer via deep craters structured from the rear side of the solar cell. The device structure as well as the density of rear contacts is optimized for a certain RTA process developed by CSG Solar. When varying the thermal loading, as it was done in this work, it is very likely that due to the enhanced diffusion of dopants the doping

level is non-optimal for this particular type of device processing. To overcome this, the nominal doping level during deposition of the amorphous layers has to be tailored to the respective RTP technique. Comparing the two different deposition methods on smooth substrates, it can be seen that the cell fabricated using a poly-Si film formed from EBE a-Si films shows a higher JSC than the cell formed from PECVD films. A similar effect was found in [8] previously. It seems that EBE grown material exhibits a better material quality in terms of current collection. The assumption of a better structural quality is supported by the results of the Raman experiments shown before (Fig. 4). One possible reason might be, as found by Stradins et al. [23], that the average grain size is slightly higher for EBE compared to PECVD. This difference strongly depends on the deposition conditions and, since the grain size was not investigated for the presented cells, additional experimental work is needed to verify this conclusion. The highest total efficiency of 6.7% is reached for the PEVCD material deposited on an abrasion etched glass substrate and processed with an RTA temperature of 1050 ◦ C for 60 s. Since all three material-substrate combinations show similar open circuit voltages and fill factors the differences in efficiency are primarily due to the enhanced current collection attributed to the abrasion etch light trapping structures scattering the incoming photons, hence lengthening their path way in the photovoltaic material and increasing the probability of absorption. The best efficiency of 6.7% has to be compared to the record cell of CSG solar with an efficiency of 10.4% reached with PECVD grown material on a textured substrate [10]. The main reason for this difference is that no rear surface texturing was applied to the cells in this study leading to short circuit currents much lower than the 29.5 mA/cm2 of the record cell. In addition, a higher doping concentration of the n+ and p+ layer compared to the record cell probably led to minor shunts during the fabrication of the craterlike back-side contacts to the buried n layer, resulting in a reduced performance in terms of fill factor and open circuit voltage. A comparison of the I–V-characteristic of the best laser annealed PECVD sample on a smooth glass substrate (Fig. 6) with the best RTA treated sample of the same kind (solid line in Fig. 5) shows that the same result can be achieved applying the novel concept of focused energy input using a laser set-up. With this method the energy is deposited directly into the silicon film while at the same time the thermal load that is introduced into the glass substrate is reduced, which is a critical parameter in high temperature processes, governing diffusion of impurities from the glass into the silicon material. Additionally, diffusion of phosphor atoms from the n+ layer into the p- layer reduces the effective thickness of the active base region which leads to a decreasing open circuit voltage [3]. When applying too much thermal budget, also stress is induced and the glass is heavily deformed making a processing to solar modules difficult or even impossible as it was the case for ZMR annealed samples, that is why no I–V-curves were measured for this annealing technique.

4. Summary and conclusion

Fig. 6. I–V-curve of a PECVD sample on a smooth glass substrate laser annealed with a scan speed of 40 mm/min.

Defect annealing processes on polycrystalline silicon thin film solar cells on glass were investigated. Rapid thermal processing was done using a conventional RTA oven, a dual wavelength laser setup and a movable two sided halogen lamp oven commonly used for ZMR experiments. The influence of the different defect annealing techniques on electron beam evaporated silicon layers and on PECVD grown layers on both smooth and roughened glass substrates was characterized by Suns-VOC measurements, the analysis of Raman spectra and the solar cell performance.

S. Steffens et al. / Materials Science and Engineering B 178 (2013) 670–675

An increase of the open circuit voltage with increasing energy input into the silicon films is observed. Values above 470 mV are reached for laser annealed EBE samples and for PECVD grown samples on abrasion etch substrates annealed with RTA and ZMR, respectively. The enhanced Suns-VOC values correlate with a reduced FWHM of the TO peak of crystalline silicon, indicating an improvement of the material quality. Especially for electron beam deposited silicon thin films the novel concept of laser annealing seems to be a very powerful tool to heal defects and hence improve the electrical properties of the polycrystalline layers. A maximum cell efficiency of 6.7% was obtained for PECVD grown layers on abrasion etched substrates annealed at a temperature of 1050 ◦ C for 60 s using an RTA furnace. Acknowledgements The authors thank Stefan Common, Martin Muske and Janis Jeanne Merkel for technical support. This work was funded by the European commission under project entitled POLYSIMODE (contract no. 240826) References [1] P. Doshi, A. Rohatgi, M. Ropp, Z. Chen, D. Ruby, D.L. Meier, Solar Energy Materials and Solar Cells 41–42 (1996) 31–39. [2] F.N. Cubaynes, P.A. Stolk, J. Verhoeven, F. Roozeboom, P.H. Woerlee, Materials Science in Semiconductor Processing 4 (2001) 351–356. [3] M.L. Terry, A. Straub, D. Inns, D. Song, A.G. Aberle, Applied Physics Letters 86 (2005) 172108. [4] M.L. Terry, D. Inns, A.G. Aberle, Advances in OptoElectronics 2007 (2007) 83657. [5] B. Rau, T. Weber, B. Gorka, P. Dogan, F. Fenske, K.Y. Lee, S. Gall, B. Rech, Materials Science and Engineering B 159–160 (2009) 329–332. [6] A. Chowdhury, J. Schneider, J. Dore, F. Mermet, A. Slaoui, Applied Physics A 107 (2012) 653–659. [7] S. Lindekugel, L. Flatten, S. Janz, J. Dore, Proceedings of the 26th European Photovoltaic Solar Energy Conference, Hamburg, Germany, 2011, pp. 2779–2783.

675

[8] T. Sontheimer, C. Becker, F. Ruske, C. Klimm, U. Bloeck, S. Gall, O. Kunz, T. Young, R. Egan, J. Hüpkes, B. Rech, Proceedings of the 35th IEEE Photovoltaic Specialists Conference, Hawaii, USA, 2010, pp. 614–619. [9] R. Egan, M. Keevers, U. Schubert, T. Young, R. Evans, S. Partlin, M. Wolf, J. Schneider, D. Hogg, B. Eggleston, M. Green, F. Falk, A. Gawlik, G. Andrä, M. Werner, C. Hagendorf, P. Dogan, T. Sontheimer, S. Gall, Proceedings of the 24th European Photovoltaic Solar Energy Conference, Hamburg, Germany, 2009, pp. 2279–2285. [10] M. Keevers, T. Young, U. Schubert, M.A. Green, Proceedings of the 22nd European Photovoltaic Solar Energy Conference, Milan, Italy, 2007, pp. 1783–1790. [11] M. Werner, U. Schubert, C. Hagendorf, J. Schneider, M. Keevers, R. Egan, Proceedings of the 24th European Photovoltaic Solar Energy Conference, Hamburg, Germany, 2009, pp. 2482–2485. [12] T. Matsuyama, N. Terada, T. Baba, T. Sawada, S. Tsuge, K. Wakisaka, S. Tsuda, Journal of Non-Crystalline Solids 198–200 (1996) 940–944. [13] T. Sontheimer, S. Scherf, C. Klimm, C. Becker, B. Rech, Journal of Applied Physics 110 (2011) 063530. [14] N.M. Johnson, D.K. Biegelsen, M.D. Moyer, Applied Physics Letters 40 (1982) 882. [15] N.H. Nickel, N.M. Johnson, W.B. Jackson, Applied Physics Letters 62 (1993) 3285. [16] B. Gorka, B. Rau, P. Dogan, C. Becker, F. Ruske, S. Gall, B. Rech, Plasma Processes and Polymers 6 (2009) S36–S40. [17] http://www.schott.com/borofloat/german/attribute/thermic/index.html (found 06/2012), or offline: Schott Borofloat 33 Produktinformation. Herausgeber Schott Glas (2007). [18] T. Ishihara, Zone-melting recrystallization of Si films for solar cells, in: R.B. Bergmann (Ed.), Growth, Characterization and Electronic Applications of Amorphous and Crystalline Si Thin Films, Research Signpost, Kerala, India, 2002, pp. 79–100. [19] A. Takami, S. Arimoto, H. Morikawa, S. Hamamoto, T. Ishihara, H. Kumabe, T. Murotani, Proceedings of the 12th European Photovoltaic Solar Energy Conference, Amsterdam, The Netherlands, 1994, pp. 59–62. [20] H. Morikawa, Y. Nishimoto, H. Naomoto, Y. Kawama, A. Takami, S. Arimoto, T. Ishihara, K. Namba, Solar Energy Materials and Solar Cells 53 (1998) 23–28. [21] R.A. Sinton, A. Cuevas, Proceedings of the 16th European Photovoltaic Solar Energy Conference, Glasgow, UK, 2000, pp. 1152–1155. [22] M.A. Green, P.A. Basore, N. Chang, D. Clugston, R. Egan, R. Evans, D. Hogg, S. Jarnason, M. Keevers, P. Lasswell, J. O’Sullivan, U. Schubert, A. Turner, S.R. Wenham, T. Young, Solar Energy 77 (2004) 857–863. [23] P. Stradins, O. Kunz, D.L. Young, Y. Yan, K.M. Jones, Y. Xu, R.C. Reedy, H.M. Branz, A.G. Aberle, Q. Wang, Materials Research Society Symposium Proceedings 989 (2007) 391–398.