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Degradation behaviour of n-channel MOSFETs operated at 77K
World Abstracts continued from page 41
6.
Discretes
Cross-coupled charge-transfer sense amplifier and latch sense scheme for hlgh-density FET memories K. S. GRAY IBM J. Res. Devel. 24(3), 283 (1980). This paper describes a sense scheme for use on high-density one-device cell field effect transistor random access memories (FET RANIs). The high-sensitivity threshold-independent cross-coupled charge-transfer sense amplifier and latch is used. The IBM 64K-bit one-device dynamic memory cell FET RAM chip design is used as the vehicle for the discussion. Adaptations made on the sense amplifier and latch for use with the sense scheme are discussed. Also described are (1) dummy cell design, (2) subthreshold leakage considerations, (3) single-ended imput/output (I/O) circuitry sensing and ramifications, (4) multiple cycle signal degradations, and (5) a maximum supply voltage ((Vtl) buffer circuit sense scheme improvement. Power MOS FETs run directly off'I'I~L J. KRAUSSE, J. TIHANY1 and P. TILLMANNS Electronics p. 145 (1980). Double-implanted, self-aligned structure builds multi-cell FETs with on-resistance as low as 0.03[/, breakdown ratings up to 1000V. Near-ideal Si-SiOz interfaces L. A. KASPRZAK and A. K. GAIND IBM J. Res. Devel. 24(3), 348 (1980). The Si-SiO2 interface plays a key role in insulated-gate field-effect transistors (IGFETs). Of principal concern are the interface charge density Oic and the fast-state density Nfs. These properties can be optimised by eliminating the transition region and creating an abrupt interface. Our work with the chemical vapour deposition (CVD) of SiO2 using a CO2-SiH4-H-, system in the presence or absence of trace amounts of HCI gas at 1000°C has demonstrated that unannealed CVD SiO2 on (100) Si using a vertical-cold-wall reactor has properties similar to those of unannealed SiO2 on (100) Si formed by the usual thermal oxidation procedure. In addition, using only 2.27 vol% HCI, v,'elhave produced films of SiO2 on (111) Si that are better than their thermal counterparts, unannealed or annealed; i.e. Qic~5× 10t°cm -2 and 2V/.s~ 10 t°cm-2-eV- I. We attribute these results, at least in part, to an abrupt interface between the CVD SiO2 and Si. Deposition rates of 10-20nm/min were used to reproducibly deposit 30-50nm of SIO2. The CVD SiO2 films also show a significantly lower standard deviation in the breakdown fields (___1.5%) and the mobile charge densities (---5%) than their thermal counterparts. In general, Nfs was independent of Qic. Degradation behaviour of n-channel MOSFETs operated at 77K J. R. b A V I S lEE Proc. 127(4) p. 183 (1980). N-channel MOS transistors have been operated at an ambient temperature of 77K with Vos=Vas to maximise the generation of highenergy ('hot') electrons in the channel. All the major transistor parameters exhibited substantial shifts which can be ascribed to two degradation mechanisms, namely the well known trapping of electrons in the gate oxide near the drain, and the generation of lattice defects in the semiconductor. ltumidity effects on reverse bias of Ta film capacitors A. R. A D O L T a n d D. O. MELROY
IEEE 18th Annual Proceedings, Reliability Physics 1980, Las Vegas, Nevada, p.39 (1980). Reverse bias testing of Ta thin film capacitors under accelerated conditions showed higher failure rates at 45° and 65°C than at 85°C. Two distinct failure modes occurred: area dependent point failures and non-area dependent failures along the counter electrode/dielectric edge. The work reported here shows that the edge failures are moisture dependent, while the point failures are not. The product limit method of statistical analysis was used to separate the two failure modes. The edge breakdowns occur only in the presence of moisture and the rate at which they occur is a function of the humidity level present. Low voltage leakage current studies indicate that there is a threshold bias value below which there is no observable moisture effect. Reliability degradation indicators being observed on terrestrial silicon solar cells J. L. PRINCE, J. W. LATHROP and R. A. HARTMAN IEEE 18th Anmml Proceedings, Reliability Physics 1980, Las Vegas, Nevada, p.26 (1980). Results of a program to investigate the reliability characteristics of 42
unencapsulated low-cost terrestrial solar cells using accelerated stress testing are presented. A total of seven types of cells were investigated. Results of extended (~1 year) bias-temperature stress testing of four cell types were obtained. An additional three cell types, including cells fabricated using the advanced technologies of ribbon-grovcn silicon and polycrystalline silicon, were subjected to various combinations of bias, temperature cycling stress tests. The spectrum of tests used was based on previous )ears' work, but differs from that used earlier. An electrical measurement procedure capable of distinguishing small changes in cell electrical parameters was used. Significant degradation was shown by some cell types in some stress tests. Other combinations of cell types and stress tests resulted in no detectable cell degradation. Analysis of the origins of the differences in degradation is continuing. Second quadrant characteristics of some cell types vcere also investigated in order to establish the electrical behaviour of cells which may be exposed to this stress condition in modules deployed in the field. Time and voltage dependence of failure in MNOS capacitors containing point defects W. H. BECKER IEEE 18th Annual Proceedings, Reliability Physics 1980, Las Vegas, Nevada, p.44 (1980). Time-dependent dielectric breakdown is an important failure mode for silicon integrated circuits. This paper presents a study of such failures in a MNOS capacitor used on a bipolar operational amplifier IC. It is shown that the cause of these failures is point defects in the Si3N4 film. The number of defective capacitors in a given population can be estimated by a silicon 'pinhole etch" decoration technique. The failure of these defects is very dependent on voltage and each has a definite threshold for failure. This threshold varies from defect to defect. Ageing at a fixed voltage stress causes rapid failure of all those defects with thresholds below the stress. The defects with higher thresholds do not fail. Voltage step-stress data is presented to show that the defects have a definite distribution of failure thresholds. This distribution is approximately normal with a median of 40 volts. Thus most defects fail well below the 120 volt dielectric breakdown of the MNOS structure. For defects aged above their failure threshold, the time-to-failure distribution is a strong function of the overvoltage (Vov); i.e. the amount the ageing voltage exceeds the defect threshold. For Vov of a few volts, the time-to-failure distribution is log-normal with a median of about 10 hours and sigma of about 2. For higher overvoltages, the median life decreases rapidly - approximately as llV/~v. Electrical and structural properties of cadmium selenide thin film transistors M. J. LEE, S. W. WRIGHT and C. P. JUDGE Solid-St. Electron. 23, 671 (1980). Stable thin film transistors based on cadmium selenide and silicon dioxide have been prepared. The degree of stability implies a decay of only 10% in drain current in 100 years of continuous DC operation. The decay is solely due to tunnelling of electrons into insulator traps and has a logarithmic time dependence. The devices have field effect mobilities up to 140cm2. Volt -1 sec -I, switching ratios in the range 105-10 ~, and good reproducibility. The CdSe films contain the hexagonal structure and grain growth occurs during anneal. Grain size and distribution are reproducible from run to run. Strain sensitivity in thick-film resistors C. CANALI, D. MALAVASI, B. MORTEN, M. PRUDENZIATI and A. TARONI IEEE Trans. Components, Hybrids Mfng Technol. Chmt-3(3). 421 (1980). Piezo-resistive properties of Dupon 1400 series thick-film resistors have been invesitagcd by measuring longitudinal and transverse gauge factors as a function of applied strain between 0 and -+-II)00 microstrain in the temperature range from - 7 0 to + 14(FC. The relative change in resistance of thick-film resistors is linear, reproducible, and hysteresis flee for the full range of applied strain. They appear more sensitive than metal resistors and have a low temperature coefficient of resistance (TCR) and gauge factor. An approach to high speed laser trimming of thick film resistors J. R. SIMS, P. G. CRETER, J. W. SOUCY and A. HOWE Solid-St. TechnoL p. 135 (1980). A study of the effects of varying laser trimming speed indicates faster speeds can be used and still result in stable resistors conforming to military specifications. A set-up procedure is detailed and a short term measurement parameter is correlated with long term stability characteristics.
6.
Discretes
Cross-coupled charge-transfer sense amplifier and latch sense scheme for hlgh-density FET memories K. S. GRAY IBM J. Res. Devel. 24(3), 283 (1980). This paper describes a sense scheme for use on high-density one-device cell field effect transistor random access memories (FET RANIs). The high-sensitivity threshold-independent cross-coupled charge-transfer sense amplifier and latch is used. The IBM 64K-bit one-device dynamic memory cell FET RAM chip design is used as the vehicle for the discussion. Adaptations made on the sense amplifier and latch for use with the sense scheme are discussed. Also described are (1) dummy cell design, (2) subthreshold leakage considerations, (3) single-ended imput/output (I/O) circuitry sensing and ramifications, (4) multiple cycle signal degradations, and (5) a maximum supply voltage ((Vtl) buffer circuit sense scheme improvement. Power MOS FETs run directly off'I'I~L J. KRAUSSE, J. TIHANY1 and P. TILLMANNS Electronics p. 145 (1980). Double-implanted, self-aligned structure builds multi-cell FETs with on-resistance as low as 0.03[/, breakdown ratings up to 1000V. Near-ideal Si-SiOz interfaces L. A. KASPRZAK and A. K. GAIND IBM J. Res. Devel. 24(3), 348 (1980). The Si-SiO2 interface plays a key role in insulated-gate field-effect transistors (IGFETs). Of principal concern are the interface charge density Oic and the fast-state density Nfs. These properties can be optimised by eliminating the transition region and creating an abrupt interface. Our work with the chemical vapour deposition (CVD) of SiO2 using a CO2-SiH4-H-, system in the presence or absence of trace amounts of HCI gas at 1000°C has demonstrated that unannealed CVD SiO2 on (100) Si using a vertical-cold-wall reactor has properties similar to those of unannealed SiO2 on (100) Si formed by the usual thermal oxidation procedure. In addition, using only 2.27 vol% HCI, v,'elhave produced films of SiO2 on (111) Si that are better than their thermal counterparts, unannealed or annealed; i.e. Qic~5× 10t°cm -2 and 2V/.s~ 10 t°cm-2-eV- I. We attribute these results, at least in part, to an abrupt interface between the CVD SiO2 and Si. Deposition rates of 10-20nm/min were used to reproducibly deposit 30-50nm of SIO2. The CVD SiO2 films also show a significantly lower standard deviation in the breakdown fields (___1.5%) and the mobile charge densities (---5%) than their thermal counterparts. In general, Nfs was independent of Qic. Degradation behaviour of n-channel MOSFETs operated at 77K J. R. b A V I S lEE Proc. 127(4) p. 183 (1980). N-channel MOS transistors have been operated at an ambient temperature of 77K with Vos=Vas to maximise the generation of highenergy ('hot') electrons in the channel. All the major transistor parameters exhibited substantial shifts which can be ascribed to two degradation mechanisms, namely the well known trapping of electrons in the gate oxide near the drain, and the generation of lattice defects in the semiconductor. ltumidity effects on reverse bias of Ta film capacitors A. R. A D O L T a n d D. O. MELROY
IEEE 18th Annual Proceedings, Reliability Physics 1980, Las Vegas, Nevada, p.39 (1980). Reverse bias testing of Ta thin film capacitors under accelerated conditions showed higher failure rates at 45° and 65°C than at 85°C. Two distinct failure modes occurred: area dependent point failures and non-area dependent failures along the counter electrode/dielectric edge. The work reported here shows that the edge failures are moisture dependent, while the point failures are not. The product limit method of statistical analysis was used to separate the two failure modes. The edge breakdowns occur only in the presence of moisture and the rate at which they occur is a function of the humidity level present. Low voltage leakage current studies indicate that there is a threshold bias value below which there is no observable moisture effect. Reliability degradation indicators being observed on terrestrial silicon solar cells J. L. PRINCE, J. W. LATHROP and R. A. HARTMAN IEEE 18th Anmml Proceedings, Reliability Physics 1980, Las Vegas, Nevada, p.26 (1980). Results of a program to investigate the reliability characteristics of 42
unencapsulated low-cost terrestrial solar cells using accelerated stress testing are presented. A total of seven types of cells were investigated. Results of extended (~1 year) bias-temperature stress testing of four cell types were obtained. An additional three cell types, including cells fabricated using the advanced technologies of ribbon-grovcn silicon and polycrystalline silicon, were subjected to various combinations of bias, temperature cycling stress tests. The spectrum of tests used was based on previous )ears' work, but differs from that used earlier. An electrical measurement procedure capable of distinguishing small changes in cell electrical parameters was used. Significant degradation was shown by some cell types in some stress tests. Other combinations of cell types and stress tests resulted in no detectable cell degradation. Analysis of the origins of the differences in degradation is continuing. Second quadrant characteristics of some cell types vcere also investigated in order to establish the electrical behaviour of cells which may be exposed to this stress condition in modules deployed in the field. Time and voltage dependence of failure in MNOS capacitors containing point defects W. H. BECKER IEEE 18th Annual Proceedings, Reliability Physics 1980, Las Vegas, Nevada, p.44 (1980). Time-dependent dielectric breakdown is an important failure mode for silicon integrated circuits. This paper presents a study of such failures in a MNOS capacitor used on a bipolar operational amplifier IC. It is shown that the cause of these failures is point defects in the Si3N4 film. The number of defective capacitors in a given population can be estimated by a silicon 'pinhole etch" decoration technique. The failure of these defects is very dependent on voltage and each has a definite threshold for failure. This threshold varies from defect to defect. Ageing at a fixed voltage stress causes rapid failure of all those defects with thresholds below the stress. The defects with higher thresholds do not fail. Voltage step-stress data is presented to show that the defects have a definite distribution of failure thresholds. This distribution is approximately normal with a median of 40 volts. Thus most defects fail well below the 120 volt dielectric breakdown of the MNOS structure. For defects aged above their failure threshold, the time-to-failure distribution is a strong function of the overvoltage (Vov); i.e. the amount the ageing voltage exceeds the defect threshold. For Vov of a few volts, the time-to-failure distribution is log-normal with a median of about 10 hours and sigma of about 2. For higher overvoltages, the median life decreases rapidly - approximately as llV/~v. Electrical and structural properties of cadmium selenide thin film transistors M. J. LEE, S. W. WRIGHT and C. P. JUDGE Solid-St. Electron. 23, 671 (1980). Stable thin film transistors based on cadmium selenide and silicon dioxide have been prepared. The degree of stability implies a decay of only 10% in drain current in 100 years of continuous DC operation. The decay is solely due to tunnelling of electrons into insulator traps and has a logarithmic time dependence. The devices have field effect mobilities up to 140cm2. Volt -1 sec -I, switching ratios in the range 105-10 ~, and good reproducibility. The CdSe films contain the hexagonal structure and grain growth occurs during anneal. Grain size and distribution are reproducible from run to run. Strain sensitivity in thick-film resistors C. CANALI, D. MALAVASI, B. MORTEN, M. PRUDENZIATI and A. TARONI IEEE Trans. Components, Hybrids Mfng Technol. Chmt-3(3). 421 (1980). Piezo-resistive properties of Dupon 1400 series thick-film resistors have been invesitagcd by measuring longitudinal and transverse gauge factors as a function of applied strain between 0 and -+-II)00 microstrain in the temperature range from - 7 0 to + 14(FC. The relative change in resistance of thick-film resistors is linear, reproducible, and hysteresis flee for the full range of applied strain. They appear more sensitive than metal resistors and have a low temperature coefficient of resistance (TCR) and gauge factor. An approach to high speed laser trimming of thick film resistors J. R. SIMS, P. G. CRETER, J. W. SOUCY and A. HOWE Solid-St. TechnoL p. 135 (1980). A study of the effects of varying laser trimming speed indicates faster speeds can be used and still result in stable resistors conforming to military specifications. A set-up procedure is detailed and a short term measurement parameter is correlated with long term stability characteristics.