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Demonstration of an optoelectronic 4-bit analog-to-digital converter using a thyristor smart comparator
1 October 2000
Optics Communications 184 (2000) 79±88
www.elsevier.com/locate/optcom
Demonstration of an optoelectronic 4-bit analog-to-digital converter using a thyristor smart comparator J. Cai, G.W. Taylor * Department of Electrical Engineering, University of Connecticut, 260 Glenbrook Road, Storrs, CT, USA Received 4 October 1999; received in revised form 19 July 2000; accepted 25 July 2000
Abstract An optoelectronic analog-to-digital converter (ADC) approach with 4-bit operation is demonstrated based on the combination of HFETs and an optoelectronic thyristor. The optoelectronic thyristor implements the comparator function and generates both optical digital and electrical output. The basic comparator function is combined with HFET dierential ampli®ers to form a smart comparator (SC) which becomes a building block that may be cascaded N times to form an N-bit ADC. In this paper, one SC is used in a feedback loop with the appropriate clocking to achieve 4-bit operation. When the optoelectronic thyristor and the HFET ampli®ers are fabricated as a monolithic integrated circuit, multi-GB/s operation is expected. Ó 2000 Elsevier Science B.V. All rights reserved. Keywords: Analog-to-digital conversion; Optoelectronic devices; Semiconductor lasers; Optical logic devices; Semiconductor switches
1. Introduction The development of high-sampling-rate, highresolution analog-to-digital converters (ADCs) is driven by the increasing number of high-speed digital signal processing applications. State-of-theart commercial ADCs are based totally on electronic design because of the performance available from advanced semiconductor integrated circuit (IC) technology. Recently, optical/optoelectronic ADCs have attracted more and more attention since the optical outputs are desirable for transmission and optical timing circuits may reduce the
*
Corresponding author. E-mail address: [email protected] (G.W. Taylor).
jitter in electrical clocking and sampling. Speci®cally, optical signals will not be aected by electronic noise and radiation, and the optical output is resistant to electromagnetic interference. By using optical ®ber, digital outputs can be sent to a microprocessor so that advanced data processing is not necessary within the ADC chip. A variety of optical/optoelectronic ADC approaches have been demonstrated. Taylor [1] proposed to use the connection between the electro-optical transfer function of the MZ interferometer and the graycode digital data to realize A/D conversion, and demonstrations have been reported [2±4]. Photonic ADC has also been demonstrated [5] based on an optical ®ber temporal-spectral mapping eect. In this technique, the analog signal is coded by optical wavelength. A wavelength-division demultiplexer is used to separate a wavelength-coded
0030-4018/00/$ - see front matter Ó 2000 Elsevier Science B.V. All rights reserved. PII: S 0 0 3 0 - 4 0 1 8 ( 0 0 ) 0 0 9 1 1 - 1
80
J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
signal into parallel channels. These parallel channels are demodulated by slow photodetectors and quantized to form an interleaved digital data output. Others have utilized symmetric self-electro-optic eect devices (S-SEEDs) to implement optical ADC [6]. In general, these approaches are limited by their bulk structure and low dynamic range since the comparator function is realized in the optical domain and cannot bene®t from advanced electronic techniques, such as low-noise, high-speed dierential ampli®ers (DAs) which are readily available in advanced ICs. The problem of A/D conversion may be viewed as the combination of three critical functions which are (1) a high-speed, low-jitter clock, (2) a high-speed and low-feedthrough sampling technique and (3) a high-speed, low-power and smallsize quantizer. Much of the photonic research focus today is on problem 1 where a mode-locked laser is proposed for low jitter. As a device integrated with the quantizer and the sampler, the mode-locked source may be an ideal clock. For problem 2, the problem of feedthrough spikes in high-speed electronic samplers may be solved by using an optical switch to control an electronic signal path since optical isolation eliminates feedthrough. Problem 3 is addressed here through the use of the smart comparator (SC) which dramatically reduces the large number of devices needed for high resolution without compromising speed and also provides optical outputs. However, the thyristor as an integrated device also addresses problems 2 and 3 since it provides the unique opportunity for a mode-locked optical source and an optoelectronic sampler to eliminate feedthrough. These issues will be addressed in future publications. In this paper, we demonstrate a 4-bit ADC operation using the unique properties of an optoelectronic thyristor to implement a SC. The optoelectronic thyristor is a laser in the ``on'' state and provides the digital output of the photonic ADC. However, the comparison and subtraction are realized using advanced electronic techniques in the electrical domain so that the photonic ADC combines logic with optical output. The remainder of the paper deals with the quantizer implementation.
2. Photonic analog-to-digital converter principle The critical part of the photonic ADC structure is the photonic comparator. The photonic comparator is based on the optoelectronic thyristor which has been fabricated and modeled [7±9]. The optoelectronic thyristor is a bistable, threeterminal device, which is typically con®gured with a load resistor in an inverter or follower con®guration as shown in Fig. 1a. The schematic current±voltage (I±V ) relationship and the laser± current (L±I) characteristic are shown in Fig. 1. For biasing the thyristor as an optical source, a load transistor is incorporated as shown in Fig. 1a and is set so that switching occurs to a current in the ``on'' state which produces laser emission. The third terminal (source) provides the thyristor with sensitive control over the switching parameters, Vsw and Isw , and is used to initiate switching of the thyristor. The comparator function utilizes the three-terminal operation of the thyristor. The reference voltage of the comparator is Vref Vbias ÿ Vh , where Vbias is the thyristor bias voltage and Vh is the holding voltage, the input to the thyristor is the source voltage Vin , and the output of the comparator labeled Vout is the subcollector voltage de®ned in Fig. 1a as Vsc . This thyristor has a ptype emitter so as to enable positive supply voltages; the emitter is biased to the supply. The thyristor three-terminal operation is shown in Table 1. However the situation of, Vin < Vbias ÿ Des for Vout \1" and Vin > Vbias ÿ Des for Vout \0" does not meet the requirements of the ADC comparator and must be reversed so that digital outputs change from ``0'' to ``1'' as analog signals become larger than threshold, and this is accomplished with a DA to complement the input. The optoelectronic thyristor-based photonic comparator (designated as SC because of the logic performed within the unit) is shown in Fig. 2a. Also shown in Fig. 2a is an N-bit ADC formed by cascading N SCs. A DA is used between the input signal and the source node of the thyristor to reverse the input polarities so that increasing input voltage can be used to threshold the comparator. For any given comparator, the negative input of the DA is the input signal Vin and the positive input of the DA is
J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
81
Fig. 1. (a) Optical thyristor node terminology and (b) I±V and L±I characteristics. Table 1 Voltage levels and switched state of the three terminal thyristor Vin
Switch status
Vout
Vbias ÿ Des
On O
Vbias ÿ Vh \1" ``0''
Vcompl Vbias Vref ÿ Des
1
so that, at the comparison point for the ®rst stage, Vs Vref and Vout Vref since switching occurs. Then, for subsequent stages, we can write Vo Vin DAiÿ1 2 Vbias Vref ÿ Des ÿ Vin DAi :
2
The photonic comparator operation is shown in Table 2.
It is clear that the basic unit of the comparator structure can be easily extended to form the ADC. As shown, at the thyristor output, a second DA subtracts Vout from the input signal Vs to form the output of the repeating unit Vo Vs ÿ Vout , which is Vo Vs for no switching or Vo Vs ÿ Vref for switching. Then, Vo becomes the input to the next stage. By using a gain of 2, Vout of the thyristor is identical between stages although it represents a dierent weight corresponding to the particular bit. Thus, the architecture and the circuit design of each bit are identical. The SC in Fig. 2 includes the basic comparator unit consisting of the thyristor and its load. This basic comparator should be compared to the conventional electronic one which is comprised of about 18 devices. It is clear that, if the function in
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J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
Fig. 2. (a) Photonic SC for cascading to form N-bit ADC and (b) photonic SC structure with feedback to form a time sequential ADC with a single SC.
Table 2 Voltage levels and optical outputs of the photonic comparator Vs
Vin (DA)
Vout
Laser output
>Vref
Vbias ÿ Des
``1'' ``0''
On O
Fig. 2 were implemented with a standard comparator, the DAs would still be required, but the circuit to determine whether the comparator had thresholded would require more devices. Fig. 2a shows how the comparators are cascaded to obtain a multi-bit ADC. It is also possible as shown in Fig. 2b to use a single comparator in a time sequential operation to obtain a multi-bit ADC, and we use this approach here. This would form the basis of a smart pixel approach to ADC for 2D array applications.
3. Experimental results and discussion The photonic ADC is realized with integrated optothyristor laser/HFET combinations based on inversion channel technology [10]. A unique feature of the inversion channel structure is that the operation of the thyristor and the HFET may be obtained with the same device structure. These results are shown in Fig. 3 where the HFET is a depletion device with a threshold of ÿ2 V. The electrical parameters of the thyristor are typically Vsw 6 V, Vh 1:9 V, Isw 0:2 mA and Ih 2:5 mA. The optoelectronic thyristor shown in Fig. 3 has been designed as an edge-emitting device. After cleaving and mounting on a copper stud, the laser has dimensions of 10 600 lm2 . The thyristor current±voltage (I±V ) characteristics, the optical power±current (L±I) characteristics
J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
83
Fig. 3. (a) Fabricated FET integrated with a thyristor/laser combination, (b) output characteristics of inversion channel device as a FET and (c) output characteristics of inversion channel device as a thyristor.
and the spectral response are measured and shown in Fig. 4. The switching voltage Vsw is 6.25 V, and the holding current Ih is 5 mA. The laser threshold current Ith is about 50 mA. The laser output spectrum is measured and shown in Fig. 4b corresponding to the designed wavelength of 0.98 lm. SC operation has been demonstrated using this optoelectronic thyristor in both static and timedependent conditions. In the static condition, in order to achieve a viable laser operating point, we choose an injection current of 55 mA, and from Fig. 4a, at this point, the thyristor holding voltage is about 2.6 V. In the experiment, the bias voltage Vbias 5 V, and so the load resistor R 2:4=0:055 43:6 X. Since the electrical output voltage Vout needs to be 2 V in the experiment for the subtraction according to the SC algorithm, the load comprised two serial resistors R1 , R2 ,
and the relation between R1 and R2 is R2 = R1 R2 2=2:4, giving R1 7:3 X, R2 36:3 X. When the input voltage Vin changes from 5 to 0 V, the electrical output Vout and optical output Pout are measured and shown in Fig. 5. In the static experiment, the input voltage Vin is directly added to the source node of the thyristor. When Vin 3:6 V, i.e. Des 1:4 V, the thyristor switches and changes state from high impedance to low impedance, causing Vout to change from low (0 V) to high (2 V) which matches with the calculation, and at the same time, the optical output Pout also changes from low to high. From the measurement, the low optical output is 11.3 lW which is the dark current of the detector and the high optical output is about 600 lW which is consistent with the thyristor L±I curve shown in Fig. 4a. The only non-ideal aspect of the comparator is the small
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J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
Fig. 4. (a) Thyristor I±V curve and L±I curve measurements and (b) thyristor optical spectrum.
excursion of input voltage above the switching point to achieve a zero output value. This is attributed to the non-zero current in the o state which may be substantially reduced. Time-dependent sampling measurements were made to demonstrate the comparator function using the above thyristors. The thyristors are accessed by probe on wafer to combine them with the o-the-shelf dierential ampli®ers. The experimental results are shown in Fig. 6. The experi-
mental data show that the comparator operation is achieved. When the input signal is larger than 2 V, the output is ``1'', and when the input signal is less than 2 V, the output is ``0''. 4. Photonic 4-bit analog-to-digital converter demonstration The photonic ADC architecture is shown in Fig. 7 and consists of two samples and holds, two
J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
85
Fig. 5. Photonic comparator electrical and optical characteristics.
Fig. 6. Time-dependent experimental result of comparator operation.
analog switches and one photonic comparator. The ADC produces the digital version of the input signal as a time sequence of N output pulses in N clock cycles. The general expression for ith-bit Vout is equal to Vout i Vout iÿ1 ÿ bi V1 zÿ1 ;
3
where bi is the comparator output for the ith evaluation which is equal to ``1'' if the ith bit is set and is equal to ``0'' otherwise, and zÿ1 implies a delay of one clock period. This architecture resembles the N-bit algorithmic architecture used in the electrical ADC.
Fig. 7. Algorithmic ADC block diagram and control signal time sequence.
However, several signi®cant improvements are achieved. First, the digital output is achieved optically from the comparator automatically and can be transmitted to remote processor via an optical ®ber. This is a signi®cant advantage for 2D array applications using 2D ®ber arrays. Second, since photonic comparator has both optical and electrical output, the structure not only brings the bene®ts of optical property to the problem of A/D conversion, but also utilizes advanced electrical techniques. Third, in the electrical ADC, the subtraction of Vref at each bit from the input voltage is
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J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
associated with the comparatorÕs output, but this subtraction is not directly controlled by the comparator. A logic circuit is necessary to decide whether Vref should be subtracted from the input according to the comparatorÕs output. In the thyristor architecture, the optical output expresses the ith-bit digital output, and the quasi-digital electrical output at the subcollector node Vsc Vref is the value that needs to be subtracted from the input. This output is digital in the sense that it is the same for each stage but analog because it is subtracted from an analog voltage. So, in fact, the thyristor-based comparator includes the logic circuit function required in the electrical architecture. Because of this multi-functional nature of the thyristor, we call this con®guration as SC. Using this photonic comparator, the algorithmic ADC is demonstrated. In the algorithmic architecture, two analog switches and two sample/hold (S/H) circuits are needed to separate the input signal and output signal since the ith-bit output will be the next bit input. Therefore, four control signals should be used to control the four devices, i.e. two analog switches and two S/H ampli®ers, respectively, and these four control signals should operate with a particular time sequence which is shown in the Fig. 7. In the experiment, the control circuit is constructed with discrete digital devices. In or-
der to realize a 4-bit ADC here, 16 clock cycles are needed. First, the clocks are counted by a 4-bit binary counter, and then using four to 16 decoders, 16 output signals are generated corresponding to the clock cycles. On combining the particular output signals and using logic gate devices, the required control signals are realized. The discrete devices used here which include analog switches, S/H ampli®ers, and logic gates are o-the-shelf items fabricated in CMOS and BICMOS. It should be mentioned that the circuit we used here to generate the control signals is not the optimum one but is the most expeditious in our experiment. When the IC is used to fabricate the algorithmic converter, it becomes ideal for the 2D planar array since the compact smart converter cell structure allows a high density of parallel optical inputs as the front end of a digital optical signal processor. Multi-bit photonic A/D conversion is realized using the architecture shown in Fig. 7 with discrete devices. The discrete devices used here include analog switches, S/H ampli®ers and logic timing circuits which are o-the-shelf items fabricated in CMOS. Since in inversion channel technology thyristor and HFET control circuits have been implemented in the same chip, an integrated photonic ADC is feasible. The 4-bit photonic A/D
Fig. 8. 4-bit photonic ADC result.
J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
conversion result is shown in Fig. 8. The low waveform is the input analog signal which is a ramped voltage from a pulse generator (a pulse with a long rise time and a short fall time). The middle one is the clock signal which activates the S/H of the input analog signal. ``Sample'' starts at the fall time and ``hold'' starts at the rise time, so the input analog signal is held and sent to the thyristor for A/D conversion at the point when clock signal moves from low to high. The top waveform is the output from the optoelectronic thyristor. The four bits from the ADC are identi®ed in the ®gure and labeled as a 1,0 pattern. The correct AD operation is easily veri®ed by comparing the bit pattern to the analog voltage which is at the beginning of each conversion cycle and is listed at the side of this ®gure. 5. Potential speed of operation The highest speed of operation is obtained from the pipelined con®guration of SCs which is the one in which each SC is separated from the next by a S/ H circuit. Since the output of the comparator is optical there are no shift registers to store the state. Instead, the optical bit is transmitted (e.g. on an optical ®ber) and the D/A detection circuit at the receiving end is designed to reproduce the analog signal by starting with the MSB and ®nishing with the LSB (in time). This con®guration has the advantage that, after the time has elapsed for the analog signal to be delivered initially to each SC in the chain, for each clock cycle, a full digital output for the next incremental analog input is obtained. Therefore, in this mode, the sample rate for the A/D conversion is the inverse of the SC switching time since a full digital word is produced at each cycle. One of the advantages of the pipelined con®guration is that a S/H pulse is applied to a S/H circuit between each SC stage. It is convenient to use this pulse to reset the thyristor simultaneously which is possible since each thyristor is isolated from the S/H by a DA stage. Therefore, the SC response time is the turn-on time of the thyristor added to the propagation delay of two DA stages. Of course, the sample time or response time of the
87
S/H circuit can be no faster than the switch-o time of the thyristor. Therefore, the conversion time which is the processing time between samples is given by tconv son 2sDA ; where son is the turn-on time of the thyristor, sDA is the propagation delay of the dierential ampli®er and it is assumed that the thyristor has been turned o during the sample time tsample . The sample time must be at least soff to ensure complete recovery of the thyristor and for this we should add a safety margin of Dt to avoid noiseinduced errors, and therefore, tsample soff Dt: The overall conversion of the ADC is then ÿ tADC tsample tconv son soff 2sDA Dt; and the ADC sampling rate is 1=tADC . Ideally, we would like to have tsample tconv which implies that soff son sDA ÿ Dt: This requirement ®ts naturally with the switching parameters of the thyristor since switch-on is usually signi®cantly faster than switch-o. This kind of analysis shows how critically dependent the speed is upon the switching parameters of the thyristor. The son is scalable to very low values, of the order of the transit time across the internal junction which is in the 2 ps range. The sDA is also in the 5±10 ps range for a scaled FET structure. Therefore, the dominant speed limitation is the turn-o time of the thyristor and this is determined by the charge-up time of the internal device capacitance through the load element plus the transit time through the device. Consider a thyristor with an internal region of 0.5 lm, and a 5 lm diameter. Then, the capacitance is 4 fF. Assuming an operating current of 2 mA and a bias point of Vh 0:5 V, the resistance of the load is 200 X. Thus, the rise time of 2.2RC is 1.8 ps and then soff sTR 2:2RC 2:5 1:8 ps. Assuming Dt 4 ps, the sampling rate is 2tsample or approximately 100 GS/s
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J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
(note that we require sDA 3 ps to reach the condition of tsample tconv above). Additional scaling is possible with more aggressive designs.
Acknowledgements This work was supported by AFRL Rome Laboratory, under contract F30602-98-C-0217.
6. Conclusion In conclusion, a new photonic comparator for optical ADC has been described based on a highspeed three-terminal electro-optic thyristor as an electronic comparator with an optical output. The comparator comprises only two components and thus oers a major reduction in component count. Furthermore, since the comparator itself makes the decision for subtraction, the logic circuit in the ADC is not necessary, and this makes very highspeed operation possible. The digital output of the ADC is obtained automatically as the laser emission of the comparators in which a thyristor in the on-state with emission is a ``1'' and a thyristor in the o-state with no emission is a ``0''.
References [1] H.F. Taylor, Proc. IEEE 63 (1975) 1524. [2] Y. Hayasaki, M. Mori, N. Nishida, Appl. Opt. 37 (1998) 3607. [3] B. Jalali, Y.M. Xie, Opt. Lett. 20 (1995) 1901. [4] P.E. Pacer, D. Styer, Opt. Engng. 33 (1994) 2638. [5] M.Y. Frankel, J.U. Kang, R.D. Esman, Electron. Lett. 33 (1997) 2096. [6] L.M. Loh, J.L. LoCicero, Opt. Engng. 35 (1996) 457. [7] G.W. Taylor, R.S. Mand, J.G. Simmons, A.Y. Cho, Appl. Phys. Lett. 50 (1987) 338. [8] G.W. Taylor, P. Cooke, IEEE Trans. Electron. Dev 39 (1992) 2529. [9] J. Cai, G.W. Taylor, IEEE Photon. Technol. Lett. 10 (1999) 1295. [10] G.W. Taylor, IEEE J. Quant. Electron. 29 (1993) 785.
Optics Communications 184 (2000) 79±88
www.elsevier.com/locate/optcom
Demonstration of an optoelectronic 4-bit analog-to-digital converter using a thyristor smart comparator J. Cai, G.W. Taylor * Department of Electrical Engineering, University of Connecticut, 260 Glenbrook Road, Storrs, CT, USA Received 4 October 1999; received in revised form 19 July 2000; accepted 25 July 2000
Abstract An optoelectronic analog-to-digital converter (ADC) approach with 4-bit operation is demonstrated based on the combination of HFETs and an optoelectronic thyristor. The optoelectronic thyristor implements the comparator function and generates both optical digital and electrical output. The basic comparator function is combined with HFET dierential ampli®ers to form a smart comparator (SC) which becomes a building block that may be cascaded N times to form an N-bit ADC. In this paper, one SC is used in a feedback loop with the appropriate clocking to achieve 4-bit operation. When the optoelectronic thyristor and the HFET ampli®ers are fabricated as a monolithic integrated circuit, multi-GB/s operation is expected. Ó 2000 Elsevier Science B.V. All rights reserved. Keywords: Analog-to-digital conversion; Optoelectronic devices; Semiconductor lasers; Optical logic devices; Semiconductor switches
1. Introduction The development of high-sampling-rate, highresolution analog-to-digital converters (ADCs) is driven by the increasing number of high-speed digital signal processing applications. State-of-theart commercial ADCs are based totally on electronic design because of the performance available from advanced semiconductor integrated circuit (IC) technology. Recently, optical/optoelectronic ADCs have attracted more and more attention since the optical outputs are desirable for transmission and optical timing circuits may reduce the
*
Corresponding author. E-mail address: [email protected] (G.W. Taylor).
jitter in electrical clocking and sampling. Speci®cally, optical signals will not be aected by electronic noise and radiation, and the optical output is resistant to electromagnetic interference. By using optical ®ber, digital outputs can be sent to a microprocessor so that advanced data processing is not necessary within the ADC chip. A variety of optical/optoelectronic ADC approaches have been demonstrated. Taylor [1] proposed to use the connection between the electro-optical transfer function of the MZ interferometer and the graycode digital data to realize A/D conversion, and demonstrations have been reported [2±4]. Photonic ADC has also been demonstrated [5] based on an optical ®ber temporal-spectral mapping eect. In this technique, the analog signal is coded by optical wavelength. A wavelength-division demultiplexer is used to separate a wavelength-coded
0030-4018/00/$ - see front matter Ó 2000 Elsevier Science B.V. All rights reserved. PII: S 0 0 3 0 - 4 0 1 8 ( 0 0 ) 0 0 9 1 1 - 1
80
J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
signal into parallel channels. These parallel channels are demodulated by slow photodetectors and quantized to form an interleaved digital data output. Others have utilized symmetric self-electro-optic eect devices (S-SEEDs) to implement optical ADC [6]. In general, these approaches are limited by their bulk structure and low dynamic range since the comparator function is realized in the optical domain and cannot bene®t from advanced electronic techniques, such as low-noise, high-speed dierential ampli®ers (DAs) which are readily available in advanced ICs. The problem of A/D conversion may be viewed as the combination of three critical functions which are (1) a high-speed, low-jitter clock, (2) a high-speed and low-feedthrough sampling technique and (3) a high-speed, low-power and smallsize quantizer. Much of the photonic research focus today is on problem 1 where a mode-locked laser is proposed for low jitter. As a device integrated with the quantizer and the sampler, the mode-locked source may be an ideal clock. For problem 2, the problem of feedthrough spikes in high-speed electronic samplers may be solved by using an optical switch to control an electronic signal path since optical isolation eliminates feedthrough. Problem 3 is addressed here through the use of the smart comparator (SC) which dramatically reduces the large number of devices needed for high resolution without compromising speed and also provides optical outputs. However, the thyristor as an integrated device also addresses problems 2 and 3 since it provides the unique opportunity for a mode-locked optical source and an optoelectronic sampler to eliminate feedthrough. These issues will be addressed in future publications. In this paper, we demonstrate a 4-bit ADC operation using the unique properties of an optoelectronic thyristor to implement a SC. The optoelectronic thyristor is a laser in the ``on'' state and provides the digital output of the photonic ADC. However, the comparison and subtraction are realized using advanced electronic techniques in the electrical domain so that the photonic ADC combines logic with optical output. The remainder of the paper deals with the quantizer implementation.
2. Photonic analog-to-digital converter principle The critical part of the photonic ADC structure is the photonic comparator. The photonic comparator is based on the optoelectronic thyristor which has been fabricated and modeled [7±9]. The optoelectronic thyristor is a bistable, threeterminal device, which is typically con®gured with a load resistor in an inverter or follower con®guration as shown in Fig. 1a. The schematic current±voltage (I±V ) relationship and the laser± current (L±I) characteristic are shown in Fig. 1. For biasing the thyristor as an optical source, a load transistor is incorporated as shown in Fig. 1a and is set so that switching occurs to a current in the ``on'' state which produces laser emission. The third terminal (source) provides the thyristor with sensitive control over the switching parameters, Vsw and Isw , and is used to initiate switching of the thyristor. The comparator function utilizes the three-terminal operation of the thyristor. The reference voltage of the comparator is Vref Vbias ÿ Vh , where Vbias is the thyristor bias voltage and Vh is the holding voltage, the input to the thyristor is the source voltage Vin , and the output of the comparator labeled Vout is the subcollector voltage de®ned in Fig. 1a as Vsc . This thyristor has a ptype emitter so as to enable positive supply voltages; the emitter is biased to the supply. The thyristor three-terminal operation is shown in Table 1. However the situation of, Vin < Vbias ÿ Des for Vout \1" and Vin > Vbias ÿ Des for Vout \0" does not meet the requirements of the ADC comparator and must be reversed so that digital outputs change from ``0'' to ``1'' as analog signals become larger than threshold, and this is accomplished with a DA to complement the input. The optoelectronic thyristor-based photonic comparator (designated as SC because of the logic performed within the unit) is shown in Fig. 2a. Also shown in Fig. 2a is an N-bit ADC formed by cascading N SCs. A DA is used between the input signal and the source node of the thyristor to reverse the input polarities so that increasing input voltage can be used to threshold the comparator. For any given comparator, the negative input of the DA is the input signal Vin and the positive input of the DA is
J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
81
Fig. 1. (a) Optical thyristor node terminology and (b) I±V and L±I characteristics. Table 1 Voltage levels and switched state of the three terminal thyristor Vin
Switch status
Vout
On O
Vbias ÿ Vh \1" ``0''
Vcompl Vbias Vref ÿ Des
1
so that, at the comparison point for the ®rst stage, Vs Vref and Vout Vref since switching occurs. Then, for subsequent stages, we can write Vo Vin DAiÿ1 2 Vbias Vref ÿ Des ÿ Vin DAi :
2
The photonic comparator operation is shown in Table 2.
It is clear that the basic unit of the comparator structure can be easily extended to form the ADC. As shown, at the thyristor output, a second DA subtracts Vout from the input signal Vs to form the output of the repeating unit Vo Vs ÿ Vout , which is Vo Vs for no switching or Vo Vs ÿ Vref for switching. Then, Vo becomes the input to the next stage. By using a gain of 2, Vout of the thyristor is identical between stages although it represents a dierent weight corresponding to the particular bit. Thus, the architecture and the circuit design of each bit are identical. The SC in Fig. 2 includes the basic comparator unit consisting of the thyristor and its load. This basic comparator should be compared to the conventional electronic one which is comprised of about 18 devices. It is clear that, if the function in
82
J. Cai, G.W. Taylor / Optics Communications 184 (2000) 79±88
Fig. 2. (a) Photonic SC for cascading to form N-bit ADC and (b) photonic SC structure with feedback to form a time sequential ADC with a single SC.
Table 2 Voltage levels and optical outputs of the photonic comparator Vs
Vin (DA)
Vout
Laser output
>Vref
``1'' ``0''
On O
Fig. 2 were implemented with a standard comparator, the DAs would still be required, but the circuit to determine whether the comparator had thresholded would require more devices. Fig. 2a shows how the comparators are cascaded to obtain a multi-bit ADC. It is also possible as shown in Fig. 2b to use a single comparator in a time sequential operation to obtain a multi-bit ADC, and we use this approach here. This would form the basis of a smart pixel approach to ADC for 2D array applications.
3. Experimental results and discussion The photonic ADC is realized with integrated optothyristor laser/HFET combinations based on inversion channel technology [10]. A unique feature of the inversion channel structure is that the operation of the thyristor and the HFET may be obtained with the same device structure. These results are shown in Fig. 3 where the HFET is a depletion device with a threshold of ÿ2 V. The electrical parameters of the thyristor are typically Vsw 6 V, Vh 1:9 V, Isw 0:2 mA and Ih 2:5 mA. The optoelectronic thyristor shown in Fig. 3 has been designed as an edge-emitting device. After cleaving and mounting on a copper stud, the laser has dimensions of 10 600 lm2 . The thyristor current±voltage (I±V ) characteristics, the optical power±current (L±I) characteristics
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Fig. 3. (a) Fabricated FET integrated with a thyristor/laser combination, (b) output characteristics of inversion channel device as a FET and (c) output characteristics of inversion channel device as a thyristor.
and the spectral response are measured and shown in Fig. 4. The switching voltage Vsw is 6.25 V, and the holding current Ih is 5 mA. The laser threshold current Ith is about 50 mA. The laser output spectrum is measured and shown in Fig. 4b corresponding to the designed wavelength of 0.98 lm. SC operation has been demonstrated using this optoelectronic thyristor in both static and timedependent conditions. In the static condition, in order to achieve a viable laser operating point, we choose an injection current of 55 mA, and from Fig. 4a, at this point, the thyristor holding voltage is about 2.6 V. In the experiment, the bias voltage Vbias 5 V, and so the load resistor R 2:4=0:055 43:6 X. Since the electrical output voltage Vout needs to be 2 V in the experiment for the subtraction according to the SC algorithm, the load comprised two serial resistors R1 , R2 ,
and the relation between R1 and R2 is R2 = R1 R2 2=2:4, giving R1 7:3 X, R2 36:3 X. When the input voltage Vin changes from 5 to 0 V, the electrical output Vout and optical output Pout are measured and shown in Fig. 5. In the static experiment, the input voltage Vin is directly added to the source node of the thyristor. When Vin 3:6 V, i.e. Des 1:4 V, the thyristor switches and changes state from high impedance to low impedance, causing Vout to change from low (0 V) to high (2 V) which matches with the calculation, and at the same time, the optical output Pout also changes from low to high. From the measurement, the low optical output is 11.3 lW which is the dark current of the detector and the high optical output is about 600 lW which is consistent with the thyristor L±I curve shown in Fig. 4a. The only non-ideal aspect of the comparator is the small
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Fig. 4. (a) Thyristor I±V curve and L±I curve measurements and (b) thyristor optical spectrum.
excursion of input voltage above the switching point to achieve a zero output value. This is attributed to the non-zero current in the o state which may be substantially reduced. Time-dependent sampling measurements were made to demonstrate the comparator function using the above thyristors. The thyristors are accessed by probe on wafer to combine them with the o-the-shelf dierential ampli®ers. The experimental results are shown in Fig. 6. The experi-
mental data show that the comparator operation is achieved. When the input signal is larger than 2 V, the output is ``1'', and when the input signal is less than 2 V, the output is ``0''. 4. Photonic 4-bit analog-to-digital converter demonstration The photonic ADC architecture is shown in Fig. 7 and consists of two samples and holds, two
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Fig. 5. Photonic comparator electrical and optical characteristics.
Fig. 6. Time-dependent experimental result of comparator operation.
analog switches and one photonic comparator. The ADC produces the digital version of the input signal as a time sequence of N output pulses in N clock cycles. The general expression for ith-bit Vout is equal to Vout i Vout iÿ1 ÿ bi V1 zÿ1 ;
3
where bi is the comparator output for the ith evaluation which is equal to ``1'' if the ith bit is set and is equal to ``0'' otherwise, and zÿ1 implies a delay of one clock period. This architecture resembles the N-bit algorithmic architecture used in the electrical ADC.
Fig. 7. Algorithmic ADC block diagram and control signal time sequence.
However, several signi®cant improvements are achieved. First, the digital output is achieved optically from the comparator automatically and can be transmitted to remote processor via an optical ®ber. This is a signi®cant advantage for 2D array applications using 2D ®ber arrays. Second, since photonic comparator has both optical and electrical output, the structure not only brings the bene®ts of optical property to the problem of A/D conversion, but also utilizes advanced electrical techniques. Third, in the electrical ADC, the subtraction of Vref at each bit from the input voltage is
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associated with the comparatorÕs output, but this subtraction is not directly controlled by the comparator. A logic circuit is necessary to decide whether Vref should be subtracted from the input according to the comparatorÕs output. In the thyristor architecture, the optical output expresses the ith-bit digital output, and the quasi-digital electrical output at the subcollector node Vsc Vref is the value that needs to be subtracted from the input. This output is digital in the sense that it is the same for each stage but analog because it is subtracted from an analog voltage. So, in fact, the thyristor-based comparator includes the logic circuit function required in the electrical architecture. Because of this multi-functional nature of the thyristor, we call this con®guration as SC. Using this photonic comparator, the algorithmic ADC is demonstrated. In the algorithmic architecture, two analog switches and two sample/hold (S/H) circuits are needed to separate the input signal and output signal since the ith-bit output will be the next bit input. Therefore, four control signals should be used to control the four devices, i.e. two analog switches and two S/H ampli®ers, respectively, and these four control signals should operate with a particular time sequence which is shown in the Fig. 7. In the experiment, the control circuit is constructed with discrete digital devices. In or-
der to realize a 4-bit ADC here, 16 clock cycles are needed. First, the clocks are counted by a 4-bit binary counter, and then using four to 16 decoders, 16 output signals are generated corresponding to the clock cycles. On combining the particular output signals and using logic gate devices, the required control signals are realized. The discrete devices used here which include analog switches, S/H ampli®ers, and logic gates are o-the-shelf items fabricated in CMOS and BICMOS. It should be mentioned that the circuit we used here to generate the control signals is not the optimum one but is the most expeditious in our experiment. When the IC is used to fabricate the algorithmic converter, it becomes ideal for the 2D planar array since the compact smart converter cell structure allows a high density of parallel optical inputs as the front end of a digital optical signal processor. Multi-bit photonic A/D conversion is realized using the architecture shown in Fig. 7 with discrete devices. The discrete devices used here include analog switches, S/H ampli®ers and logic timing circuits which are o-the-shelf items fabricated in CMOS. Since in inversion channel technology thyristor and HFET control circuits have been implemented in the same chip, an integrated photonic ADC is feasible. The 4-bit photonic A/D
Fig. 8. 4-bit photonic ADC result.
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conversion result is shown in Fig. 8. The low waveform is the input analog signal which is a ramped voltage from a pulse generator (a pulse with a long rise time and a short fall time). The middle one is the clock signal which activates the S/H of the input analog signal. ``Sample'' starts at the fall time and ``hold'' starts at the rise time, so the input analog signal is held and sent to the thyristor for A/D conversion at the point when clock signal moves from low to high. The top waveform is the output from the optoelectronic thyristor. The four bits from the ADC are identi®ed in the ®gure and labeled as a 1,0 pattern. The correct AD operation is easily veri®ed by comparing the bit pattern to the analog voltage which is at the beginning of each conversion cycle and is listed at the side of this ®gure. 5. Potential speed of operation The highest speed of operation is obtained from the pipelined con®guration of SCs which is the one in which each SC is separated from the next by a S/ H circuit. Since the output of the comparator is optical there are no shift registers to store the state. Instead, the optical bit is transmitted (e.g. on an optical ®ber) and the D/A detection circuit at the receiving end is designed to reproduce the analog signal by starting with the MSB and ®nishing with the LSB (in time). This con®guration has the advantage that, after the time has elapsed for the analog signal to be delivered initially to each SC in the chain, for each clock cycle, a full digital output for the next incremental analog input is obtained. Therefore, in this mode, the sample rate for the A/D conversion is the inverse of the SC switching time since a full digital word is produced at each cycle. One of the advantages of the pipelined con®guration is that a S/H pulse is applied to a S/H circuit between each SC stage. It is convenient to use this pulse to reset the thyristor simultaneously which is possible since each thyristor is isolated from the S/H by a DA stage. Therefore, the SC response time is the turn-on time of the thyristor added to the propagation delay of two DA stages. Of course, the sample time or response time of the
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S/H circuit can be no faster than the switch-o time of the thyristor. Therefore, the conversion time which is the processing time between samples is given by tconv son 2sDA ; where son is the turn-on time of the thyristor, sDA is the propagation delay of the dierential ampli®er and it is assumed that the thyristor has been turned o during the sample time tsample . The sample time must be at least soff to ensure complete recovery of the thyristor and for this we should add a safety margin of Dt to avoid noiseinduced errors, and therefore, tsample soff Dt: The overall conversion of the ADC is then ÿ tADC tsample tconv son soff 2sDA Dt; and the ADC sampling rate is 1=tADC . Ideally, we would like to have tsample tconv which implies that soff son sDA ÿ Dt: This requirement ®ts naturally with the switching parameters of the thyristor since switch-on is usually signi®cantly faster than switch-o. This kind of analysis shows how critically dependent the speed is upon the switching parameters of the thyristor. The son is scalable to very low values, of the order of the transit time across the internal junction which is in the 2 ps range. The sDA is also in the 5±10 ps range for a scaled FET structure. Therefore, the dominant speed limitation is the turn-o time of the thyristor and this is determined by the charge-up time of the internal device capacitance through the load element plus the transit time through the device. Consider a thyristor with an internal region of 0.5 lm, and a 5 lm diameter. Then, the capacitance is 4 fF. Assuming an operating current of 2 mA and a bias point of Vh 0:5 V, the resistance of the load is 200 X. Thus, the rise time of 2.2RC is 1.8 ps and then soff sTR 2:2RC 2:5 1:8 ps. Assuming Dt 4 ps, the sampling rate is 2tsample or approximately 100 GS/s
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(note that we require sDA 3 ps to reach the condition of tsample tconv above). Additional scaling is possible with more aggressive designs.
Acknowledgements This work was supported by AFRL Rome Laboratory, under contract F30602-98-C-0217.
6. Conclusion In conclusion, a new photonic comparator for optical ADC has been described based on a highspeed three-terminal electro-optic thyristor as an electronic comparator with an optical output. The comparator comprises only two components and thus oers a major reduction in component count. Furthermore, since the comparator itself makes the decision for subtraction, the logic circuit in the ADC is not necessary, and this makes very highspeed operation possible. The digital output of the ADC is obtained automatically as the laser emission of the comparators in which a thyristor in the on-state with emission is a ``1'' and a thyristor in the o-state with no emission is a ``0''.
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