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Dependence of electrical properties on interfacial layer of Ta2O5 films
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Microelectronic Engineering 84 (2007) 2865–2868 www.elsevier.com/locate/mee
Dependence of electrical properties on interfacial layer of Ta2O5 films Jae-Woong Lee a, Moon-Ho Ham a, Wan-Joo Maeng b, Hyungjun Kim b, Jae-Min Myoung a,* a
b
Information and Electronic Materials Research Laboratory, Department of Materials Science and Engineering, Yonsei University, 134 Shinchon-Dong, Seoul 120-749, Republic of Korea Department of Materials Science and Engineering, Pohang University of Science and Technology, Pohang 790-784, Republic of Korea Received 19 December 2006; accepted 16 February 2007 Available online 25 February 2007
Abstract The change in the thickness and chemical states of the interfacial layer and the related electrical properties in Ta2O5 films with different annealing temperatures were investigated. The high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the 700 C-annealed Ta2O5 film remained to be amorphous and had the thinnest interfacial layer which was caused by Ta-silicate decomposition to Ta2O5 and SiO2. In addition, the electrical properties were improved after annealing treatments. Our results suggest that an annealing treatment at 700 C results in the highest capacitance and the lowest leakage current in Ta2O5 films due to the thinnest interfacial layer and non-crystallization. 2007 Elsevier B.V. All rights reserved. PACS: 77.55.+f; 73.61.Ng; 68.55.Jk; 82.80.Pv; 68.37.Lp Keywords: Tantalum oxide; Interfacial layer; High-resolution transmission electron microscopy; X-ray photoelectron spectroscopy
1. Introduction Interfacial layer formation is the critical problem in using metal oxides with a high dielectric constant in complementary metal-oxide-semiconductor (CMOS) devices. The silicon dioxide (SiO2) gate insulator has been confronted with a limit of thickness, so that high dielectric constant (k) materials are considered [1]. However, an interfacial layer which is formed between the high dielectric layer and a silicon substrate has a detrimental effect on the capacitance of devices and is the impediment in the use of high-k materials. Moreover, an annealing treatment is necessary to improve the properties of the dielectric layer but generally causes a thicker interfacial layer than that of the as-deposited sample. Previous studies have reported that the thickness of the interfacial layer
*
Corresponding author. Tel.: +82 2 2123 2843; fax: +82 2 365 2680. E-mail address: [email protected] (J.-M. Myoung).
0167-9317/$ - see front matter 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.02.008
increased after annealing treatments, which led to the decrease of the capacitance due to its low dielectric constant [2,3]. Among high-k materials, Ta2O5 is one of the most promising materials due to its desirable properties such as high dielectric constant (k 25), low defect density, low leakage current, and good thermal stability [4]. In this paper, the change in the thickness and chemical states of the interfacial layer in Ta2O5 films and its effects on electrical properties were investigated as a function of annealing temperature. Ta2O5 dielectric layers were prepared by atomic layer deposition (ALD) method and then annealed at 600, 700, and 800 C in nitrogen ambient. The thickness of the interfacial layer increased after annealing treatments at 600 and 800 C, but the thickness decreased for 700 C-annealed sample. The decrease of the interfacial layer thickness reduces the detrimental effect on the capacitance, so that a higher capacitance could be obtained. Besides, the charge density decreased after annealing treatments, which resulted in the decrease of the leakage current.
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2. Experiment ˚ -thick Ta2O5 films were prepared at 250 C About 90 A on (1 0 0) p-type silicon substrates by ALD. Native oxides on the substrates were chemically eliminated by 1% HF solution prior to the growth of the films. The tantalum precursor was Pentakis (dimethylamino) Ta (PDMAT), and the oxygen plasma was used as a reactant. The argon gas was introduced as a carrier and purging gas. One ALD cycle was performed through the following sequence; an exposure to PDMAT carried by Ar, evacuating the chamber by Ar purging for 3 s, an exposure to oxygen plasma for 3 s with an rf power of 300 W, followed by another Ar purging for 3 s. The growth rate of the process is ˚ per 1 cycle. In order to examine post-annealing 1.25 A effects of interfacial layers, rapid thermal annealing (RTA) treatments were performed at 600, 700, and 800 C in nitrogen ambient for 1 min. The crystallinity and microstructure of Ta2O5 films and interfacial layers were investigated by high-resolution transmission electron microscopy (HRTEM) operating at 400 kV. By X-ray photoelectron spectroscopy (XPS) spectra using 1486.6 eV Al Ka source, the chemical compositions and states of elements were analyzed. The current–voltage (I–V) and capacitance–voltage (C–V) characteristics were measured with HP 4145B semiconductor parameter analyzer and HP 4284A capacitance meter at 1 MHz frequency, respectively. 3. Results and discussion Fig. 1 shows HRTEM images of the Ta2O5 films which were as-deposited and annealed at different temperatures of 600, 700, and 800 C in nitrogen ambient for 1 min. The Ta2O5 layers remained to be amorphous states when the samples were annealed below 700 C. For the sample annealed at 800 C, the Ta2O5 layer was partially crystal˚ because of the denlized, and its thickness decreased to 7 A sification effect during crystallization compared with the
Fig. 1. HRTEM images of (a) the as-deposited Ta2O5 film and the Ta2O5 films annealed at (b) 600 C, (c) 700 C, and (d) 800 C in nitrogen ambient for 1 min.
case of as-deposited sample [5]. During deposition and post-annealing treatments, the thin interfacial layer was formed as a result of reactions occurred between the gate dielectric and the silicon substrate. The thickness of the interfacial layers generally increases after annealing treatments due to the diffusion of silicon, tantalum, and oxygen atoms from the substrates and the Ta2O5 films [6–8]. This phenomenon was observed for the samples annealed at 600 and 800 C which are shown in Fig. 1b and d, respectively. On the other hand, the interfacial layer thickness of ˚ comthe 700 C-annealed sample showed a decrease of 2 A pared with the case of as-deposited sample as shown in Fig. 1c. This result is different from the previous reports [6–8]. In order to investigate the change of the chemical states in the interfacial layers, XPS studies were performed. The XPS spectra of Si 2p core levels which were calibrated from C 1s peak at 285 eV are shown in Fig. 2. The interface transition region consists of a mixture of Si in various oxidation states such as bulk Si, Si1+–Si3+, Ta-silicate, and SiO2(Si4+) [9]. From the binding energy of 98.7 eV corresponding to the metallic Si 2p [10], the oxidation states showed the chemical shifts of 0.95, 1.75, 2.72, and 4.1 eV for Si1+–Si4+, respectively. The Si 2p peak at 102.1 eV indicates the formation of Ta-silicate which is formed during deposition and annealing treatments of the Ta2O5 films [8,11,12]. In order to identify the change in the chemical states of the interfacial layer, the atomic percent areas of the components were considered. The atomic percent areas of the intermediate oxidation states between Ta2O5 layers and Si substrates are summarized in Table 1. After the annealing treatment at 600 C, Si2O and SiO decreased because they bonded with the excess oxygen mainly diffused from the Ta2O5 films [13]. Instead, Ta-silicate increased from 27.2% to 35.7% due to the bond of Ta, O, and Si diffused into the interfacial layer. During this process, the physical thickness of the
Fig. 2. Si 2p photoelectron spectra of (a) the as-deposited Ta2O5 film and the Ta2O5 films annealed at (b) 600 C, (c) 700 C, and (d) 800 C in nitrogen ambient for 1 min.
J.-W. Lee et al. / Microelectronic Engineering 84 (2007) 2865–2868
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Table 1 The atomic percent areas of the intermediate-oxidation states at Ta2O5/ Si(1 0 0) interface, identified by Si 2p spectra Oxidation state
Atomic % area
As-deposited 1+
Si Si2+ Si3+ Ta-silicate Si4+
9.1 18.6 10.6 27.2 34.5
Annealing temperature (C) 600
700
800
1.7 12.8 28.2 35.7 21.6
7.3 2.4 21.7 23.9 44.7
1.7 1.2 15.9 44.8 36.4
interfacial layer increased, as shown in Fig. 1b. On the other hand, for 700 C-annealed sample, Ta-silicate decreased to 23.9%, and SiO2 increased to 44.7%. In addition, an atomic percent area of Ta2O5 in O 1s spectra (not shown here) increased to 5% compared with the case of as-deposited sample. From the relative change of the chemical states, it can be concluded that Ta-silicate decomposed into Ta2O5 and SiO2 [11]. The ternary compound for Ta–Si–O systems is thermodynamically unstable, so that it decomposes into more stable Ta2O5 and SiO2 [14]. It agrees well with the HRTEM image which showed a decrease of the interfacial layer thickness as illustrated in Fig. 1c. During the annealing treatment at 800 C, the formation and decomposition of Ta-silicate in the sample occurred simultaneously. In the 800 Cannealed sample, Ta-silicate increased again and non-stoichiometric states decreased significantly as shown in Table 1. It supports that the Ta-silicate formation rate is higher than the Ta-silicate decomposition rate, resulting in the increase of the interfacial layer thickness as shown in Fig. 1d. The electrical properties of the Ta2O5 dielectric films were evaluated as a function of annealing temperature through C–V and I–V analyses. The Al/Ta2O5/p-type Si MOS capacitor structure was fabricated by the thermal evaporation of Al on the Ta2O5 layer, and an active area of the stack was 3.14 · 104 cm2. Fig. 3a shows the C–V curves measured at 1 MHz frequency. The applied voltage was swept from 5 to +5 V and then was swept back to 5 V. The accumulation capacitance increased after the annealing treatments, which had a maximum for the 700 C-annealed sample. Note that the capacitance is susceptibly affected by the thickness and the chemical states of the interfacial layer. The 600 C- and 800 C-annealed samples had thicker interface layers than that of the asdeposited sample. Nevertheless, they had the higher accumulation capacitance. It is due to the increase of the amount of Ta-silicate which has a high dielectric constant. It agrees well with the previous work, where the enhanced accumulation capacitance resulted from the increase of the silicate concentration with a high dielectric constant [6]. On the other hand, the 700 C-annealed sample with the highest capacitance showed the decrease of the interfacial layer thickness as well as the decrease of the amount of Ta-silicate. This reveals that the highest capacitance of
Fig. 3. C–V characteristics for the Ta2O5 films with different annealing temperatures measured at 1 MHz frequency. The inset shows the oxide trapped density (Ntot). (b) I–V characteristics for the Ta2O5 films with different annealing temperatures.
the 700 C-annealed sample is due to the decrease of the interfacial layer thickness. This phenomenon means that the thickness rather than the chemical state in the interfacial layer plays a significant role in determining the capacitance of the 700 C-annealed sample. In addition, as the annealing temperatures increased, the C–V curves shifted to the positive gate bias because of the decrease of the positive charges which were attributed to the positive fixed oxide charges and mobile ionic charges [15,16]. The C–V hysteresis curves were observed for all the samples. They were due to the existence of the negative charges trapped in the oxide defect states [16,17]. The inset in Fig. 3a shows the oxide trapped density (denoted as Not) of MOS stacks which can be calculated using the following equation N ot ¼ C acc DV FB =ðqAÞ where Cacc is accumulation capacitance, DVFB is the hysteresis width, q is the electron charge and A is the electrode area [18]. As the annealing temperature increased to 700 C, the oxide trapped density decreased. However, for the sample annealed at 800 C, the oxide trapped density slightly increased because of the partially crystallized
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Ta2O5 layer which contained the defects such as grain boundaries and vacancies. Fig. 3b shows the I–V characteristics of the Ta2O5 films with different annealing temperatures. The leakage current significantly decreased after the annealing treatments. These leakage current characteristics were attributed to the reduction of the leakage paths such as interfacial trapped charges, oxygen vacancies, and contaminants [5]. The 700 C-annealed Ta2O5 film had the lowest leakage current density of 2.83 · 107 A/cm2, while the 800 Cannealed sample had a higher leakage current than that of the 700 C-annealed sample because of the partial crystallization in the Ta2O5 layer. 4. Conclusion In summary, the change in the thickness and chemical states of the interfacial layer and the related electrical properties of the Ta2O5 dielectric films with different annealing temperatures were investigated. From the HRTEM images, the 700 C-annealed sample was observed to be amorphous with the thinnest interfacial layer, whereas the 800 Cannealed sample was found to be partially crystallized. The XPS analyses demonstrated that the decrease of the interfacial layer thickness was attributed to the Ta-silicate decomposition into Ta2O5 and SiO2. After the annealing treatments, the electrical properties were improved. In particular, the 700 C-annealed sample was found to have the highest capacitance density and the lowest leakage current density. Therefore, our results suggest that the change in the interfacial layer thickness by post-annealing treatments plays a significant role in enhancing the electrical properties.
Acknowledgement This work was supported by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2005-041-D00402). References [1] G.D. Wilk, R.M. Wallace, J.M. Anthony, J. Appl. Phys. 89 (2001) 5243. [2] C. Chaneliere, J.L. Autran, R.A.B. Devine, B. Balland, Mater. Sci. Eng. R-Rep. R 22 (1998) 269. [3] F.C. Chiu, J.-J. Wang, J.Y.M. Lee, S.C. Wu, J. Appl. Phys. 81 (1997) 6911. [4] P. Balk, Adv. Mater. 7 (1995) 703. [5] H.J. Song, C.S. Lee, S.W. Kang, Electrochem. Solid State Lett. 4 (2001) F13. [6] T.H. Moon, M.H. Ham, J.M. Myoung, Appl. Phys. Lett. 86 (2005) 102903. [7] R.A.B. Devine, Appl. Phys. Lett. 68 (1996) 1924. [8] G.B. Alers, D.J. Werderk, Y. Chabal, H.C. Lu, E.P. Gusev, T. Gustafsson, R.S. Urdahl, Appl. Phys. Lett. 73 (1998) 1517. [9] F.J. Himpsel, F.R. McFeely, A. Taleb-Ibrahimi, J.A. Yarmoff, Phys. Rev. B 38 (1988) 6084. [10] C.H.F. Peden, J.W. Rogers Jr., N.D. Shinn, K.B. Kidd, K.L. Tsang, Phys. Rev. B 47 (1993) 15622. [11] X. Zhao, M. Leavy, N.P. Magtoto, J.A. Kelber, Appl. Phys. Lett. 79 (2001) 3479. [12] H. Ono, Y. Hosokawa, T. Ikarashi, K. Shinoda, N. Ikarashi, K. Koyanagi, H. Yamaguchi, J. Appl. Phys. 89 (2001) 995. [13] H.J. Park, A. Mao, D.L. Kwong, J.M. White, J. Vac. Sci. Technol. A 18 (2000) 2522. [14] R. Beyers, J. Appl. Phys. 56 (1984) 147. [15] B.C.M. Lai, N.H. Kung, J.Y.M. Lee, J. Appl. Phys. 85 (1999) 4087. [16] Y. Taur, T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, New York, 1998, p. 82. [17] N.A. Chowdhury, R. Garg, D. Misra, Appl. Phys. Lett. 85 (2004) 3289. [18] J.H. Hong, T.H. Moon, J.M. Myoung, Microelectron. Eng. 75 (2004) 263.
Microelectronic Engineering 84 (2007) 2865–2868 www.elsevier.com/locate/mee
Dependence of electrical properties on interfacial layer of Ta2O5 films Jae-Woong Lee a, Moon-Ho Ham a, Wan-Joo Maeng b, Hyungjun Kim b, Jae-Min Myoung a,* a
b
Information and Electronic Materials Research Laboratory, Department of Materials Science and Engineering, Yonsei University, 134 Shinchon-Dong, Seoul 120-749, Republic of Korea Department of Materials Science and Engineering, Pohang University of Science and Technology, Pohang 790-784, Republic of Korea Received 19 December 2006; accepted 16 February 2007 Available online 25 February 2007
Abstract The change in the thickness and chemical states of the interfacial layer and the related electrical properties in Ta2O5 films with different annealing temperatures were investigated. The high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the 700 C-annealed Ta2O5 film remained to be amorphous and had the thinnest interfacial layer which was caused by Ta-silicate decomposition to Ta2O5 and SiO2. In addition, the electrical properties were improved after annealing treatments. Our results suggest that an annealing treatment at 700 C results in the highest capacitance and the lowest leakage current in Ta2O5 films due to the thinnest interfacial layer and non-crystallization. 2007 Elsevier B.V. All rights reserved. PACS: 77.55.+f; 73.61.Ng; 68.55.Jk; 82.80.Pv; 68.37.Lp Keywords: Tantalum oxide; Interfacial layer; High-resolution transmission electron microscopy; X-ray photoelectron spectroscopy
1. Introduction Interfacial layer formation is the critical problem in using metal oxides with a high dielectric constant in complementary metal-oxide-semiconductor (CMOS) devices. The silicon dioxide (SiO2) gate insulator has been confronted with a limit of thickness, so that high dielectric constant (k) materials are considered [1]. However, an interfacial layer which is formed between the high dielectric layer and a silicon substrate has a detrimental effect on the capacitance of devices and is the impediment in the use of high-k materials. Moreover, an annealing treatment is necessary to improve the properties of the dielectric layer but generally causes a thicker interfacial layer than that of the as-deposited sample. Previous studies have reported that the thickness of the interfacial layer
*
Corresponding author. Tel.: +82 2 2123 2843; fax: +82 2 365 2680. E-mail address: [email protected] (J.-M. Myoung).
0167-9317/$ - see front matter 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.02.008
increased after annealing treatments, which led to the decrease of the capacitance due to its low dielectric constant [2,3]. Among high-k materials, Ta2O5 is one of the most promising materials due to its desirable properties such as high dielectric constant (k 25), low defect density, low leakage current, and good thermal stability [4]. In this paper, the change in the thickness and chemical states of the interfacial layer in Ta2O5 films and its effects on electrical properties were investigated as a function of annealing temperature. Ta2O5 dielectric layers were prepared by atomic layer deposition (ALD) method and then annealed at 600, 700, and 800 C in nitrogen ambient. The thickness of the interfacial layer increased after annealing treatments at 600 and 800 C, but the thickness decreased for 700 C-annealed sample. The decrease of the interfacial layer thickness reduces the detrimental effect on the capacitance, so that a higher capacitance could be obtained. Besides, the charge density decreased after annealing treatments, which resulted in the decrease of the leakage current.
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2. Experiment ˚ -thick Ta2O5 films were prepared at 250 C About 90 A on (1 0 0) p-type silicon substrates by ALD. Native oxides on the substrates were chemically eliminated by 1% HF solution prior to the growth of the films. The tantalum precursor was Pentakis (dimethylamino) Ta (PDMAT), and the oxygen plasma was used as a reactant. The argon gas was introduced as a carrier and purging gas. One ALD cycle was performed through the following sequence; an exposure to PDMAT carried by Ar, evacuating the chamber by Ar purging for 3 s, an exposure to oxygen plasma for 3 s with an rf power of 300 W, followed by another Ar purging for 3 s. The growth rate of the process is ˚ per 1 cycle. In order to examine post-annealing 1.25 A effects of interfacial layers, rapid thermal annealing (RTA) treatments were performed at 600, 700, and 800 C in nitrogen ambient for 1 min. The crystallinity and microstructure of Ta2O5 films and interfacial layers were investigated by high-resolution transmission electron microscopy (HRTEM) operating at 400 kV. By X-ray photoelectron spectroscopy (XPS) spectra using 1486.6 eV Al Ka source, the chemical compositions and states of elements were analyzed. The current–voltage (I–V) and capacitance–voltage (C–V) characteristics were measured with HP 4145B semiconductor parameter analyzer and HP 4284A capacitance meter at 1 MHz frequency, respectively. 3. Results and discussion Fig. 1 shows HRTEM images of the Ta2O5 films which were as-deposited and annealed at different temperatures of 600, 700, and 800 C in nitrogen ambient for 1 min. The Ta2O5 layers remained to be amorphous states when the samples were annealed below 700 C. For the sample annealed at 800 C, the Ta2O5 layer was partially crystal˚ because of the denlized, and its thickness decreased to 7 A sification effect during crystallization compared with the
Fig. 1. HRTEM images of (a) the as-deposited Ta2O5 film and the Ta2O5 films annealed at (b) 600 C, (c) 700 C, and (d) 800 C in nitrogen ambient for 1 min.
case of as-deposited sample [5]. During deposition and post-annealing treatments, the thin interfacial layer was formed as a result of reactions occurred between the gate dielectric and the silicon substrate. The thickness of the interfacial layers generally increases after annealing treatments due to the diffusion of silicon, tantalum, and oxygen atoms from the substrates and the Ta2O5 films [6–8]. This phenomenon was observed for the samples annealed at 600 and 800 C which are shown in Fig. 1b and d, respectively. On the other hand, the interfacial layer thickness of ˚ comthe 700 C-annealed sample showed a decrease of 2 A pared with the case of as-deposited sample as shown in Fig. 1c. This result is different from the previous reports [6–8]. In order to investigate the change of the chemical states in the interfacial layers, XPS studies were performed. The XPS spectra of Si 2p core levels which were calibrated from C 1s peak at 285 eV are shown in Fig. 2. The interface transition region consists of a mixture of Si in various oxidation states such as bulk Si, Si1+–Si3+, Ta-silicate, and SiO2(Si4+) [9]. From the binding energy of 98.7 eV corresponding to the metallic Si 2p [10], the oxidation states showed the chemical shifts of 0.95, 1.75, 2.72, and 4.1 eV for Si1+–Si4+, respectively. The Si 2p peak at 102.1 eV indicates the formation of Ta-silicate which is formed during deposition and annealing treatments of the Ta2O5 films [8,11,12]. In order to identify the change in the chemical states of the interfacial layer, the atomic percent areas of the components were considered. The atomic percent areas of the intermediate oxidation states between Ta2O5 layers and Si substrates are summarized in Table 1. After the annealing treatment at 600 C, Si2O and SiO decreased because they bonded with the excess oxygen mainly diffused from the Ta2O5 films [13]. Instead, Ta-silicate increased from 27.2% to 35.7% due to the bond of Ta, O, and Si diffused into the interfacial layer. During this process, the physical thickness of the
Fig. 2. Si 2p photoelectron spectra of (a) the as-deposited Ta2O5 film and the Ta2O5 films annealed at (b) 600 C, (c) 700 C, and (d) 800 C in nitrogen ambient for 1 min.
J.-W. Lee et al. / Microelectronic Engineering 84 (2007) 2865–2868
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Table 1 The atomic percent areas of the intermediate-oxidation states at Ta2O5/ Si(1 0 0) interface, identified by Si 2p spectra Oxidation state
Atomic % area
As-deposited 1+
Si Si2+ Si3+ Ta-silicate Si4+
9.1 18.6 10.6 27.2 34.5
Annealing temperature (C) 600
700
800
1.7 12.8 28.2 35.7 21.6
7.3 2.4 21.7 23.9 44.7
1.7 1.2 15.9 44.8 36.4
interfacial layer increased, as shown in Fig. 1b. On the other hand, for 700 C-annealed sample, Ta-silicate decreased to 23.9%, and SiO2 increased to 44.7%. In addition, an atomic percent area of Ta2O5 in O 1s spectra (not shown here) increased to 5% compared with the case of as-deposited sample. From the relative change of the chemical states, it can be concluded that Ta-silicate decomposed into Ta2O5 and SiO2 [11]. The ternary compound for Ta–Si–O systems is thermodynamically unstable, so that it decomposes into more stable Ta2O5 and SiO2 [14]. It agrees well with the HRTEM image which showed a decrease of the interfacial layer thickness as illustrated in Fig. 1c. During the annealing treatment at 800 C, the formation and decomposition of Ta-silicate in the sample occurred simultaneously. In the 800 Cannealed sample, Ta-silicate increased again and non-stoichiometric states decreased significantly as shown in Table 1. It supports that the Ta-silicate formation rate is higher than the Ta-silicate decomposition rate, resulting in the increase of the interfacial layer thickness as shown in Fig. 1d. The electrical properties of the Ta2O5 dielectric films were evaluated as a function of annealing temperature through C–V and I–V analyses. The Al/Ta2O5/p-type Si MOS capacitor structure was fabricated by the thermal evaporation of Al on the Ta2O5 layer, and an active area of the stack was 3.14 · 104 cm2. Fig. 3a shows the C–V curves measured at 1 MHz frequency. The applied voltage was swept from 5 to +5 V and then was swept back to 5 V. The accumulation capacitance increased after the annealing treatments, which had a maximum for the 700 C-annealed sample. Note that the capacitance is susceptibly affected by the thickness and the chemical states of the interfacial layer. The 600 C- and 800 C-annealed samples had thicker interface layers than that of the asdeposited sample. Nevertheless, they had the higher accumulation capacitance. It is due to the increase of the amount of Ta-silicate which has a high dielectric constant. It agrees well with the previous work, where the enhanced accumulation capacitance resulted from the increase of the silicate concentration with a high dielectric constant [6]. On the other hand, the 700 C-annealed sample with the highest capacitance showed the decrease of the interfacial layer thickness as well as the decrease of the amount of Ta-silicate. This reveals that the highest capacitance of
Fig. 3. C–V characteristics for the Ta2O5 films with different annealing temperatures measured at 1 MHz frequency. The inset shows the oxide trapped density (Ntot). (b) I–V characteristics for the Ta2O5 films with different annealing temperatures.
the 700 C-annealed sample is due to the decrease of the interfacial layer thickness. This phenomenon means that the thickness rather than the chemical state in the interfacial layer plays a significant role in determining the capacitance of the 700 C-annealed sample. In addition, as the annealing temperatures increased, the C–V curves shifted to the positive gate bias because of the decrease of the positive charges which were attributed to the positive fixed oxide charges and mobile ionic charges [15,16]. The C–V hysteresis curves were observed for all the samples. They were due to the existence of the negative charges trapped in the oxide defect states [16,17]. The inset in Fig. 3a shows the oxide trapped density (denoted as Not) of MOS stacks which can be calculated using the following equation N ot ¼ C acc DV FB =ðqAÞ where Cacc is accumulation capacitance, DVFB is the hysteresis width, q is the electron charge and A is the electrode area [18]. As the annealing temperature increased to 700 C, the oxide trapped density decreased. However, for the sample annealed at 800 C, the oxide trapped density slightly increased because of the partially crystallized
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Ta2O5 layer which contained the defects such as grain boundaries and vacancies. Fig. 3b shows the I–V characteristics of the Ta2O5 films with different annealing temperatures. The leakage current significantly decreased after the annealing treatments. These leakage current characteristics were attributed to the reduction of the leakage paths such as interfacial trapped charges, oxygen vacancies, and contaminants [5]. The 700 C-annealed Ta2O5 film had the lowest leakage current density of 2.83 · 107 A/cm2, while the 800 Cannealed sample had a higher leakage current than that of the 700 C-annealed sample because of the partial crystallization in the Ta2O5 layer. 4. Conclusion In summary, the change in the thickness and chemical states of the interfacial layer and the related electrical properties of the Ta2O5 dielectric films with different annealing temperatures were investigated. From the HRTEM images, the 700 C-annealed sample was observed to be amorphous with the thinnest interfacial layer, whereas the 800 Cannealed sample was found to be partially crystallized. The XPS analyses demonstrated that the decrease of the interfacial layer thickness was attributed to the Ta-silicate decomposition into Ta2O5 and SiO2. After the annealing treatments, the electrical properties were improved. In particular, the 700 C-annealed sample was found to have the highest capacitance density and the lowest leakage current density. Therefore, our results suggest that the change in the interfacial layer thickness by post-annealing treatments plays a significant role in enhancing the electrical properties.
Acknowledgement This work was supported by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2005-041-D00402). References [1] G.D. Wilk, R.M. Wallace, J.M. Anthony, J. Appl. Phys. 89 (2001) 5243. [2] C. Chaneliere, J.L. Autran, R.A.B. Devine, B. Balland, Mater. Sci. Eng. R-Rep. R 22 (1998) 269. [3] F.C. Chiu, J.-J. Wang, J.Y.M. Lee, S.C. Wu, J. Appl. Phys. 81 (1997) 6911. [4] P. Balk, Adv. Mater. 7 (1995) 703. [5] H.J. Song, C.S. Lee, S.W. Kang, Electrochem. Solid State Lett. 4 (2001) F13. [6] T.H. Moon, M.H. Ham, J.M. Myoung, Appl. Phys. Lett. 86 (2005) 102903. [7] R.A.B. Devine, Appl. Phys. Lett. 68 (1996) 1924. [8] G.B. Alers, D.J. Werderk, Y. Chabal, H.C. Lu, E.P. Gusev, T. Gustafsson, R.S. Urdahl, Appl. Phys. Lett. 73 (1998) 1517. [9] F.J. Himpsel, F.R. McFeely, A. Taleb-Ibrahimi, J.A. Yarmoff, Phys. Rev. B 38 (1988) 6084. [10] C.H.F. Peden, J.W. Rogers Jr., N.D. Shinn, K.B. Kidd, K.L. Tsang, Phys. Rev. B 47 (1993) 15622. [11] X. Zhao, M. Leavy, N.P. Magtoto, J.A. Kelber, Appl. Phys. Lett. 79 (2001) 3479. [12] H. Ono, Y. Hosokawa, T. Ikarashi, K. Shinoda, N. Ikarashi, K. Koyanagi, H. Yamaguchi, J. Appl. Phys. 89 (2001) 995. [13] H.J. Park, A. Mao, D.L. Kwong, J.M. White, J. Vac. Sci. Technol. A 18 (2000) 2522. [14] R. Beyers, J. Appl. Phys. 56 (1984) 147. [15] B.C.M. Lai, N.H. Kung, J.Y.M. Lee, J. Appl. Phys. 85 (1999) 4087. [16] Y. Taur, T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, New York, 1998, p. 82. [17] N.A. Chowdhury, R. Garg, D. Misra, Appl. Phys. Lett. 85 (2004) 3289. [18] J.H. Hong, T.H. Moon, J.M. Myoung, Microelectron. Eng. 75 (2004) 263.