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Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata
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Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata Shaahin Angizi a, Soheil Sarmadi a, Samira Sayedsalehi a, Keivan Navi a,b,n a b
Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G. C., Tehran, Iran Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran
art ic l e i nf o
a b s t r a c t
Article history: Received 8 September 2013 Received in revised form 7 October 2014 Accepted 7 October 2014
Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-à-vis state-of-the-art. & 2014 Elsevier Ltd. All rights reserved.
Keywords: Quantum-dotcellular automata (QCA) Five-input majority gate RAM cell Set and reset ability
1. Introduction In recent years, shrinkage in CMOS circuits' dimensions has faced serious challenges such as leakage current and high power consumption which prevent the exponential trend of decrease in feature size. Studies to find new approaches to substitute conventional CMOS circuits have increased. Quantum-dot cellular automata is one of these approaches for digital logic designs at Nano scale with ultralow power, high performance and least feature size [1,2]. Each QCA cell is composed of four dots and two excess electrons. These electrons can tunnel between dots due to columbic repulsion and diagonally occupy corners of the cell, hence leading to two stable arrangements for QCA cell which are shown in Fig. 1. These two stable states of QCA cell is named cell polarization. Polarizations 1 and þ1 are encoded as logic “0” and “1”, respectively. As it is shown in Fig. 2(a), by placing several QCA cells side by side, a standard QCA wire can be constructed to propagate a logic value. Moreover, a QCA inverter chain can be constructed exploiting 451 rotated QCA cells. This kind of wire propagates the input signal in odd cells and inversion of the input signal in even cells, as shown in
n Corresponding author at: Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G. C., Tehran, Iran. Tel.: þ 98 2129904195; fax: þ98 2122431804. E-mail addresses: [email protected] (S. Angizi), [email protected] (S. Sarmadi), [email protected] (S. Sayedsalehi), [email protected] (K. Navi).
Fig. 2(b). Coplanar wire crossing is achieved using these two types of wires as shown in Fig. 3 [2]. Structural properties of QCA cells within a wire lead to perform computations using a four-phase clock which in turn allow designing parallel QCA circuit employing four clocks [3]. As it is illustrated in Fig. 4, each clocking zone goes through all four phases (Switch, Hold, Release and Relax) each of which has a 901 phase delay from the other. In the switch phase, cell polarization is affected by the juxtaposed cells. Cells keep their polarizations during the hold phase and only can determine the polarization of neighbor cells, which are in the switch phase. In the release and relax phases, cells lose their polarizations and stay un-polarized until the next switch phase [4,9]. The control of data flow is a significant part of designing a robust QCA structure which is gained by increasing cell numbers in the clocking zones [3]. It is also noteworthy that number of cells in each clocking zone must be at least two cells to prevent noise effects on QCA circuit [4,5]. Till date many efforts have been made to implement QCA digital logic circuits; for instance, in [6,7] new structures for five-input majority gate are presented. Also designs for one-bit full adder [7,8], studies on configurable logic gates [22], analysis of fault tolerance and reliability for QCA designs [5,23–27] and flip flops and memory structures [10–20] have been presented. In most of the mentioned works, QCADesigner [28] tool which is an open source simulator has been employed for modeling and verifying QCA structures. To the best of our knowledge, the BNs (Bayesian Networks) model [29] is also used for evaluating and modeling QCA circuits.
http://dx.doi.org/10.1016/j.mejo.2014.10.003 0026-2692/& 2014 Elsevier Ltd. All rights reserved.
Please cite this article as: S. Angizi, et al., Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.10.003i
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The main aim of this study is to implement a new robust RAM cell with set and reset ability based on the new five-input majority gate with least cell count, input to output latency and area occupation. Rest of the paper is organized as follow: Section 2 provides a review on QCA elementary logics and previous structures of RAM cells. New five-input majority gate is addressed in Section 3. In Section 4, the novel robust QCA design and implementation for RAM are proposed based on the five-input majority gate. Section 5 includes simulation results and finally Section 6 concludes this paper.
2. QCA review In this section, the common QCA logics are explained in the order of inverter and majority gate. In addition, the state-of-the-art designs for random access memory cells are reviewed.
Fig. 1. QCA basic cell with two possible polarization states.
Fig. 4. Clocking zones in QCA.
Fig. 2. (a) QCA standard wire and (b) Inverter chain.
Fig. 3. Coplanar wire crossing.
Please cite this article as: S. Angizi, et al., Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.10.003i
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Fig. 5. A QCA inverter.
Fig. 6. Three-input majority gate structure.
Fig. 8. The schematic diagram of conventional RAM cell in [11].
Table 1 Truth table of three-input majority gate. A
B
C
Maj (A, B and C)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 0 1 1 1
Fig. 7. Robust implementation of QCA three-input majority gate with the data flow directions.
2.1. Inverter QCA implementation of an inverter is illustrated in Fig. 5. The input signal is provided from left side, divided into two QCA wires and consequently merged together, therefore the complement of
Fig. 9. The first RAM cell structure presented in [18], (a) schematic diagram (b) QCA implementation.
Please cite this article as: S. Angizi, et al., Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.10.003i
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Fig. 10. The presented RAM cell structure with set and reset ability in [20], (a) schematic diagram (b) QCA implementation.
input signal is computed at the merging point and propagated to the right side [2]. 2.2. Majority gate Majority gate is one of the basic building blocks in QCA circuits due to its configurability to construct various structures. As it is shown in Fig. 6, a three-input majority gate is consisted of three input cells, one device cell and one output cell. The device cell is polarized to the majority polarization due to electron repulsion between the three input cells [2]. Truth table of three-input majority gate is shown in Table 1. Assume that the inputs are A, B and C, so the logic function of majority gate is: MðA; B; CÞ ¼ AB þ AC þ BC
ð1Þ
By setting the polarization of one input cell (C) to constant value of 1 (“0” in binary), majority gate functionality behaves like a two-input AND gate and the logic function demonstrated as: MðA; B; 0Þ ¼ ABþ ðAÞð0Þ þ ðBÞð0Þ ¼ AB
ð2Þ
Similarly by fixing one of the input cells (C) to polarization of þ1 (“1” in binary), two-input OR gate is achieved, as follows: MðA; B; 1Þ ¼ AB þ ðAÞð1Þ þ ðBÞð1Þ ¼ A þ B
ð3Þ
As mentioned before every QCA circuit is controlled by a clocking mechanism. As it is illustrated in Fig. 7, synchronization of the majority gate is gained when all the input signals are provided to the gate at the identical clocking zone, while middle cells are at the next clocking zone and the output cell is at the clocking zone after that of the middle cells. This rule provides QCA logic circuits with regularity and robustness [3,4]. 2.3. Previous RAM cell structures RAM cell design is one of the most attractive fields of study in QCA. Generally there are two types of RAM cell designs in QCA
Fig. 11. The second RAM cell structure presented in [18], (a) schematic diagram (b) QCA implementation.
which are categorized as loop-based [10–15,18–20] and line-based [16,17] according to the operational manner of the QCA circuits. In the loop-based RAM cell structures, storing mechanism is achieved using a loop that contains all four clocking zones, but line-based RAM cell structures use a QCA line to save previous value of the output. In this part, previous works on designing RAM cell architectures are reviewed. The authors in [11] have made an early effort to present a loopbased QCA Random Access Memory cell. As illustrated in schematic diagram of Fig. 8, the presented architecture is based on D-latch and a loop is used for saving the memory content; in QCA implementation, it also consumes two clocking cycles to transmit the input signal to the output. A QCA random access memory without set and reset ability has been suggested in [18]. As it is shown in Fig. 9(a), this design has a loop-based mechanism and is constructed based on SR-latch. when Select ¼ “1” and Write/Read ¼“0” content of RAM cell is not altered and can be read but when Select ¼ “1” and the Write/Read ¼“1” the new input will be transmitted to the output. In this structure coplanar wire crossing method has been employed, furthermore this design has used only one cell in some of the clocking zones which increases noise sensitivity of the circuit (Fig. 9(b)). First RAM cell architecture with set and reset ability has been presented in [20]. As it illustrated in Fig. 10(a), this design is composed of two
Please cite this article as: S. Angizi, et al., Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.10.003i
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Fig. 12. Reliability comparison between single-stage three-input, single stage five-input and seven-input majority gates based on PTM calculations in [27].
Fig. 13. (a) The presented structure for single-stage five-input majority gate in [6] and. (b) The presented structure for single-stage five-input majority gate in [7].
Fig. 14. (a) The schematic of a five-input majority gate and (b) QCA layout of proposed single-stage structure for five-input majority gate.
Table 2 Truth table for five-input majority gate based on the summation of the input values. Sum (A, B, C, D and E) Maj (A, B, C, D and E) 0 1 2 3 4 5
0 0 0 1 1 1
2-to-1 multiplexers. One of these multiplexers has been utilized as the D-latch by joining the output signal to the first multiplexer's input. When the select and write/read signals are equaled to “1”,
Fig. 15. (a) The schematic of proposed RAM cell and (b) The QCA layout of proposed RAM cell structure with set and reset ability using the five-input majority gate in Fig. 14(b).
new input data will be inserted in RAM cell, besides read operation has been implemented by setting write/read signal to “0”. It uses single multiplexed wire for set and reset operations, this signal also
Please cite this article as: S. Angizi, et al., Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.10.003i
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Table 3 Operations of proposed RAM cell structure in Fig. 15. Mode of Type of operation operation
Select Set Reset Write/ Input Previous read output
Output
Normal
Write Write
1 1
0 0
1 1
1 1
1 0
x x
1 0
Normal
Read Read
1 1
0 0
1 1
0 0
x x
0 1
0 1
Set
Set
x
1
1
x
x
x
1
Reset
Reset
x
0
0
x
x
x
0
determines the content of the cell only when the select signal is deactivated by “0” and write/read signal is activated by “1”. The latency of this RAM circuit is 1.75 clock cycle for transmission of the input signal to output cell (Fig. 10(b)). As it is demonstrated in Fig. 11 another design for RAM cell is presented in [18] with the same operation as the first design in Fig. 9. This structure has been based on D-latch with an un-robust three-input majority gate structure, additionally set and reset ability of RAM is lacking in this design.
3. Novel five-input majority gate As mentioned earlier majority gate is an elementary structure in QCA designs, therefore in this section a new robust five-input majority gate is presented. The logic function of five-input majority gate is
Table 4 QCADesigner parameters model.
MðA; B; C; D; EÞ ¼ ABC þ ABD þ ABE þ ACD þ ACE
Parameter
Value
Cell size Number of samples Convergence tolerance Radius of effect Relative permittivity Clock low Clock high Clock shift Clock amplitude factor Layer separation Maximum iterations per sample
18 nm 50,000 0.001000 65.000000 nm 12.900000 3.800000e-023J 9.800000e-022J 0 2.000000 11.500000 100
þ ADE þ BCD þBCE þ BDE þ CDE
ð4Þ
By setting two of the five input cells' polarizations to 1 or þ1, respectively, a three-input AND gate and also a three-input OR gate can be formed. As reliability is an essential issue for characterization of proper functionality of QCA circuits, lots of studies have been done regards to this fact. In [24], the n-input majority gate's limitations to use in computational structures are investigated through a logic-level analysis called PGM (Probabilistic Gate Model). The authors have reported that in a large tree structures of majority gates such as cascaded one-bit full adder cells (which are consisted of multi-level
Fig. 16. (a) Simulation result of presented five-input majority gate in Fig. 14(b) and (b) Simulation result of three-input AND gate.
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Fig. 17. Simulation result of proposed RAM cell structure in Fig. 15(b).
majority gates) or multi-stage multi-input majority gate when the input error rate is not zero, the information will be lost. The authors in [27] have inspected the reliability of multi-input majority gate through PTM calculations (Probabilistic Transfer Matrix) and MATLAB is used to prove that the reliability of a single-stage five-input majority gate is equal to three-input majority gate. As is illustrated in Fig. 12, by increasing the probability of gate failure, the overall reliability of three-input, five-input and seveninput majority gates will be decreased with the same rate. Based on the mentioned concepts in [24,27], in this section we are going to design a single-stage five-input majority gate as the main component of proposed RAM cell. In [6,7] two kinds of single-stage five-input majority gate have been introduced which are shown in Fig. 13(a) and (b). In the first design, the output cell is trapped by input cells therefore preventing access to it in one layer. In the later, input cells are adjacent to each other therefore causing unwanted effect on one another (For example inputs B and D or inputs C and E). One could work around this problem by providing inputs in diagonal direction rather than horizontal or vertical, but that would make the design more faultsusceptible.
Our proposed structure and the schematic of five-input majority gate are demonstrated in Fig. 14. This component can be applied to construct QCA logic circuits in a single layer. Majority gate takes all five input signals in one direction at the first clocking zone. The middle cells, which are in the next clocking zone after the input signals, are polarized based on the majority of inputs' polarizations. The output function is produced in the third clocking zone, at any of the cells in the dotted area, each of them can be connected to the output cell. Table 2 shows the truth table for five-input majority gate based on numerical summation of binary values of the five inputs.
4. The proposed RAM cell structure with set and reset ability The schematic for the proposed RAM cell structure with set and reset ability and QCA implementation of that are indicated in Fig. 15. This design is composed of three three-input majority gates and one five-input majority gate which is presented in Fig. 14(b). The proposed RAM structure is controlled by two separated signals (Set and Reset). In the normal mode (Set ¼ “0” and Reset ¼ “1”) when the select signal is activated (“1”) and write/read signal has
Please cite this article as: S. Angizi, et al., Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.10.003i
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Table 5 Comparison results of presented RAM cell structures. RAM structure
Set and Reset ability
Coplanar wire crossing
Cell count
Occupation area (lm2)
Gate count
Input to output delay (clocking cycle)
Presented RAM cell in [11] Presented RAM cell in [18] (Fig. 9) Presented RAM cell in [18] (Fig. 11) Presented RAM cell in [20] (Fig. 10) Proposed RAM cell in Fig. 15
No No No Yes Yes
Yes Yes No No No
158 100 63 109 88
0.16 0.11 0.07 0.13 0.08
8 8 6 8 5
2 3 2 1.75 1.5
been set to “1”, input data will be transmitted to the output and consequently write operation will be done. Moreover, read operation has been accomplished by setting the select and write/read signals to “1” and “0”, respectively. In the set mode, content of RAM cell will be set to “1” using the determination of set signal value by “1”. Also the reset mode will be performed by fixing the reset signal to “0” independent of the state of select and write/read signals. The complete operation of the proposed RAM cell is shown in Table 3. As previously mentioned, the output of five-input majority gate can be extracted from any one of the output cells. To achieve synchronization for the presented RAM structure, additional cells have been placed in the input, set and reset wires as shown in Fig. 15(b).
5. Simulation results In this section, simulation results of the proposed designs are verified using QCADesigner tool version 2.0.3 [21] with default parameters shown in Table 4 and also similar outcomes are achieved from both simulation engines (Bistable Approximation and Coherence Vector) of this software. Simulation result of the presented five-input majority gate is illustrated in Fig. 16(a). As it is clear, the majority of input cells' polarizations (A, B, C, D and E) determines the value of output. As mentioned earlier, three-input AND gate and three-input OR gate can be constructed by fixing two arbitrary inputs' polarizations to “ 1” and “ þ1”, respectively. Based on Fig. 16(b), accurate operation of the three-input AND gate is proved. Analysis of the achieved waveforms confirms that all the presented QCA designs work correctly. The simulation result of the proposed RAM structure is shown in Fig. 17, for example in the normal mode when the select and write/read signals are activated by “þ 1” simultaneously, the input signal is transmitted to the output after 1.5 clock cycle, rather than previous RAM designs. In addition, by fixing the set and reset lines to “ 1” reset operation is performed and the result is also evaluated after 1.5 clocking cycle. Fig. 17 shows that the proposed RAM cell works correctly and expected outcomes are obtained. Comparison results between the proposed RAM cell architecture and the previous designs are computed using QCADesigner and reported in Table 5. As it is clear, the proposed design is the fastest RAM cell with set and reset ability and it consumes less gate count and propagation delay in comparison to state-of-theart structures in [11,18,20]. According to the aforementioned synchronization concepts, the propagation delays of single-stage three and five-input majority gates are equal since both of them must be synchronized in three clocking zones (0.75 clocking cycle). Therefore, the consumed gate count can be a considerable benchmark for latency analysis which is provided in Table 5. This design also surpasses most of previous designs form the occupation area and cell count points of view. 6. Conclusion In this paper, a novel robust five-input majority gate for quantumdot cellular automata was presented. This component can be used to
design QCA circuits using one single layer in contrast to previous designs for five-input majority gate. By utilizing this ability, a new Random Access Memory structure was presented which was controlled by two separate set and reset signals. Simulation results achieved using QCADesigner tool, prove that the proposed RAM cell has a simple and robust structure and surpasses previous designs in terms of input to output latency, complexity and area occupation.
Acknowledgment The authors would like to thank Dr. Peyman Rezvani for his literature contribution and Dr. Esam Alkaldy at Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University for his helpful comments. References [1] R. Compano, L. Molenkamp, and D.J. Paul, Technology roadmap for nanoelectronics, in: Proceedings of the European Commission IST Programme, Future Emerging Technology, 1999. [2] P.D. Tougaw, C.S. Lent, Logical devices implemented using quantum cellular automata, Appl. Phys. 75 (1994) 1818–1824. [3] K. Kim, K. Wu, R. Karri, Towards designing robust QCA architectures in the presence of sneak noise paths, in: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2005, pp 1214–1219. [4] K. Kim, K. Wu, R. Karri, Quantum-dot cellular automata design guideline, IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E89 (A(6)) (2006) 1607–1614. [5] X. Ma, F. Lombardi, Fault tolerant schemes for QCA systems, in: Proceedings of the IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008. [6] K. Navi, S. Sayedsalehi, R. Farazkish, M. Rahimi Azghadi, Five-input majority gate, a new device for quantum-dot cellular automata, J. Comput. Theor. Nanosci. 7 (2010) 1546–1553. [7] K. Navi, R. Farazkish, S. Sayedsalehi, M. Rahimi Azghadi, A new quantum-dot cellular automata full-adder, Microelectron. J. 41 (2010) 820–826 (Elsevier). [8] S. Hashemi, M. Tehrani, K. Navi, An efficient quantum-dot cellular automata full-adder, Sci. Res. Essays 7 (2012) 177–189. [9] V. Vankamamidi, M. Ottavi, F. Lombardi, Two-dimensional schemes for clocking/timing of QCA circuits, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27 (2008) 34–44. [10] A. Shahini Shamsabadi, B. Shahgholi Ghahfarokhi, K. Zamanifar, A. Vafaei, Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study, J. Syst. Archit. 55 (2009) 180–187 (Elsevier). [11] K. Walus, A. Vetteth, G.A. Jullien, V.S. Dimitrov, RAM design using quantumdot cellular automata, in: Technical Proceedings of the Nanotechnology Conference and Trade Show, 2, 2003, pp. 160–163. [12] X. Yang, L. Cai, X. Zhao, Low power dual-edge triggered flip-flop structure in quantum dot cellular automata, Electron. Lett. 46 (2010) 825 (–626). [13] A. Vetteth, K. Walus, V.S. Dimitrov, G.A. Jullien, Quantum-Dot Cellular Automata of Flip-Flops, ATIPS Laboratory 2500 University Drive, N.W., Calgary, Alberta, Canada T2N 1N4, 2003. [14] V. Vankamamidi, M. Ottavi, F. Lombardi, A serial memory by quantum-dot cellular automata (QCA), IEEE Trans. Comput. 57 (2008) 606–618. [15] D. Berzon, T.J. Fountain, A memory design in QCAs using the squares formalism, in: Proceedings of the Great Lakes Symposium, VLSI, 1999, pp. 166–169. [16] V. Vankamamidi, M. Ottavi, F. Lombardi, A line-based parallel memory for QCA implementation, IEEE Trans. Nanotechnol. 4 (2005) 690–698. [17] B. Taskin, B. Hong, Improving line-based QCA memory cell design through dual phase clocking, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16 (12) (2008) 1648–1656. [18] M.A. Dehkordi, A. Shahini Shamsabadi, B. Shahgholi Ghahfarokhi, A. Vafaei, RAM novel cell designs based on inherent capabilities of quantum-dot cellular automata, Microelectron. J. 42 (2011) 701–708 (Elsevier).
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Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata Shaahin Angizi a, Soheil Sarmadi a, Samira Sayedsalehi a, Keivan Navi a,b,n a b
Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G. C., Tehran, Iran Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran
art ic l e i nf o
a b s t r a c t
Article history: Received 8 September 2013 Received in revised form 7 October 2014 Accepted 7 October 2014
Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-à-vis state-of-the-art. & 2014 Elsevier Ltd. All rights reserved.
Keywords: Quantum-dotcellular automata (QCA) Five-input majority gate RAM cell Set and reset ability
1. Introduction In recent years, shrinkage in CMOS circuits' dimensions has faced serious challenges such as leakage current and high power consumption which prevent the exponential trend of decrease in feature size. Studies to find new approaches to substitute conventional CMOS circuits have increased. Quantum-dot cellular automata is one of these approaches for digital logic designs at Nano scale with ultralow power, high performance and least feature size [1,2]. Each QCA cell is composed of four dots and two excess electrons. These electrons can tunnel between dots due to columbic repulsion and diagonally occupy corners of the cell, hence leading to two stable arrangements for QCA cell which are shown in Fig. 1. These two stable states of QCA cell is named cell polarization. Polarizations 1 and þ1 are encoded as logic “0” and “1”, respectively. As it is shown in Fig. 2(a), by placing several QCA cells side by side, a standard QCA wire can be constructed to propagate a logic value. Moreover, a QCA inverter chain can be constructed exploiting 451 rotated QCA cells. This kind of wire propagates the input signal in odd cells and inversion of the input signal in even cells, as shown in
n Corresponding author at: Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G. C., Tehran, Iran. Tel.: þ 98 2129904195; fax: þ98 2122431804. E-mail addresses: [email protected] (S. Angizi), [email protected] (S. Sarmadi), [email protected] (S. Sayedsalehi), [email protected] (K. Navi).
Fig. 2(b). Coplanar wire crossing is achieved using these two types of wires as shown in Fig. 3 [2]. Structural properties of QCA cells within a wire lead to perform computations using a four-phase clock which in turn allow designing parallel QCA circuit employing four clocks [3]. As it is illustrated in Fig. 4, each clocking zone goes through all four phases (Switch, Hold, Release and Relax) each of which has a 901 phase delay from the other. In the switch phase, cell polarization is affected by the juxtaposed cells. Cells keep their polarizations during the hold phase and only can determine the polarization of neighbor cells, which are in the switch phase. In the release and relax phases, cells lose their polarizations and stay un-polarized until the next switch phase [4,9]. The control of data flow is a significant part of designing a robust QCA structure which is gained by increasing cell numbers in the clocking zones [3]. It is also noteworthy that number of cells in each clocking zone must be at least two cells to prevent noise effects on QCA circuit [4,5]. Till date many efforts have been made to implement QCA digital logic circuits; for instance, in [6,7] new structures for five-input majority gate are presented. Also designs for one-bit full adder [7,8], studies on configurable logic gates [22], analysis of fault tolerance and reliability for QCA designs [5,23–27] and flip flops and memory structures [10–20] have been presented. In most of the mentioned works, QCADesigner [28] tool which is an open source simulator has been employed for modeling and verifying QCA structures. To the best of our knowledge, the BNs (Bayesian Networks) model [29] is also used for evaluating and modeling QCA circuits.
http://dx.doi.org/10.1016/j.mejo.2014.10.003 0026-2692/& 2014 Elsevier Ltd. All rights reserved.
Please cite this article as: S. Angizi, et al., Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.10.003i
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The main aim of this study is to implement a new robust RAM cell with set and reset ability based on the new five-input majority gate with least cell count, input to output latency and area occupation. Rest of the paper is organized as follow: Section 2 provides a review on QCA elementary logics and previous structures of RAM cells. New five-input majority gate is addressed in Section 3. In Section 4, the novel robust QCA design and implementation for RAM are proposed based on the five-input majority gate. Section 5 includes simulation results and finally Section 6 concludes this paper.
2. QCA review In this section, the common QCA logics are explained in the order of inverter and majority gate. In addition, the state-of-the-art designs for random access memory cells are reviewed.
Fig. 1. QCA basic cell with two possible polarization states.
Fig. 4. Clocking zones in QCA.
Fig. 2. (a) QCA standard wire and (b) Inverter chain.
Fig. 3. Coplanar wire crossing.
Please cite this article as: S. Angizi, et al., Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.10.003i
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Fig. 5. A QCA inverter.
Fig. 6. Three-input majority gate structure.
Fig. 8. The schematic diagram of conventional RAM cell in [11].
Table 1 Truth table of three-input majority gate. A
B
C
Maj (A, B and C)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 0 1 1 1
Fig. 7. Robust implementation of QCA three-input majority gate with the data flow directions.
2.1. Inverter QCA implementation of an inverter is illustrated in Fig. 5. The input signal is provided from left side, divided into two QCA wires and consequently merged together, therefore the complement of
Fig. 9. The first RAM cell structure presented in [18], (a) schematic diagram (b) QCA implementation.
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Fig. 10. The presented RAM cell structure with set and reset ability in [20], (a) schematic diagram (b) QCA implementation.
input signal is computed at the merging point and propagated to the right side [2]. 2.2. Majority gate Majority gate is one of the basic building blocks in QCA circuits due to its configurability to construct various structures. As it is shown in Fig. 6, a three-input majority gate is consisted of three input cells, one device cell and one output cell. The device cell is polarized to the majority polarization due to electron repulsion between the three input cells [2]. Truth table of three-input majority gate is shown in Table 1. Assume that the inputs are A, B and C, so the logic function of majority gate is: MðA; B; CÞ ¼ AB þ AC þ BC
ð1Þ
By setting the polarization of one input cell (C) to constant value of 1 (“0” in binary), majority gate functionality behaves like a two-input AND gate and the logic function demonstrated as: MðA; B; 0Þ ¼ ABþ ðAÞð0Þ þ ðBÞð0Þ ¼ AB
ð2Þ
Similarly by fixing one of the input cells (C) to polarization of þ1 (“1” in binary), two-input OR gate is achieved, as follows: MðA; B; 1Þ ¼ AB þ ðAÞð1Þ þ ðBÞð1Þ ¼ A þ B
ð3Þ
As mentioned before every QCA circuit is controlled by a clocking mechanism. As it is illustrated in Fig. 7, synchronization of the majority gate is gained when all the input signals are provided to the gate at the identical clocking zone, while middle cells are at the next clocking zone and the output cell is at the clocking zone after that of the middle cells. This rule provides QCA logic circuits with regularity and robustness [3,4]. 2.3. Previous RAM cell structures RAM cell design is one of the most attractive fields of study in QCA. Generally there are two types of RAM cell designs in QCA
Fig. 11. The second RAM cell structure presented in [18], (a) schematic diagram (b) QCA implementation.
which are categorized as loop-based [10–15,18–20] and line-based [16,17] according to the operational manner of the QCA circuits. In the loop-based RAM cell structures, storing mechanism is achieved using a loop that contains all four clocking zones, but line-based RAM cell structures use a QCA line to save previous value of the output. In this part, previous works on designing RAM cell architectures are reviewed. The authors in [11] have made an early effort to present a loopbased QCA Random Access Memory cell. As illustrated in schematic diagram of Fig. 8, the presented architecture is based on D-latch and a loop is used for saving the memory content; in QCA implementation, it also consumes two clocking cycles to transmit the input signal to the output. A QCA random access memory without set and reset ability has been suggested in [18]. As it is shown in Fig. 9(a), this design has a loop-based mechanism and is constructed based on SR-latch. when Select ¼ “1” and Write/Read ¼“0” content of RAM cell is not altered and can be read but when Select ¼ “1” and the Write/Read ¼“1” the new input will be transmitted to the output. In this structure coplanar wire crossing method has been employed, furthermore this design has used only one cell in some of the clocking zones which increases noise sensitivity of the circuit (Fig. 9(b)). First RAM cell architecture with set and reset ability has been presented in [20]. As it illustrated in Fig. 10(a), this design is composed of two
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Fig. 12. Reliability comparison between single-stage three-input, single stage five-input and seven-input majority gates based on PTM calculations in [27].
Fig. 13. (a) The presented structure for single-stage five-input majority gate in [6] and. (b) The presented structure for single-stage five-input majority gate in [7].
Fig. 14. (a) The schematic of a five-input majority gate and (b) QCA layout of proposed single-stage structure for five-input majority gate.
Table 2 Truth table for five-input majority gate based on the summation of the input values. Sum (A, B, C, D and E) Maj (A, B, C, D and E) 0 1 2 3 4 5
0 0 0 1 1 1
2-to-1 multiplexers. One of these multiplexers has been utilized as the D-latch by joining the output signal to the first multiplexer's input. When the select and write/read signals are equaled to “1”,
Fig. 15. (a) The schematic of proposed RAM cell and (b) The QCA layout of proposed RAM cell structure with set and reset ability using the five-input majority gate in Fig. 14(b).
new input data will be inserted in RAM cell, besides read operation has been implemented by setting write/read signal to “0”. It uses single multiplexed wire for set and reset operations, this signal also
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Table 3 Operations of proposed RAM cell structure in Fig. 15. Mode of Type of operation operation
Select Set Reset Write/ Input Previous read output
Output
Normal
Write Write
1 1
0 0
1 1
1 1
1 0
x x
1 0
Normal
Read Read
1 1
0 0
1 1
0 0
x x
0 1
0 1
Set
Set
x
1
1
x
x
x
1
Reset
Reset
x
0
0
x
x
x
0
determines the content of the cell only when the select signal is deactivated by “0” and write/read signal is activated by “1”. The latency of this RAM circuit is 1.75 clock cycle for transmission of the input signal to output cell (Fig. 10(b)). As it is demonstrated in Fig. 11 another design for RAM cell is presented in [18] with the same operation as the first design in Fig. 9. This structure has been based on D-latch with an un-robust three-input majority gate structure, additionally set and reset ability of RAM is lacking in this design.
3. Novel five-input majority gate As mentioned earlier majority gate is an elementary structure in QCA designs, therefore in this section a new robust five-input majority gate is presented. The logic function of five-input majority gate is
Table 4 QCADesigner parameters model.
MðA; B; C; D; EÞ ¼ ABC þ ABD þ ABE þ ACD þ ACE
Parameter
Value
Cell size Number of samples Convergence tolerance Radius of effect Relative permittivity Clock low Clock high Clock shift Clock amplitude factor Layer separation Maximum iterations per sample
18 nm 50,000 0.001000 65.000000 nm 12.900000 3.800000e-023J 9.800000e-022J 0 2.000000 11.500000 100
þ ADE þ BCD þBCE þ BDE þ CDE
ð4Þ
By setting two of the five input cells' polarizations to 1 or þ1, respectively, a three-input AND gate and also a three-input OR gate can be formed. As reliability is an essential issue for characterization of proper functionality of QCA circuits, lots of studies have been done regards to this fact. In [24], the n-input majority gate's limitations to use in computational structures are investigated through a logic-level analysis called PGM (Probabilistic Gate Model). The authors have reported that in a large tree structures of majority gates such as cascaded one-bit full adder cells (which are consisted of multi-level
Fig. 16. (a) Simulation result of presented five-input majority gate in Fig. 14(b) and (b) Simulation result of three-input AND gate.
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Fig. 17. Simulation result of proposed RAM cell structure in Fig. 15(b).
majority gates) or multi-stage multi-input majority gate when the input error rate is not zero, the information will be lost. The authors in [27] have inspected the reliability of multi-input majority gate through PTM calculations (Probabilistic Transfer Matrix) and MATLAB is used to prove that the reliability of a single-stage five-input majority gate is equal to three-input majority gate. As is illustrated in Fig. 12, by increasing the probability of gate failure, the overall reliability of three-input, five-input and seveninput majority gates will be decreased with the same rate. Based on the mentioned concepts in [24,27], in this section we are going to design a single-stage five-input majority gate as the main component of proposed RAM cell. In [6,7] two kinds of single-stage five-input majority gate have been introduced which are shown in Fig. 13(a) and (b). In the first design, the output cell is trapped by input cells therefore preventing access to it in one layer. In the later, input cells are adjacent to each other therefore causing unwanted effect on one another (For example inputs B and D or inputs C and E). One could work around this problem by providing inputs in diagonal direction rather than horizontal or vertical, but that would make the design more faultsusceptible.
Our proposed structure and the schematic of five-input majority gate are demonstrated in Fig. 14. This component can be applied to construct QCA logic circuits in a single layer. Majority gate takes all five input signals in one direction at the first clocking zone. The middle cells, which are in the next clocking zone after the input signals, are polarized based on the majority of inputs' polarizations. The output function is produced in the third clocking zone, at any of the cells in the dotted area, each of them can be connected to the output cell. Table 2 shows the truth table for five-input majority gate based on numerical summation of binary values of the five inputs.
4. The proposed RAM cell structure with set and reset ability The schematic for the proposed RAM cell structure with set and reset ability and QCA implementation of that are indicated in Fig. 15. This design is composed of three three-input majority gates and one five-input majority gate which is presented in Fig. 14(b). The proposed RAM structure is controlled by two separated signals (Set and Reset). In the normal mode (Set ¼ “0” and Reset ¼ “1”) when the select signal is activated (“1”) and write/read signal has
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Table 5 Comparison results of presented RAM cell structures. RAM structure
Set and Reset ability
Coplanar wire crossing
Cell count
Occupation area (lm2)
Gate count
Input to output delay (clocking cycle)
Presented RAM cell in [11] Presented RAM cell in [18] (Fig. 9) Presented RAM cell in [18] (Fig. 11) Presented RAM cell in [20] (Fig. 10) Proposed RAM cell in Fig. 15
No No No Yes Yes
Yes Yes No No No
158 100 63 109 88
0.16 0.11 0.07 0.13 0.08
8 8 6 8 5
2 3 2 1.75 1.5
been set to “1”, input data will be transmitted to the output and consequently write operation will be done. Moreover, read operation has been accomplished by setting the select and write/read signals to “1” and “0”, respectively. In the set mode, content of RAM cell will be set to “1” using the determination of set signal value by “1”. Also the reset mode will be performed by fixing the reset signal to “0” independent of the state of select and write/read signals. The complete operation of the proposed RAM cell is shown in Table 3. As previously mentioned, the output of five-input majority gate can be extracted from any one of the output cells. To achieve synchronization for the presented RAM structure, additional cells have been placed in the input, set and reset wires as shown in Fig. 15(b).
5. Simulation results In this section, simulation results of the proposed designs are verified using QCADesigner tool version 2.0.3 [21] with default parameters shown in Table 4 and also similar outcomes are achieved from both simulation engines (Bistable Approximation and Coherence Vector) of this software. Simulation result of the presented five-input majority gate is illustrated in Fig. 16(a). As it is clear, the majority of input cells' polarizations (A, B, C, D and E) determines the value of output. As mentioned earlier, three-input AND gate and three-input OR gate can be constructed by fixing two arbitrary inputs' polarizations to “ 1” and “ þ1”, respectively. Based on Fig. 16(b), accurate operation of the three-input AND gate is proved. Analysis of the achieved waveforms confirms that all the presented QCA designs work correctly. The simulation result of the proposed RAM structure is shown in Fig. 17, for example in the normal mode when the select and write/read signals are activated by “þ 1” simultaneously, the input signal is transmitted to the output after 1.5 clock cycle, rather than previous RAM designs. In addition, by fixing the set and reset lines to “ 1” reset operation is performed and the result is also evaluated after 1.5 clocking cycle. Fig. 17 shows that the proposed RAM cell works correctly and expected outcomes are obtained. Comparison results between the proposed RAM cell architecture and the previous designs are computed using QCADesigner and reported in Table 5. As it is clear, the proposed design is the fastest RAM cell with set and reset ability and it consumes less gate count and propagation delay in comparison to state-of-theart structures in [11,18,20]. According to the aforementioned synchronization concepts, the propagation delays of single-stage three and five-input majority gates are equal since both of them must be synchronized in three clocking zones (0.75 clocking cycle). Therefore, the consumed gate count can be a considerable benchmark for latency analysis which is provided in Table 5. This design also surpasses most of previous designs form the occupation area and cell count points of view. 6. Conclusion In this paper, a novel robust five-input majority gate for quantumdot cellular automata was presented. This component can be used to
design QCA circuits using one single layer in contrast to previous designs for five-input majority gate. By utilizing this ability, a new Random Access Memory structure was presented which was controlled by two separate set and reset signals. Simulation results achieved using QCADesigner tool, prove that the proposed RAM cell has a simple and robust structure and surpasses previous designs in terms of input to output latency, complexity and area occupation.
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