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Design for environment
CHAPTER
9
Design for Environment: A Printed Circuit Board
Assembly Example SUDARSHAN SIDDHAYE AND PAUL SHENG
University of California, Berkeley
Introduction Integration of factors concerning environmental impact during manufacture, use, and disposition of the product is an emerging issue in design of electronics. The drivers for this in electronics include certification standards such as ISO 14000 and British standard 7750; ecolabeling programs such as Energy Star, Blue Angel, and TCO; increasing internalization of waste mitigation and disposal costs into the product cost; and an increasing need for environmental accountability in global supply networks. One important aspect of product design for environment (DfE) in electronics is the consideration of the environmental impact during the manufacturing stage. In particular, a significant contributor to life-cycle environmental impacts is the fabrication and assembly stages of a printed circuit board. Process models can be used as an analytical tool to develop environmental performance indicators for products. These process models, while modeling the manufacturing waste streams, also implicitly model the product parameters and can be used conveniently for product design optimization. This part of the chapter will introduce the techniques based on process modeling and product optimization that can be applied to printed circuit board assembly design to minimize the environmental impact. Although the focus of this part is on PCB assemblies, after studying these techniques, one easily can apply the principles to other product optimization problems. We first talk briefly about the process models for PC board fabrication. A waste-stream weighting scheme, which is extremely useful for comparing two or more dissimilar waste streams, then is introduced. After that we discuss an optimization algorithm that will seek a balance between the various board design parameters, such as board area, number of layers, and number of boards on a panel, to come up
113
1 14
GREEN ELECTRONICS
with the physical board design with the minimal manufacturing waste per board. The results of a case study will be presented to give the reader an idea of how the technique can be implemented. Last we qualitatively discuss specific issues such as how to incorporate various design constraints, how to extend this analysis to packaging and the semiconductor manufacturing level, and how this piece of analysis fits into the overall life-cycle analysis of a product.
Process Modeling Manufacturing a printed circuit board assembly consists of three parts: (1) semiconductor manufacture, (2) electronic packaging manufacture, and (3) bareboard fabrication and component assembly. Despite a tremendous flexibility in process selection in semiconductor manufacturing, there is somewhat limited room for product optimization to achieve better environmental results. In electronic packaging, one can choose from a wide array of packages. However, in most cases, the functional requirements very quickly narrow the choice to a few types. For bare-board fabrication, about 7% of the material used actually goes into the product and the remaining 93% is emitted as process waste (Allen, 1997). Hence, minimizing the process waste is the most logical way to minimize the environmental impact of a circuit board. The process steps include laminate core fabrication, resist coating, exposure, development, copper etch, resist strip, oxide treatment, lamination, drilling, desmear and copper plating, and solder masking, as shown in Figure 9-1. We can model the thermochemical and thermomechanical behavior of various process steps involved in fabrication to predict the waste streams. As an example, the waste streams from the etching operation can be modeled in terms of the board parameters as (9-1)
mcu = Pcu (1 - Kcu ) Acore tcu
(Mcuc12/Mcu) mcu (mcu2C12/Mcu)
(9-2)
met c = m c u mcu2c12 =
.................................
9}
Inner Layer Circuitization
... .........................................................................................................................................................................................
.................................. .t ~ ............................................................................................................... a ...........................................................................................................................................................
i
iE
..
i =
...................................
Outer Layer Circuitization
FIGURE 9-1
(9-3)
Processsteps in PCB fabrication.
,
/
Design for Environment: A Printed Circuit Board Assembly Example 1 15 160 0.25
140 120
0.2
100 0.15
8O
~_ 0.1
60 c~ 40
P,
20
0.05
Aqueous Particulate
Solid
Wastewater
(a) Solder Paste Waste FIGURE 9 - 2
No Clean
Aqueous Weighted
No Clean Weighted
(b) Dross Waste
Processmodel estimates for reflow and wave solder processes.
where m represents the mass, M represents the molecular weight, A represents the area, t represents the thickness, and K represents the fraction of copper retained on the board after etching, for a particular layer. Similar models can be formulated for component assembly operations such as stenciling, component placement, reflow, wave solder, and board cleaning. A complete set of models can be found in Siddhaye and Sheng (1997) and Worhach and Sheng (1997). These models must be validated using the actual waste-stream data collected at the fabrication site. Figure 9-2 shows the model estimates for reflow and wave soldering processes.
Health Hazard Assessment
It is crucial to be able to compare the raw mass of these waste streams. This can be achieved using some kind of health hazard assessment method like the health hazard scoring system described in Srinivasan, Wu, and Sheng (1995). This system computes a scalar weighting factor called the health hazard score (HHS). This number is calculated for a particular waste stream using its health hazard potential data (carcinogenicity, reactivity, flammability, dermal irritability, inhalation toxicity, oral toxicity, and eye irritation), its phase (solid, solid particulate, liquid, vapor, or aerosol), and the safety practices on site. This number essentially brings two dissimilar waste streams to the same level of hazard for the purpose of mutual comparison. The categorical hazard score, H, is determined based on the information from various sources such as the American Conference of Governmental and Industrial Hygienists (ACGIH) threshold limit value (TLV) data and the Registry of Toxic Effects of Chemical Substances (RTECS) database. To introduce phase effects with chemical hazard subscores, a phase matrix, P, can be constructed to partition the hazard share for each factor among the different physical phases using the Kepner-Tregoe method, where each coefficient is assigned a fractional value from 0 to 1.
1 16 GREEN ELECTRONICS
.I
OralToxicity
"1..........................................
-~Component1..~
"F
--~
'~1~1Inhaled Toxicityr
-~Component2-'*
E
L,03
~
Carcinogenesisp
~-
-,,Component3.-. i
__..~De-l-m----a!i------irjtati~ n _i_~ Eye
9"~Componenti "-P
HHS = H T p ~ E FIGURE 9 - 3
I.
-r "T"
II "l Flammability /_~
i
"1
|-
Reactivity ~
(1) L O r 03 "13 "- N
Health hazard scoring method.
The final factor to consider is site modeling. Since each site in which manufacturing occurs is different in terms of facilities design, equipment, and work practices, these site-specific factors have a significant influence on waste-stream environmental impact. However, these factors are largely qualitative in nature (e.g., wearing protective garments, continuous monitoring of the process). A major challenge, therefore, is to reduce qualitative site information into a quantitative form, which can be evaluated along with chemical hazards and phase. One approach is to construct a set of pairwise evaluations comparing toxicity (oral and inhaled), carcinogenesis, irritation (dermal and eye), reactivity, and flammability using the analytic hierarchy process (AHP), a method that ranks pairwise comparisons between various factors. Successive comparisons set up a matrix. Initially, a subjective set of priorities is elicited from the user regarding the different factors (such as toxicity, reactivity, flammability). These priorities then are placed into an AHP matrix. The schematic of the HHS method is shown in Figure 9-3. Examples of categorical hazard scores are shown in Table 9-1. An example phase matrix is shown in Table 9-2, and an example AHP matrix is shown in Table 9-3.
TABLE 9-1
Score, H i , for "Reactivity"
SCORE
REACTS WITH
9 8 7 6 4-5 1-3 0
Metals, oxidizing agents, acids, bases, moist air, water, etc. Metals and moist air Metals Air (moist) Oxidizing agents Acids or bases No known substance (inert)
Design for Environment: A Printed Circuit Board Assembly Example 1 17 TABLE 9 - 2
An Example Phase Matrix PHASE
HAZARD
SOLID
L I Q U I D AEROSOL V A P O R
SOLIDPARTICLES
Oral toxicity Inhalation toxicity Eye irritation Dermal irritation Carcinogenicity Reactivity Flammability
0.3 0 0 0.2 0 0 0.1
0.4 0 0 0.5 0.3 0.5 0.6
0.3 0.2 0.2 0.3 0.1 0.1 0.1
0 0.5 0.4 0 0.3 0.2 0.1
0 0.3 0.4 0 0.3 0.2 0.1
Based on this matrix, a l-x-7 fate and transport column, vector F, can be calculated. A rank value is determined through the following equation:
R1 =
Xij
(4)
j=l
where Xij are the elements of the k-x-k prioritization matrix, X. Here, k = 7, the number of effects of interest. The elements of F then are determined by a simple normalization: k
F(i) = Ri / Z Ri' i = 1 . . . . k
(5)
i=1
For the matrix in Table 9-3, the F vector is F = [0.01 0.05 0.07 0.43 0.03 0.21 0.20] 7,
(9-6)
The environmental impact index, or health hazard score for the ith waste stream and the jth phase (HHSij) can be calculated as shown in eq. (7), where H i is the l-x-7 vector of the raw score [O, I , E . . . . . F] for the ith waste stream, Pij is the
TABLE 9 - 3
Example AHP Matrix for Site-Specific Prioritization O O
/ X
1
5 10 30 2 20 20
R F I E D C 1/5 1/10 1/30 1/2 1/'20 1/20 1/5 1/5 1 1 1/10 2 1/4 1/3 1 1 1/6 2 2 3 10 6 1 15 1/5 1/8 1/2 1/2 1/15 1 1 1 5 4 1/2 5 1 1 5 3 1/3 8
118
GREEN ELECTRONICS
transpose of the jth column of the phase matrix for the ith waste stream. H iPij is a l-x-7 vector equal to the element-by-element product of Pij and Hi: HHSij = HiPij
*
F
(9-7)
Once derived, an overall HHS index can be written for chemical species with multiphase pathways in terms of the mass fractions of the different phases as HHSi = ~_HHSijMj/~_M j J J
(9-8)
Board Optimization Deciding the Variables of the Problem Once equipped with a set of process models and hazard assessments, we can analyze a particular board design. Keeping the functionality of the board untouched, we can change its physical design and observe the change in the waste-stream generation impact. First, we intuitively decide which factors will have the most significant impact on the waste stream. In circuit boards, we observe from the process models that the number of layers, number of boards tiled on a single panel, and the board area are the key design parameters. We cannot vary the number of pins or components at this point because that will hamper the functionality of the board and our focus is not on devices on the board.
Deriving Interparameter Relationships Changing certain design parameters affects other design parameters. For example, changing the dimensions of the board requires recomputing the copper fraction for every layer. Hence, we need to derive relationships between various parameters. These relationships serve as the equality constraints of the optimization problem. In our board example, we need to derive three formulas:
1. Copper fraction of the signal layers. Balakrishnan and Pecht (1995) derived a relationship for the average length of a copper trace on a board as
~r
Lavg = (A + 1)6(n - 1 ) ~ s
EI+~/2A=/NI(A~+I)]
(9-9)
where A s is the aspect ratio, A r is the routable area of the board, N t is the total number of component pins, and n is the average net size. From this, we can write the copper fraction as gcu-board "- (Zavg Nint/trace)/Ab where N i n t -"
N l (n
- 1)/n
(9-10)
Design for Environment: A Printed Circuit Board Assembly Example 1 19 2. Number of boards per panel. Boards can be arranged on a rectangular panel in two possible orientations, as shown in Figure 9-4. If we denote the length and breadth of the board and panel by L o, W o, Lp, and Wp, respectively, then the number of boards for the two orientations will be as follows. Orientation 1" If G L > W b, then (9-11)
N b = Int (LJWb) Int (Wp/Lb) + Int (LJLb) otherwise N b = Int(Lpl Wb) Int(Wp/Lb) Orientation 2: If G w > Wo, then
(9-12)
N o = Int (Lp/L b) Int (Wp/Wo) + Int (Wp/Lo) otherwise N b = Int (Lp/L b) Int (Wp/Wb)
We must calculate the number of boards per panel using these formulas and choose the orientation that gives the maximum number of boards per panel. This way, more material will go into the product and less into the manufacturing waste. 3. Total number of signal layers. The number of signal layers can be estimated given the routable board area, A r, and the number of "reference components," Nref, using the density approach described in Balakrishnan and Pecht (1995). The number of reference components is equivalent to the number of components when all components are weighted with reference to a 14-pin DIP component as one unit. The categorical functional dependence is given in Table 9-4.
~
~---~---
~
~
~
L
m
11111181111 11111811 (a) Orientation 1
FIGURE 9 - 4
Two panel layouts.
(b) Orientation 2
l/ l/
12:0 GREEN ELECTRONICS TABLE 9--4
Signal Layer Estimation
Ar/Nref (so. IN/14-PIN DIP)
Ns_layers
Above 1.0 0.8-1.0 0.6---0.8 0.42-0.6 0.35-0.42 0.2-0.35 0.0-0.2
2 2 4 6 8 10 10+
OptimizaLion Once we derive the process models and the preceding relationships, we can follow a procedure like the one depicted in Figure 9-5 to optimize the board design parameters. The results of such an optimization are shown in Figure 9-6. The plot shows the weighted mass of the waste streams on per board basis as a function of the board dimensions. From this plot, we can choose the dimensions of the board corresponding to the minimum waste. We also can observe the effect of relaxing a constraint or imposing an additional constraint on the optimization problem. These constraints easily can be imposed or removed during the waste-stream calculation from process models. Several useful conclusions can be drawn from these plots: 9 The minimum waste does not necessarily occur for the smallest or thinnest (i.e., fewest layers) board size. 9 A large variation (more than 100% in the plots shown) in the amount of waste per board occurs as we vary the dimensions and the number of layers of the board. Hence, the scope for waste minimization through design optimization is tremendous. 9 The choice of panels also makes a difference in waste generation. Hence, whenever a variety of panels is available, we must calculate which to choose.
Redesign ~ Ac ...Enclosure Wp I LbrrlinLp, L, bm~ WbminWbmax ' ~ ComputeAr
ns~
Npin Step
FIGURE 9-5
J J ~ I ChooseOptimal ParameterSet I I DevelopWaste/ StreamMap I:~
NoL.l,i'SelectAvailable~~ FindNboardsUSingl.J EstimateWastel I TilingAlgorithmI "[ Streams ii
l'
Board design optimization procedure.
IterateLb, Wb|
IterateLp,Wp
Design for Environment:A Printed Circuit Board Assembly Example 121
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ff
9 . ..
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1.5
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Boardlength(inches)
8
4
9
.
Boicclwidth(inches)
Boil~cllength (inches)
(a) Panel 1 (18" x 24") FIGURE 9 - 6
8
4
Bolmdwidth (inches)
(b) Panel 2 (21"x 27")
Waste mass as a function of board dimensions for two different panel sizes.
Extending the Scope of Analysis A bare board is only one component of an overall printed circuit board assembly. Hence, it is important to perform a similar optimization analysis on every component of the assembly. Also, design variation in one component sometimes necessitates the design variation in another. For example, making the board smaller may allow the use of flip-chip ball grid array components, which may not be as environmentally benign as quad fiat packages because of the potential worker exposure hazard in the solder-bumping process. Therefore, the optimization procedure eventually can be extended to incorporate selection of component packaging. Electronic packaging presents discrete choices of package types. We can formulate the process models for each package type as a function of a functional parameter, such as the pin count. For semiconductor or die manufacturing, environmental issues largely are a function of waste mitigation at the manufacturing process; currently, limited opportunity is available to effect environmental decisions through design changes. However, a change in technology brings about major changes in process steps, chemicals used, and process mechanics and a resulting significant change in process waste. Therefore, process models for semiconductor manufacturing must predict the waste per die as a function of the yield (which is a function of die size and wafer size) and the technology used. So far, we have examined mainly design optimization of a product for minimum process waste. One aspect neglected in this analysis was the amount of material going into the product itself and its eventual fate. Although manufacturing wastes represent the dominant life-cycle impact for printed circuit boards, we cannot neglect the environmental impacts of use and disposition phases of the life cycle for other components of a circuit board or computer. Life-cycle analysis (LCA) examines a product from the time its raw material is mined to the time when the product is disposed back into the environment. So LCA looks at material and energy flows in
122
GREENELECTRONICS
mining, material refinement, manufacturing, use, consumption, and disposal (which includes recycling, reuse, remanufacturing, incineration, deposit in a landfill, etc.) associated with a particular product. While LCA conceptually is straightforward, to implement such analyses requires a great deal of data that often are unavailable or of low quality. LCA is extremely data intensive, and while results can be found for some comparisons, often the data are so poor that little can be learned from them. Furthermore, few have agreed on how the multiple health and environmental impacts of a product's life cycle can be compared to those of another product, making between-product comparisons difficult. LCA is an attempt, ultimately, to draw a quantitative connection between the existence of a product (its manufacture, use, and disposition) and environmental impact. DfE is an attempt to incorporate this information (i.e., connections, analyses) to minimize environmental impacts of design decisions. One can say that, just as more traditional engineering models help designers predict the performance of their design (in terms of speed, weight, energy consumption, and other more standard measures of performance), LCA is a model that predicts for designers the environmental performance of their designs.
References Allen, David. "Life Cycle Assessment and Design for the Environment." Tutorial Notes, IEEE Symposium on Electronics and the Environment, San Francisco, CA, May 1997. Balakrishnan S., and M. Pecht. Placement and Routing of Electronic Modules, pp. 59-96. New York: Marcel Dekker, 1993. Siddhaye, S., and P. Sheng. "Integration of Environmental Factors for Process Modeling of Printed Circuit Board Fabrication," Proceedings of the IEEE International Symposium on Electronics and the Environment, San Francisco, May 1997, pp. 226-233. Srinivasan M., T. Wu, and P. Sheng. "Development of a Scoring Index for the Evaluation of Environmental Factors in Machining Processes: Part I, Formulation." Transactions ofNAMR123 (1995), pp. 115-121. Worhach, P., and P. Sheng. "integration of Environmental Factors for Process Modeling of Printed Circuit Board Assembly." Proceedings of the IEEE International Symposium on Electronics and the Environment, San Francisco, May 1997, pp. 218-225.
9
Design for Environment: A Printed Circuit Board
Assembly Example SUDARSHAN SIDDHAYE AND PAUL SHENG
University of California, Berkeley
Introduction Integration of factors concerning environmental impact during manufacture, use, and disposition of the product is an emerging issue in design of electronics. The drivers for this in electronics include certification standards such as ISO 14000 and British standard 7750; ecolabeling programs such as Energy Star, Blue Angel, and TCO; increasing internalization of waste mitigation and disposal costs into the product cost; and an increasing need for environmental accountability in global supply networks. One important aspect of product design for environment (DfE) in electronics is the consideration of the environmental impact during the manufacturing stage. In particular, a significant contributor to life-cycle environmental impacts is the fabrication and assembly stages of a printed circuit board. Process models can be used as an analytical tool to develop environmental performance indicators for products. These process models, while modeling the manufacturing waste streams, also implicitly model the product parameters and can be used conveniently for product design optimization. This part of the chapter will introduce the techniques based on process modeling and product optimization that can be applied to printed circuit board assembly design to minimize the environmental impact. Although the focus of this part is on PCB assemblies, after studying these techniques, one easily can apply the principles to other product optimization problems. We first talk briefly about the process models for PC board fabrication. A waste-stream weighting scheme, which is extremely useful for comparing two or more dissimilar waste streams, then is introduced. After that we discuss an optimization algorithm that will seek a balance between the various board design parameters, such as board area, number of layers, and number of boards on a panel, to come up
113
1 14
GREEN ELECTRONICS
with the physical board design with the minimal manufacturing waste per board. The results of a case study will be presented to give the reader an idea of how the technique can be implemented. Last we qualitatively discuss specific issues such as how to incorporate various design constraints, how to extend this analysis to packaging and the semiconductor manufacturing level, and how this piece of analysis fits into the overall life-cycle analysis of a product.
Process Modeling Manufacturing a printed circuit board assembly consists of three parts: (1) semiconductor manufacture, (2) electronic packaging manufacture, and (3) bareboard fabrication and component assembly. Despite a tremendous flexibility in process selection in semiconductor manufacturing, there is somewhat limited room for product optimization to achieve better environmental results. In electronic packaging, one can choose from a wide array of packages. However, in most cases, the functional requirements very quickly narrow the choice to a few types. For bare-board fabrication, about 7% of the material used actually goes into the product and the remaining 93% is emitted as process waste (Allen, 1997). Hence, minimizing the process waste is the most logical way to minimize the environmental impact of a circuit board. The process steps include laminate core fabrication, resist coating, exposure, development, copper etch, resist strip, oxide treatment, lamination, drilling, desmear and copper plating, and solder masking, as shown in Figure 9-1. We can model the thermochemical and thermomechanical behavior of various process steps involved in fabrication to predict the waste streams. As an example, the waste streams from the etching operation can be modeled in terms of the board parameters as (9-1)
mcu = Pcu (1 - Kcu ) Acore tcu
(Mcuc12/Mcu) mcu (mcu2C12/Mcu)
(9-2)
met c = m c u mcu2c12 =
.................................
9}
Inner Layer Circuitization
... .........................................................................................................................................................................................
.................................. .t ~ ............................................................................................................... a ...........................................................................................................................................................
i
iE
..
i =
...................................
Outer Layer Circuitization
FIGURE 9-1
(9-3)
Processsteps in PCB fabrication.
,
/
Design for Environment: A Printed Circuit Board Assembly Example 1 15 160 0.25
140 120
0.2
100 0.15
8O
~_ 0.1
60 c~ 40
P,
20
0.05
Aqueous Particulate
Solid
Wastewater
(a) Solder Paste Waste FIGURE 9 - 2
No Clean
Aqueous Weighted
No Clean Weighted
(b) Dross Waste
Processmodel estimates for reflow and wave solder processes.
where m represents the mass, M represents the molecular weight, A represents the area, t represents the thickness, and K represents the fraction of copper retained on the board after etching, for a particular layer. Similar models can be formulated for component assembly operations such as stenciling, component placement, reflow, wave solder, and board cleaning. A complete set of models can be found in Siddhaye and Sheng (1997) and Worhach and Sheng (1997). These models must be validated using the actual waste-stream data collected at the fabrication site. Figure 9-2 shows the model estimates for reflow and wave soldering processes.
Health Hazard Assessment
It is crucial to be able to compare the raw mass of these waste streams. This can be achieved using some kind of health hazard assessment method like the health hazard scoring system described in Srinivasan, Wu, and Sheng (1995). This system computes a scalar weighting factor called the health hazard score (HHS). This number is calculated for a particular waste stream using its health hazard potential data (carcinogenicity, reactivity, flammability, dermal irritability, inhalation toxicity, oral toxicity, and eye irritation), its phase (solid, solid particulate, liquid, vapor, or aerosol), and the safety practices on site. This number essentially brings two dissimilar waste streams to the same level of hazard for the purpose of mutual comparison. The categorical hazard score, H, is determined based on the information from various sources such as the American Conference of Governmental and Industrial Hygienists (ACGIH) threshold limit value (TLV) data and the Registry of Toxic Effects of Chemical Substances (RTECS) database. To introduce phase effects with chemical hazard subscores, a phase matrix, P, can be constructed to partition the hazard share for each factor among the different physical phases using the Kepner-Tregoe method, where each coefficient is assigned a fractional value from 0 to 1.
1 16 GREEN ELECTRONICS
.I
OralToxicity
"1..........................................
-~Component1..~
"F
--~
'~1~1Inhaled Toxicityr
-~Component2-'*
E
L,03
~
Carcinogenesisp
~-
-,,Component3.-. i
__..~De-l-m----a!i------irjtati~ n _i_~ Eye
9"~Componenti "-P
HHS = H T p ~ E FIGURE 9 - 3
I.
-r "T"
II "l Flammability /_~
i
"1
|-
Reactivity ~
(1) L O r 03 "13 "- N
Health hazard scoring method.
The final factor to consider is site modeling. Since each site in which manufacturing occurs is different in terms of facilities design, equipment, and work practices, these site-specific factors have a significant influence on waste-stream environmental impact. However, these factors are largely qualitative in nature (e.g., wearing protective garments, continuous monitoring of the process). A major challenge, therefore, is to reduce qualitative site information into a quantitative form, which can be evaluated along with chemical hazards and phase. One approach is to construct a set of pairwise evaluations comparing toxicity (oral and inhaled), carcinogenesis, irritation (dermal and eye), reactivity, and flammability using the analytic hierarchy process (AHP), a method that ranks pairwise comparisons between various factors. Successive comparisons set up a matrix. Initially, a subjective set of priorities is elicited from the user regarding the different factors (such as toxicity, reactivity, flammability). These priorities then are placed into an AHP matrix. The schematic of the HHS method is shown in Figure 9-3. Examples of categorical hazard scores are shown in Table 9-1. An example phase matrix is shown in Table 9-2, and an example AHP matrix is shown in Table 9-3.
TABLE 9-1
Score, H i , for "Reactivity"
SCORE
REACTS WITH
9 8 7 6 4-5 1-3 0
Metals, oxidizing agents, acids, bases, moist air, water, etc. Metals and moist air Metals Air (moist) Oxidizing agents Acids or bases No known substance (inert)
Design for Environment: A Printed Circuit Board Assembly Example 1 17 TABLE 9 - 2
An Example Phase Matrix PHASE
HAZARD
SOLID
L I Q U I D AEROSOL V A P O R
SOLIDPARTICLES
Oral toxicity Inhalation toxicity Eye irritation Dermal irritation Carcinogenicity Reactivity Flammability
0.3 0 0 0.2 0 0 0.1
0.4 0 0 0.5 0.3 0.5 0.6
0.3 0.2 0.2 0.3 0.1 0.1 0.1
0 0.5 0.4 0 0.3 0.2 0.1
0 0.3 0.4 0 0.3 0.2 0.1
Based on this matrix, a l-x-7 fate and transport column, vector F, can be calculated. A rank value is determined through the following equation:
R1 =
Xij
(4)
j=l
where Xij are the elements of the k-x-k prioritization matrix, X. Here, k = 7, the number of effects of interest. The elements of F then are determined by a simple normalization: k
F(i) = Ri / Z Ri' i = 1 . . . . k
(5)
i=1
For the matrix in Table 9-3, the F vector is F = [0.01 0.05 0.07 0.43 0.03 0.21 0.20] 7,
(9-6)
The environmental impact index, or health hazard score for the ith waste stream and the jth phase (HHSij) can be calculated as shown in eq. (7), where H i is the l-x-7 vector of the raw score [O, I , E . . . . . F] for the ith waste stream, Pij is the
TABLE 9 - 3
Example AHP Matrix for Site-Specific Prioritization O O
/ X
1
5 10 30 2 20 20
R F I E D C 1/5 1/10 1/30 1/2 1/'20 1/20 1/5 1/5 1 1 1/10 2 1/4 1/3 1 1 1/6 2 2 3 10 6 1 15 1/5 1/8 1/2 1/2 1/15 1 1 1 5 4 1/2 5 1 1 5 3 1/3 8
118
GREEN ELECTRONICS
transpose of the jth column of the phase matrix for the ith waste stream. H iPij is a l-x-7 vector equal to the element-by-element product of Pij and Hi: HHSij = HiPij
*
F
(9-7)
Once derived, an overall HHS index can be written for chemical species with multiphase pathways in terms of the mass fractions of the different phases as HHSi = ~_HHSijMj/~_M j J J
(9-8)
Board Optimization Deciding the Variables of the Problem Once equipped with a set of process models and hazard assessments, we can analyze a particular board design. Keeping the functionality of the board untouched, we can change its physical design and observe the change in the waste-stream generation impact. First, we intuitively decide which factors will have the most significant impact on the waste stream. In circuit boards, we observe from the process models that the number of layers, number of boards tiled on a single panel, and the board area are the key design parameters. We cannot vary the number of pins or components at this point because that will hamper the functionality of the board and our focus is not on devices on the board.
Deriving Interparameter Relationships Changing certain design parameters affects other design parameters. For example, changing the dimensions of the board requires recomputing the copper fraction for every layer. Hence, we need to derive relationships between various parameters. These relationships serve as the equality constraints of the optimization problem. In our board example, we need to derive three formulas:
1. Copper fraction of the signal layers. Balakrishnan and Pecht (1995) derived a relationship for the average length of a copper trace on a board as
~r
Lavg = (A + 1)6(n - 1 ) ~ s
EI+~/2A=/NI(A~+I)]
(9-9)
where A s is the aspect ratio, A r is the routable area of the board, N t is the total number of component pins, and n is the average net size. From this, we can write the copper fraction as gcu-board "- (Zavg Nint/trace)/Ab where N i n t -"
N l (n
- 1)/n
(9-10)
Design for Environment: A Printed Circuit Board Assembly Example 1 19 2. Number of boards per panel. Boards can be arranged on a rectangular panel in two possible orientations, as shown in Figure 9-4. If we denote the length and breadth of the board and panel by L o, W o, Lp, and Wp, respectively, then the number of boards for the two orientations will be as follows. Orientation 1" If G L > W b, then (9-11)
N b = Int (LJWb) Int (Wp/Lb) + Int (LJLb) otherwise N b = Int(Lpl Wb) Int(Wp/Lb) Orientation 2: If G w > Wo, then
(9-12)
N o = Int (Lp/L b) Int (Wp/Wo) + Int (Wp/Lo) otherwise N b = Int (Lp/L b) Int (Wp/Wb)
We must calculate the number of boards per panel using these formulas and choose the orientation that gives the maximum number of boards per panel. This way, more material will go into the product and less into the manufacturing waste. 3. Total number of signal layers. The number of signal layers can be estimated given the routable board area, A r, and the number of "reference components," Nref, using the density approach described in Balakrishnan and Pecht (1995). The number of reference components is equivalent to the number of components when all components are weighted with reference to a 14-pin DIP component as one unit. The categorical functional dependence is given in Table 9-4.
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12:0 GREEN ELECTRONICS TABLE 9--4
Signal Layer Estimation
Ar/Nref (so. IN/14-PIN DIP)
Ns_layers
Above 1.0 0.8-1.0 0.6---0.8 0.42-0.6 0.35-0.42 0.2-0.35 0.0-0.2
2 2 4 6 8 10 10+
OptimizaLion Once we derive the process models and the preceding relationships, we can follow a procedure like the one depicted in Figure 9-5 to optimize the board design parameters. The results of such an optimization are shown in Figure 9-6. The plot shows the weighted mass of the waste streams on per board basis as a function of the board dimensions. From this plot, we can choose the dimensions of the board corresponding to the minimum waste. We also can observe the effect of relaxing a constraint or imposing an additional constraint on the optimization problem. These constraints easily can be imposed or removed during the waste-stream calculation from process models. Several useful conclusions can be drawn from these plots: 9 The minimum waste does not necessarily occur for the smallest or thinnest (i.e., fewest layers) board size. 9 A large variation (more than 100% in the plots shown) in the amount of waste per board occurs as we vary the dimensions and the number of layers of the board. Hence, the scope for waste minimization through design optimization is tremendous. 9 The choice of panels also makes a difference in waste generation. Hence, whenever a variety of panels is available, we must calculate which to choose.
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Design for Environment:A Printed Circuit Board Assembly Example 121
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Waste mass as a function of board dimensions for two different panel sizes.
Extending the Scope of Analysis A bare board is only one component of an overall printed circuit board assembly. Hence, it is important to perform a similar optimization analysis on every component of the assembly. Also, design variation in one component sometimes necessitates the design variation in another. For example, making the board smaller may allow the use of flip-chip ball grid array components, which may not be as environmentally benign as quad fiat packages because of the potential worker exposure hazard in the solder-bumping process. Therefore, the optimization procedure eventually can be extended to incorporate selection of component packaging. Electronic packaging presents discrete choices of package types. We can formulate the process models for each package type as a function of a functional parameter, such as the pin count. For semiconductor or die manufacturing, environmental issues largely are a function of waste mitigation at the manufacturing process; currently, limited opportunity is available to effect environmental decisions through design changes. However, a change in technology brings about major changes in process steps, chemicals used, and process mechanics and a resulting significant change in process waste. Therefore, process models for semiconductor manufacturing must predict the waste per die as a function of the yield (which is a function of die size and wafer size) and the technology used. So far, we have examined mainly design optimization of a product for minimum process waste. One aspect neglected in this analysis was the amount of material going into the product itself and its eventual fate. Although manufacturing wastes represent the dominant life-cycle impact for printed circuit boards, we cannot neglect the environmental impacts of use and disposition phases of the life cycle for other components of a circuit board or computer. Life-cycle analysis (LCA) examines a product from the time its raw material is mined to the time when the product is disposed back into the environment. So LCA looks at material and energy flows in
122
GREENELECTRONICS
mining, material refinement, manufacturing, use, consumption, and disposal (which includes recycling, reuse, remanufacturing, incineration, deposit in a landfill, etc.) associated with a particular product. While LCA conceptually is straightforward, to implement such analyses requires a great deal of data that often are unavailable or of low quality. LCA is extremely data intensive, and while results can be found for some comparisons, often the data are so poor that little can be learned from them. Furthermore, few have agreed on how the multiple health and environmental impacts of a product's life cycle can be compared to those of another product, making between-product comparisons difficult. LCA is an attempt, ultimately, to draw a quantitative connection between the existence of a product (its manufacture, use, and disposition) and environmental impact. DfE is an attempt to incorporate this information (i.e., connections, analyses) to minimize environmental impacts of design decisions. One can say that, just as more traditional engineering models help designers predict the performance of their design (in terms of speed, weight, energy consumption, and other more standard measures of performance), LCA is a model that predicts for designers the environmental performance of their designs.
References Allen, David. "Life Cycle Assessment and Design for the Environment." Tutorial Notes, IEEE Symposium on Electronics and the Environment, San Francisco, CA, May 1997. Balakrishnan S., and M. Pecht. Placement and Routing of Electronic Modules, pp. 59-96. New York: Marcel Dekker, 1993. Siddhaye, S., and P. Sheng. "Integration of Environmental Factors for Process Modeling of Printed Circuit Board Fabrication," Proceedings of the IEEE International Symposium on Electronics and the Environment, San Francisco, May 1997, pp. 226-233. Srinivasan M., T. Wu, and P. Sheng. "Development of a Scoring Index for the Evaluation of Environmental Factors in Machining Processes: Part I, Formulation." Transactions ofNAMR123 (1995), pp. 115-121. Worhach, P., and P. Sheng. "integration of Environmental Factors for Process Modeling of Printed Circuit Board Assembly." Proceedings of the IEEE International Symposium on Electronics and the Environment, San Francisco, May 1997, pp. 218-225.