Design methodology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS technology

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International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue

Design methodology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS technology

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Q1

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Mahmood Mohammed a,∗ , Khaldoon Abugharbieh a , Mahmoud Abdelfattah b,1 , Sanad Kawar a a

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b

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Electrical Engineering Department, Princess Sumaya University for Technology, Amman 11941, Jordan Electronics Engineering Department, Princess Sumaya University for Technology, Amman 11941, Jordan

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a r t i c l e

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i n f o

a b s t r a c t

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Article history: Received 30 July 2015 Accepted 11 January 2016

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Keywords: CMOS MOSFET 16 17 Process variations Saturation 18 Subthreshold 19 Temperature compensation 20 21 Q3 Voltage reference circuits 14 15

This work presents a detailed methodology to design a precision voltage reference circuit using MOSFET devices. First, the I–V relations of saturation and subthreshold MOSFETs are presented along with the temperature dependency of these devices. Then, a step-by-step procedure on how to design the main building blocks of voltage reference circuits is discussed. The proper relations between these building blocks are detailed. Moreover, circuit techniques to minimize the impact of process, voltage and temperature (PVT) variations on the voltage reference circuit are introduced. In order to verify the methodological approach, a novel circuit is presented. This new design has been simulated in the state-of-the-art 28 nm CMOS technology using Synopsys Custom Designer and HSPICE CAD tools. It generates a reference voltage of 252 mV with line sensitivity (LS) of 0.64% in a supply voltage range of 0.85–4.1 V. The temperature coefficient (TC) is 218.8 ppm/◦ C, through a temperature range of −15–80 ◦ C. The power supply rejection ratio (PSRR) is −34 dB at 50 Hz and −48.6 dB at 1 MHz. Finally, the power consumption is 395 nW at nominal supply voltage. The process variations coefficient is 0.19%, and the peak-to-peak output noise is 3.08 ␮V/(Hz)1/2 at 10 Hz. © 2016 Elsevier GmbH. All rights reserved.

1. Introduction

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Constant DC voltages, which vary minimally with process, voltage and temperature (PVT) variations, are widely used in analog, digital and mixed-signal circuits [1]. In order to generate such precision DC voltages, voltage reference circuits are used. Because of their critical role in microelectronics, different techniques, technologies and circuit configurations have been applied to achieve such precision voltages. Bandgap voltage reference circuits which use bipolar transistors have been deployed to generate a constant DC voltage as in [2] and [3]. Although lateral PNP devices are implemented in standard CMOS technologies, many problems are associated with this technique. First, BJTs generate a high reference voltage that requires a high supply voltage. This does not meet the low

∗ Corresponding author. Tel.: +962 785397207. E-mail addresses: [email protected] (M. Mohammed), [email protected] (K. Abugharbieh), [email protected] (M. Abdelfattah), [email protected] (S. Kawar). 1 Now with the Electrical and Computer Engineering Department, Purdue University, IN, USA.

voltage constraints for low power applications [4]. Second, they use resistors which are likely to occupy a large area and consume power [5]. Furthermore, as technology nodes scale down, using bipolar devices becomes unsuitable compared to other techniques such as subthreshold MOSFETs [6]. Unlike BJTs, subthreshold MOSFETs can use a low supply voltage for acceptable operation. Thus, they offer an attractive replacement of the BJTs. However, this replacement presents some design challenges. For example, even though the I–V relation of the MOSFETs in the subthreshold region is similar to the I–V relation of the BJTs, there are three important differences between them. First, the subthreshold current is small due to the large drain-to-source resistance in the subthreshold operation, which will allow a large thermal noise to pass through the circuit. Second, MOSFET devices have intrinsic matching problems that cause a larger output voltage variation than BJT devices. Finally, the drain current (ID ) does not have the same temperature coefficient as that of the BJT. Therefore, the temperature coefficient of the MOSFET-based voltage reference circuit will be affected [1]. So, special attention in the design and verification methods is required to obtain an overall acceptable design. Previous works in the literature presented new circuits and design optimization techniques such as [1] and [4–10]. But, a

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Please cite this article in press as: Mohammed M, et al. Design methodology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS technology. Int J Electron Commun (AEÜ) (2016), http://dx.doi.org/10.1016/j.aeue.2016.01.008

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detailed design methodology of voltage reference circuits using MOSFET devices has rarely been addressed. For example, in [1] and [7–9], full methodologies have been presented, but these methodologies discuss the design of voltage reference circuits using BJTs. In [4–6] and [10], the designs are based on MOSFET devices. The principle of operation of the proposed circuits was discussed. But, the design methodology has not been addressed explicitly. Therefore, in [4–6], the principle of operation of the voltage reference circuits based on subthreshold MOSFETs is briefly presented without a discussion regarding the saturation MOSFETs, while in [10] the discussion is based on the strong inversion operation without a discussion regarding the subthreshold operation. This paper provides a full methodological approach to designing and verifying voltage reference circuits using MOSFET devices operating in saturation and subthreshold regions. It provides a step-by-step procedure to show how the design can overcome PVT variations. It also includes a discussion about the assumptions which can be made during the design process. A design and simulation example for a voltage reference circuit using subthreshold MOSFETs is provided. This design example has been verified using the scaled-down 28 nm CMOS technology. Each section contains an illustration from the design example along with the simulation results. This scaleddown technology has been rarely addressed in the literature due to the design challenges associated with these technologies. However, the circuit topology has been briefly presented by authors in [11] using 90 nm CMOS technology. Some changes have been made to the circuit configuration of [11] to make it more robust. Further, a new analysis is presented in this work. Moreover, the performance of voltage reference circuits is characterized by specific parameters. Three of these parameters are considered the most critical, which are the temperature coefficient, the line sensitivity and the power supply rejection ratio. There are other parameters that are considered important according to some applications such as process variation coefficient, power consumption and peak-to-peak output noise [1]. All these parameters are addressed in this paper. Hence, this paper offers a detailed resource for design engineers and universities teaching graduate level microelectronics and analog IC design courses. The design theory is presented in Section 2. The concept of operation and the design verifications are presented in Sections 3 and 4, respectively. Section 5 discusses the design parameters with the simulation results. Section 6 discusses additional design considerations. Finally, Section 7 concludes the work presented in this paper.

where S is the aspect ratio (W/L) of the MOSFET devices,  is the carrier mobility, COX is the gate-oxide capacitance,  is the channel length modulation coefficient, VDS is the drain-to-source voltage, and A is a non-ideal factor known as the subthreshold slope. Finally, VTH is the threshold voltage, and VT is the thermal voltage. By rewriting (1) and (2) in terms of gate-to-source voltage (VGS ), assuming that  = 0 and VDS  4VT , (3) and (4) represent VGS in saturation and subthreshold regions, respectively.



VGS

sat

VGS

sub

= VTH +

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2. Design theory Regardless of circuit techniques and technologies, voltage reference circuits have to offer a specific approach to overcome PVT variations. But, before presenting this approach, the following subsections show how MOSFET transistors can be utilized in voltage reference circuits’ design. 2.1. MOSFET operation in saturation and subthreshold regions

113

The I–V characteristics of the MOSFET transistors operating in saturation and subthreshold regions are given by (1) and (2), respectively.

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I DS

111 112

sat

=

1 SCOX (VGSsat − VTH )2 (1 + VDS ) 2

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 IDS

sub

= SCOX (A − 1)VT2 exp

VGSsub − VTH AVT

= VTH + AVT ln

IDS

sub

SCOX (A − 1)VT2

IC

BJT

= IS exp

V  BE

VT

(5)

123 124 125 126

129 130

131

132 133

134

(6)

As seen in (7), VTH also has a linear relation with absolute temperature. But, VTH decreases as temperature increases, where T0 is a reference temperature [13] and k is the absolute TC of VTH . (7)

On the other hand,  is the only parameter that has a nonlinear relation with T. It is given in (8), where 0 is the mobility at T0 . Parameter m is the mobility temperature exponent. The value of m is about 1.5 in standard CMOS technologies [14]. T0

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Physical characteristics of MOSFET devices generate temperature dependency in the circuits which deploy such devices. VT , VTH and  are parameters that depend on temperature, and they are given by (6), (7) and (8), respectively [12]. VT , in (6), is linearly proportional to absolute temperature (T). KB is the Boltzmann constant, and q is the elementary charge.

 T −m

121

(4)

2.2. Temperature dependency of the MOSFET devices

VTH = VTH (T0 ) − k(T − T0 )

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where IC BJT is the collector current, IS is the saturation current, and VBE is the base-to-emitter voltage of the BJT.

KB T VT = q

119

(3)

Finally, (2) has a similar I–V relation to the BJT assuming that VDS  4VT . The I–V relation of the BJT is given by (5) [7].

 = 0 104

2IDS sat SCOX

118

(8)

Temperature dependency of VT and VTH offer an attractive technique for temperature compensation, since they can neutralize the opposite linear dependency on temperature of each other. However, using  for temperature compensation is usually avoided because of its nonlinear relation with temperature. Due to the presence of VT , VTH and , the output voltages and currents in MOSFET based circuits can be classified into two types: Proportional to absolute temperature (PTAT) voltage or current and complementary to absolute temperature (CTAT) voltage or current. In order to generate an output voltage or current as independent as possible from temperature, both PTAT and CTAT currents and/or voltages have to be generated. Then, they are used to neutralize each other as will be discussed in the following sections.

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(1) 3. Concept of operation



1 − exp

 −V  DS

VT (2)

As seen in Fig. 1, voltage reference circuits consist of three main building blocks. Each one of them is designed with a specific technique to accomplish a certain task. The following subsections briefly

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Load Stage - Produce Sufficient VREF. - Use large W and L MOSFET(s) to avoid process variations.

Single MOSFET Transistor

Combination of MOSFET Transistors

Use Diode-connected technique Produce CTAT

Fig. 1. Main building blocks for voltage reference circuits.

Saturation

Subthreshold

VREF ~ (VTH, 1/µ)

VREF ~ (1/µ, 1/VT , VTH , VT) V

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discuss the design technique along with the task of each building block.

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3.1. The load stage circuit

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The load stage is responsible for generating a sufficient reference voltage (VREF ) that has a specific relation with temperature. CTAT voltage can be generated in the load stage by forcing VREF to be equal to the VGS of a single MOSFET transistor operating in saturation or subthreshold regions. This circuit technique can be seen in [4] and [15] where they have used a subthreshold and a saturation MOSFET, respectively. However, the load stage can also be designed using a combination of multiple MOSFET devices as in [5] and [16]. They have used a combination of subthreshold MOSFETs in the load stage. In [10], saturation MOSFETs were used in the load stage. In both cases, VREF might have a PTAT or a CTAT relation according to the circuit configuration that has been adapted. This temperature dependency of VREF has to be neutralized by the current source circuit as will be shown in the following subsection. Also, the load stage is utilized to minimize process variations by using large W and L transistors. This will be detailed in Section 5.

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3.2. The current source circuit

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As seen in Fig. 1, the current source produces a current (I) that is injected in the load stage. This current has to eliminate the temperature dependency of VREF . If the load stage uses a single MOSFET transistor with a CTAT relation, then the current source has to produce a PTAT current that depends on V 2T and . For example, if a single saturation transistor is used in the load stage, then V 2T will counteract the temperature dependency of VTH , while carrier mobilities of the load and the current source circuits will cancel each other. Thus, subthreshold MOSFETs must be used in the current source circuit to produce a dependency on V 2T . But, if the load stage uses a combination of MOSFET devices, then the current source should provide an opposite relation with temperature. Since VREF uses the current (I), the current source should offer a good technique to separate VREF from the variations in the supply voltage. In order to insure that (I) and VREF do not vary with supply voltage, high impedance transistors should be used in each branch to ensure that the variation in supply voltage will not affect the current flowing in these branches. Moreover, the diode connected structure of the MOSFET transistors can be used to force drainto-source voltages to be equal to gate-to-source voltages. Thus, drain-to-source voltages are almost constant for small variations in the supply voltage. Furthermore, some designs have deployed amplifiers in the current source circuit, as in [5], [6] and [16], to ensure similar voltage variations on different parts of the circuit. These concepts will be clarified with more discussions in the design parameters section.

will cancel V

Considered as Bias Voltage Circuit Produce PTAT or CTAT depending on circuit configuration Sat. Only Depends on (µ, VTH) CTAT

I ~ (µ, VT2) PTAT

Sub. Only Sat. and Sub. Depends on Depends on (µ, VTH , VT) (µ, VTH , VT) PTAT CTAT

PTAT CTAT

PTAT: (µ, VT2) CTAT: (1/µ, 1/VT2)

Opposite temperature relation

Current Source (Reference) - Produce current (I) that has opposite temperature relation with load stage. - Must use subthreshold MOSFET to produce VT2. - For good LS: 1. Use long channel transistors. 2. Use diode-connected structure. 3. Use amplifier circuit.

Start-up Circuit - Ensure bias in the desired state. - Disabled automatically after reaching the required value

Fig. 2. Flowchart of the design methodology.

3.3. The start-up circuit

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The start-up circuit is used to ensure bias in the desired state upon power up. After the reference voltage reaches the required value, the start-up circuit is disabled automatically [8]. Finally, the flowchart of Fig. 2 illustrates the concept of operation of voltage reference circuits using MOSFET transistors. Also, it shows the relation between the main building blocks of voltage reference circuits. 4. Design verifications

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A new voltage reference circuit is presented in Fig. 3. This circuit will be used as a design example throughout this paper. It will solidify concepts shown in Figs. 1 and 2. This circuit produces a constant reference voltage based on the difference between transistors’ voltages and through a temperature compensation technique that utilizes the subthreshold operation of the MOSFETs. All transistors in the circuit are operating in the subthreshold region, except for M1 which operates in the triode region as a resistor. To ensure strong triode operation of M1, it has been chosen to have a low VTH (LVTH ). The circuit consists of three stages: the current generator stage, the load stage and the startup stage. The detailed principle of operation is presented in the following subsections. 4.1. The PTAT current generator stage

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The current IM6 , which is produced by this stage, can be derived by writing the KVL loop through the transistors M1–M5 as in (9). VDS1 = VGS4 + VGS5 − VGS2 − VGS3

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(9)

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Fig. 3. The proposed CMOS voltage reference circuit.

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Substituting (4) in (9) for transistors M2–M5, VDS1 can be written as in (10).

246

VDS1 = VTH4 + A4 VT ln

244

IM8

248

− A2 VT ln

249

− A3 VT ln

IM6 =

S44COX (A4 − 1)VT2

+ VTH5 + A5 VT ln

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IM8

S22COX (A2 − 1)VT2

VDS1 1 (X2 + 1) RM1

(16)

By substituting (13) and (15) into (16), the current IM6 can be written as in (17).

− VTH2

S55C OX (A5 − 1)VT2 IM1

However, IM1 = (X2 + 1)IM6 . Therefore, IM6 can be written as in (16).

IM6 =

− VTH3

1 S1 COX (VA −VTH1 )AVT ln (X2 + 1)

S S 2 3 S4 S5

×

X1 X1 (X2 +1)X2



(17)

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Let Bi = Si i Cox (A − 1), where i denotes to the transistors. Also, assume that A is equal for all transistors as will be shown in Section 6. Thus, (10) can be re-arranged as in (11).

expression (VA − VTH1 ) is equal to The (VA − VTH (T0 )1 + k1 (T − T0 )). However, with the condition: VA − VTH (T0 )1  k1 (T − T0 ), VA − VTH1 can be replaced by k1 T. In this case, the current (IM6 ) produced by the current generator stage is given by (18). This current has a PTAT relation and it will be injected in the load stage to counter the CTAT temperature dependency of VREF .

254

VDS1 = {VTH4 + VTH5 − VTH2 − VTH3 }

IM6 =

IM7

(10)

S33COX (A3 − 1)VT2

250 251 252



+ AVT ln

255

IM8 B4VT2

×

IM8 B5VT2

×

B2VT2 IM1

 2

×

B3VT IM7

(11)

1 S1 COX (k1 T )AVT ln (X2 + 1)

S S 2 3 S4 S5

×

X1 X1 (X2 + 1)X2



(18)

4.2. The load stage

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274

275 276

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286

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By simplifying (11) and assuming that VTH ,  and COX are identical for all transistors, VDS1 can be written as in (12). VDS1 = AVT ln

S S 2 3

IM8 IM8 × S4 S5 IM1 IM7



(12)

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To simplify (12), the current IM8 , IM7 and IM1 can be written in terms of IM6 . This is done by assuming the ratios of the current mirror transistors are: (X1 = S8 /S6 ) and (X2 = S7 /S6 ). Therefore, IM8 = X1 IM6 and IM7 = X2 IM6 , while IM1 = IM7 + IM6 . So, IM1 = (X2 + 1)IM6 . Thus, (12) can be re-written as in (13).

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VDS1 = AVT ln

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S S 2 3 S4 S5

×

X1 X1 (X2 + 1)X2

IM1

RM1 ∼ =

1 S1COX (VA − VTH1 )

VREF = VGS10 = VTH10 + AVT ln



(13)

Since M1 is operating in the triode region, IM1 can be found as in (14). Assuming VDS1 is very small, the resistance of M1 (RM1 ) is given by (15), where VA is the gate-to-source voltage of M1 as seen in Fig. 3. VDS1 = RM1

This stage is constructed by the subthreshold diode-connected transistor, M10, and the current mirror transistor M9. Eq. (19) represents VREF . In order to have a temperature compensated reference voltage, the current IM6 in (18) is injected in the load stage through the current mirror M6 and M9. The ratio between M6 and M9 is X3 , where X3 = S9 /S6 . So, IM9 = X3 IM6 . Eq. (20) represents VREF after substituting (18) into (19), where IM9 = X3 IM6 and N is a constant given by (21).

(14) (15)

VREF = VTH10 + AVT ln N=

 NT 

IM9 S10 COX (A − 1)VT2

VT

X3 S1 Ak1 ln (X2 + 1)S10 (A − 1)

S S 2 3 S4 S5

×

X1 X1 (X2 + 1)X2

dVREF AKB = −k10 + ln q dT

KB

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(19)

295

(20)

296

(21)

297



For zero TC, the condition dVREF /dT = 0 must be satisfied. Eq. (22) represents the derivative of VREF with respect to T.

 qN 

287

(22)

As can be seen from (22), by proper sizing (W/L) of the transistors M1–M10, the condition for zero TC can be satisfied. All other

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Table 1 Transistor sizes of the CMOS voltage reference circuit of Fig. 3.

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305 306 307 308 309 310 311 312 313 314 315

Transistor

Size (W/L)

Multipliers factor (m)

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10

(1/1.5 ␮m) (0.5/0.1 ␮m) (1/0.05 ␮m) (0.145/0.1 ␮m) (0.5/0.15 ␮m) (0.1/3.5 ␮m) (3.5/0.06 ␮m) (0.1/3.5 ␮m) (0.1/3.5 ␮m) (3.5/0.2 ␮m)

1 50 1 40 1 1 10 1 1 2

parameters are constant. This proper sizing of the transistors is done as follows:

Fig. 4. The startup effect on building up the PTAT current (IM6 ) and VREF as the VDD turns on.

– Evaluate the value of N for zero TC from (22). – The parameter N has been found by applying k10 = 1 mV/◦ C (as will be evaluated in Section 6), while A has been assumed to be 1.5. This value of A is the average value since 1 < A < 2 as will be seen in Section 6. Also, KB = 1.3806 × 10−23 and q = 1.602 × 10−19 . Thus, N = 0.193. – Then, this value of N is used in (21) to find the sizes of the transistors S1 –S10 . Again, A = 1.5 while k1 = 1.8 mV/◦ C. But, these values of the transistors should be optimized to overcome PVT variations as much as possible. Section 5 discusses the optimization of these transistors.

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By solving (21) and (22) for zero TC, the sizes of the most critical transistors are evaluated and then optimized as in Table 1.

Fig. 5. The average reference voltage of 252 mV with line sensitivity of 0.64% at T = 25 ◦ C.

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4.3. The start-up stage

according to process, voltage and temperature parameters. Therefore, this will give more insight on how to use the design parameters to evaluate the performance of voltage reference circuits. Synopsys 28 nm iPDK CMOS technology is used to design and simulate the voltage reference circuit of Fig. 3.

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In self-biased voltage reference circuits, one of two possible operating states exists upon power up. The first state is the desirable state where the current is flowing through the branches of the circuit. However, an undesirable state might exist if the transistors carry a zero current as the circuit starts to operate [9]. Thus, the transistors may remain off. To avoid the undesirable state, a startup circuit has been used to ensure bias in the desired state. For the circuit of Fig. 3, the transistor Ms7, with a size of (0.15/0.04) ␮m, offers a path for the current in the PTAT current generator stage as VDD turns on. Then, it turns off as the reference voltage reaches the required value and disconnects the start-up circuit. The transistors Ms2, Ms5 and Ms6 are used to minimize the current flowing in the start-up circuit. They have an aspect ratio of (0.1/3.5) ␮m. Moreover, the transistors Ms1, Ms3 and Ms4 are used to drive Ms7 as the circuit starts to operate. Fig. 4 illustrates the effect of the startup circuit upon power up. It shows how the PTAT current IM6 and the output voltage (VREF ) are ramped up while the supply voltage is swept from 0 V to the nominal voltage 0.9 V. Also, it shows how VGS of the transistor MS7 (VGS MS7 ) is ramped down as VDD increases. As seen from this figure, the current starts at 0 A and then it is changed to about 13 nA as the supply voltage reaches the nominal value. This means that the state of the zero current upon power up has been avoided. Similarly, VREF reaches the required value as the supply voltage reaches the nominal value, where VREF has an initial value of 0 V.

344

5. Design parameters

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As mentioned previously, the performance of reference voltage circuits is characterized by specific parameters. The following subsections discuss these parameters. Furthermore, the behavior of the voltage reference circuit of Fig. 3 is verified with simulation results

5.1. Voltage parameters

5.1.1. Line sensitivity The line sensitivity specifies the variation of the output reference voltage (VREF T(nominal) ) with respect to the input supply voltage range (VDD ), as seen in (23). VREF

T(nominal)

VDD

 V 

350 351 352 353

354

The average output reference voltage, the line sensitivity, the supply voltage range and the PSRR are voltage parameters used to measure the performance of voltage reference circuits.

LS =

349

V

[or × 100 (%)]

(23)

In order to reduce the line sensitivity, high impedance transistors are used in each branch to ensure that the variation in VDD will not affect the current flowing in each branch. In the circuit of Fig. 3, the high impedance transistors M6–M9 should be as long as possible to ensure minimum line sensitivity. Also, the diodeconnected transistors M2, M4, M5 and M10 keep VDS of these transistors almost constant for small variations of supply voltage. Fig. 5 shows the VREF voltage generated with a supply voltage range of 0.85–4.1 V. The average reference voltage is 252 mV. The line sensitivity is 0.64%, where VREF is 21 mV over a supply voltage range of 3.25 V. To maintain the high impedance in the transistors M6–M9, the minimum supply voltage is 0.85 V. These high impedance transistors maintain a proper operation, where the supply voltage variations do not significantly change the value of the line sensitivity due to the existence of these transistors.

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Fig. 7. Variation in VREF with respect to temperature for different supply voltages, TC = 218.8 ppm/◦ C.

Fig. 6. The PSRR at VDD nominal = 0.9 V and T = 25 ◦ C.

378 379 380 381 382 383

384 385 386 387 388 389 390

391

5.3. Process variation parameters

Although the simulation result in Fig. 5 is still valid for a supply voltage of 4.1 V, the transistor M1 starts to operate in the saturation region after a supply voltage of 1 V. Practically, at supply voltage higher than 1 V, the gate oxide will likely break down due to unacceptable vertical electrical field and the FET will not operate properly. 5.1.2. Power supply rejection ratio PSRR is a common parameter used to evaluate voltage reference circuits. It specifies the ability of these circuits to reject supply noise and other undesired signals at certain frequencies. Eq. (24) represents the AC relation of PSRR. Fig. 6 illustrates the PSRR for a wide frequency range. The PSRR is −34 dB at 50 Hz and −48.6 dB at 1 MHz. VREF AC PSRR = 20 log (dB) VIN AC

(24)

393

In order to enhance the PSRR, an RC filter has been used. The values of R and C are chosen to be 1 M and 1 pf, respectively.

394

5.2. Temperature parameters

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399

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The temperature coefficient, given by (25), relates the reference voltage drift over the range of operating temperatures. TC requirements vary from few ppm/◦ C to hundreds of ppm/◦ C according to different applications [1]. TC =

VREF

Vin(nominal)

T × VREF

6

◦

× 10 (ppm/ C)

(25)

Vin(nominal)

where VREF Vin (nominal) is the variation of the reference voltage within the temperature range [Tmin , Tmax ] and T = Tmax − Tmin . Fig. 7 shows the variation of the reference voltages within a temperature range of −15 ◦ C–80 ◦ C for the circuit in Fig. 3. The average TC is 218.8 ppm/◦ C for different supply voltages. The TC at the nominal supply voltage of 0.9 V is almost 200 ppm/ ◦ C, which indicates that the robustness of the design is observed around the nominal supply voltage. Optimizing the TC does not only depend on the temperature compensation technique which has been discussed in Section 4, but also on minimizing the variations of VREF due to supply voltage variations. The temperature compensation technique does not achieve a complete zero TC because of the approximations made to derive the relation for zero TC. Thus, the enhancement done on the voltage parameters is reflected on enhancing the TC.

The source of process variations is the random changes in the physical characteristics of the circuit components during the fabrication process. These changes of the physical characteristics can be classified into two types: die-to-die (D2D) and within-die (WID) variations. D2D variations affect all elements in the circuit fairly equally, and they are produced because of two reasons [17]. First, each die is exposed to different fabrication conditions. The variations in the fabrication conditions are random between dice but deterministic within each die [18]. For example, processing temperatures, equipment properties, wafer polishing and wafer placement are considered sources for D2D variations. Second, the existence of variations within each die is also a source for D2D variations. For example, resist thickness across the wafer is a source for D2D variations. On the other hand, WID variations affect different elements in the circuit differently. They are produced by the mismatch between the elements of the circuit in terms of their widths (W) and lengths (L). The source of this mismatch is either random or systematic source [17]. The aberrations in the stepper lens are an example of systematic within-die variations, whereas the difference in placement of dopant atoms in the device channel region is an example of the random variations [19]. In order to test the performance of the voltage reference circuit under process variations, worst case conditions are applied to the circuit. If the circuit operates correctly on these worst case conditions, then it will operate correctly within the typical conditions. Fig. 8a shows the behavior of the voltage reference circuit under worst case scenarios (i.e. process corners: FF, FS, SF and SS). The terms Fast NMOS or Fast PMOS and Slow NMOS or Slow PMOS are related to the condition of three internal parameters of the transistor. These parameters are: the effective length (Leff ), VTH and the oxide thickness (tox). If the transistor is operating with the shortest Leff , the lowest VTH and the thinnest tox, it is said that the transistor is under Fast operation. However, if the transistor is operating with the longest Leff , the highest VTH and the thickest tox, it is said that the transistors is under slow operation. Also, the terms Fast and Slow are related to other external parameters which are the supply voltage and temperature. If the supply voltage is high and the temperature is low, then it is a Fast corner. The opposite is a Slow corner [20]. Fig. 8a gives a robust indication that the behavior of the circuit under process variations is stable. The LS remains almost constant except for the FS corner, where it increases after VDD = 3.5 V. Since the nominal VDD = 0.9 V, the increase in LS of the FS corner after VDD = 3.5 V is not critical. Also, the change in the value of VREF for the process corners is due to the change in Leff , VTH and tox.

Please cite this article in press as: Mohammed M, et al. Design methodology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS technology. Int J Electron Commun (AEÜ) (2016), http://dx.doi.org/10.1016/j.aeue.2016.01.008

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Fig. 9. The PTAT currents IM6 and IM9 at different supply voltages.

5.4. Additional design parameters

494

Besides what has been discussed in the previous subsections, additional design parameters are important to measure the performance of voltage reference circuits. They also affect the previous voltage, temperature and process parameters.

Fig. 8. Simulation results of the process variation parameters. (a) Performance of VREF at different process corners at T = 25 ◦ C; (b) MC distribution of VREF over 400 samples at T = 25 ◦ C.

462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493

Nevertheless, the worst case conditions are associated with two problems. First, they might assume unrealistic scenarios about the variations of the PVT conditions, which affect the assessment made on the behavior of the circuit under such conditions. Second, they provide little quantitative information about the behavior of the circuit, which limits the capability to enhance its performance. Therefore, statistical methods, such as Monte Carlo (MC) simulations, are also used to test the performance in addition to the worst case methods. Worst case conditions are still used for quick simulations, where the statistical methods require complex techniques and methodologies [18]. Fig. 8b, which is the MC simulation of the voltage reference circuit, shows the distribution of VREF over 400 samples including WID and D2D variations. The average value of VREF () is 0.2518 V, whereas the standard deviation () is 0.000478 V. So, the coefficient of variation (/) is less than 0.19%. The simulator HSPICE provides a random mismatch between W and L of each transistor differently. A 5% Gaussian distribution mismatch in terms of W and L is used. Also, a 5% random mismatch is used on the value of VTH for each transistor. In general, statistical methods are used to evaluate the PVT variations. But, voltage and temperature variations can be evaluated by other methods with defined parameters such as line sensitivity and temperature coefficients. However, this is not the case for the process variations where statistical methods are the most accurate techniques to evaluate them. As mentioned earlier, WID variations are produced according to the mismatches between transistors in terms of their widths and lengths. This mismatch is inversely proportional to (WL)1/2 [8]. As a consequence, such variations can be reduced by setting the channel length and width of the load stage transistors to large values, until mismatch is negligible compared to the effect of process variations [5]. Therefore, the current mirror transistor, M9, has an aspect ratio of (0.1/3.5) ␮m while M10 has an aspect ratio of (3.5/0.2 ␮m) × 2.

5.4.1. Supply current (IQ ) It is the current required for voltage reference circuits to operate properly at the steady-state conditions. This current is also known as the quiescent current. It is desirable to have small IQ for high power efficiency and accurate output reference voltage [1]. Fig. 9 shows the current (I) drawn from the supply voltage at the load stage in a temperature range of −15–80 ◦ C for different supply voltages. It is observed that I increases with temperature. This means that I has a PTAT relation as expected from (18). The power consumption for the voltage reference circuit of Fig. 3, which is evaluated at nominal VDD = 0.9 V, is 395 nW. 5.4.2. Output noise The random motion of the charge carriers is the noise source in electronic circuits. Hence, because of the random nature of the noise, it is predicted via statistical analysis. Thermal noise and flicker noise are the dominant types of noise in CMOS circuits. They are given by (26) and (27) respectively [8].

496 497 498

499 500 501 502 503 504 505 506 507 508 509 510

511 512 513 514 515 516

4KB T gm

(26)

517

Kn COX WLf

(27)

518

V¯ n2 thermal = V¯ n2 flicker =

495

where KB is the Boltzmann constant,  is a process parameter that is approximately 2/3 [8]. Further, gm is the transconductance of the MOSFET transistors. Kn is another process parameter with an order of 10−25 V2 F, while f is the frequency. Usually, the output noise in voltage reference circuits is determined graphically as the peak-to-peak voltage in a bandwidth range of 0.1–10 Hz. Thus, it is a frequency dependent parameter. Fig. 10 represents the unfiltered output noise for the circuit of Fig. 3. It has an amplitude of 3.08 ␮V/(Hz)1/2 at 10 Hz. As seen in (26) and (27), thermal and flicker noises have an inversely proportional relation with W and L. So, to reduce the output noise, long channel transistors are used. Other sources of noise also exist such as the shot noise. But, these sources are usually ignored because of their small contribution compared to thermal and flicker noises [1].

Please cite this article in press as: Mohammed M, et al. Design methodology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS technology. Int J Electron Commun (AEÜ) (2016), http://dx.doi.org/10.1016/j.aeue.2016.01.008

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Fig. 10. Output noise in the frequency range of 0.1–10 Hz. Fig. 11. ID vs. VGS of M1 and M10 at different operating temperatures. 533

6. Design considerations

541

Some of the MOSFET constant parameters depend on the fabrication process. Since designers have no control on these parameters, assumptions are usually made while deriving the equation for VREF. So, theoretical calculations for different parameters, in voltage reference circuits, will approximate but not fully reflect the exact behavior of these circuits. In the following subsections, the main process dependent parameters that affect the performance of voltage reference circuits are presented.

542

6.1. Subthreshold slope factor (A)

534 535 536 537 538 539 540

543 544 545 546 547

548

549 550 551 552

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It is a non-ideal factor for MOSFET transistors operating in the subthreshold region, and it is given by (28). It depends on the depletion capacitance (CD ) and the gate-oxide capacitance (COX ). CD is always smaller than or equal to COX , which means that 1 ≤ A ≤ 2 [1]. CD A=1+ COX

(28)

During the derivation of VREF in (20), A has been assumed to be equal for M2–M5. This is acceptable if the sizes of the transistors are equal or close to each other, where CD depends on W and L of the transistors, as seen in (29) [21], and COX is almost constant. A0 εs CD = Wdep

(29)

558

where A0 is the cross section area of the junction, εs is the electrical permittivity of the silicon and Wdep is width of the depletion region. For the voltage reference circuit of Fig. 3, S2 ≈ S4 and S3 ≈ S5 . This makes the assumption acceptable while deriving the equation of VREF .

559

6.2. Channel length modulation coefficient ()

554 555 556 557

566

 represents the relative variation in the channel length (L) of MOSFET transistors for a given increment in VDS [17]. To avoid the effect of , long channel transistors should be used. Thus, in saturation region, large size transistors should be used to ensure that the assumption of  = 0 is acceptable while deriving (3). But, for subthreshold operation, VDS should be larger than 4VT so the current in (2) becomes as independent as possible form  [15].

567

6.3. Absolute temperature coefficient of VTH (k)

560 561 562 563 564 565

568 569 570 571

k is a coefficient which describes the change in VTH with respect to 1 ◦ C change in temperature. Eq. (7) shows the relation between VTH and T, where k is the absolute temperature coefficient of VTH . As seen in Fig. 11, the value of k changes with respect to temperature

and W/L of the transistors. Even though the value of k varies from 1 mV/◦ C to 4 mV/◦ C, it can be assumed constant [12]. But, for proper temperature compensation, the value of k should be evaluated for each transistor. Many theoretical works have been done to evaluate k as in [12] and [22]. However, k can be also evaluated graphically from Fig. 11. For example, VTH of M10 is 0.53 V at T = 0 ◦ C and 0.555 V at T = 25 ◦ C. So, by substituting these values in (7) and generating two equations with two unknowns, k10 can be found to be 1 mV/◦ C. Similarly, the value of k1 for M1 has been found to be 1.8 mV/◦ C.

7. Conclusion This work presented a methodological approach for designing voltage reference circuits using MOSFET devices. The theoretical operation of the MOSFET was discussed based on how they are utilized for voltage reference circuits. The full procedure of the design is introduced by analyzing the building blocks and defining the relation between them. In order to verify this methodology and discuss the relevant parameters, a new design circuit was presented and simulated using 28 nm CMOS technology. This circuit generates a reference voltage of 252 mV with a line sensitivity of 0.64% in a supply voltage range of 0.85–4.1 V. The temperature coefficient is 218.8 ppm/◦ C, through a temperature range of −15–80 ◦ C. The power supply rejection ratio is −34 dB at 50 Hz and −48.6 dB at 1 MHz. The power consumption is 395 nW at nominal supply voltage. The peak-to-peak output noise is 3.08 ␮V/(Hz)1/2 at 10 Hz and the process variations coefficient is 0.19%. Furthermore, the assumptions, which are usually made while designing voltage reference circuits, were discussed to ensure proper operation of these circuits. Table 2 summarizes the previous works in terms of the main parameters discussed in this paper. As seen in Table 2, in terms of results, this work deploys the 28 nm CMOS technology which has been rarely used in literature. Also, the proposed circuit shows a significant reduction in the value of the process variation coefficient compared to other works. Moreover, the supply voltage range (VDD ) in the proposed circuit outperforms the supply voltage range in other works. In terms of circuit configuration, the proposed circuit uses triode MOSFET instead of using resistors as in [10] and [14]. Resistors are often avoided, because they occupy a large area. In [5], a major improvement in the line sensitivity and the PSRR has been observed, where an additional current mirror has been used. However, this increases the number of transistors in each branch. Therefore, the minimum supply voltage increased to be 1.4 V. This minimum supply voltage is unacceptable for scaleddown technologies.

Please cite this article in press as: Mohammed M, et al. Design methodology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS technology. Int J Electron Commun (AEÜ) (2016), http://dx.doi.org/10.1016/j.aeue.2016.01.008

572 573 574 575 576 577 578 579 580

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582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616

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Sat

180 0.634 0.85–2.5 0.024 19.4 −20 to 80 −88.2 3.4% – 547 nW 28 0.225 0.9–3.25 0.5 138.5 −20 to 150 −62 – – – 180 0.436 0.8–3 2.81 ±38.2 −20 to 100 −47 – – – 130 0.781 1.2–2.3 0.34 48 0 to 100 −51.4 0.38% – 9.72 ␮W 180 0.221 0.9–2.5 2 – −20 to 120 – – – 3.3 ␮W

[28]

130 0.178 0.5–3 0.033 231 −20 to 80 −53 0.56% 16 243 pW

[27]

180 0.263 0.45–2 0.44 142 0 to 125 −45 3.9% 2.3 11.6 nW

Subthreshold Sat

350 0.847 1.8–4.5 0.185 11.8 0 to 130 −72 – – 36 ␮W Technology (nm) VREF (V) VDD (V) LS (%/V) TC (ppm/◦ C) Temp. range (◦ C) PSRR @ 50 Hz (dB) Process variation coefficient (/) Output noise (␮V/(Hz)1/2 ) Power consumption @ max VDD

MOSFET type

350 0.74 1.4–3 0.002 7 −20 to 80 −45 0.87% – 0.3 ␮W

1200 0.295 1.2 VREF ± 10 mV 119 −25 to 125 −40 @ 5 kHz – – 4.32 ␮W

[26] [14] [5] [4] [10]

Fabricated Type

Table 2

Q12 Comparison between different designs of the CMOS voltage reference circuits using MOSFET devices.

350 0.67 0.9–4 0.27 10 0 to 80 −47 3.1% – 0.22 ␮W

Sat. Sub.

Simulated

[15]

[24]

[23]

Subthreshold

90 0.115 0.25–1.2 3.1 518 −20 to 80 −31 – – –

[25]

180 0.22 0.6–2 0.51 135 −25 to 125 −51 @ 1 MHz – 0.27 19 nW

28 0.252 0.85–4.1 0.64 218.8 −15 to 80 −34 0.19% 3.08 6.39 ␮W

This work

[16]

Sat. Sub.

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9

Unlike [16], the proposed circuit uses subthreshold and triode MOSFETs only, while [16] uses saturation transistors. So, for proper approximation analysis, the effect of the channel length modulation coefficient () of the saturation MOSFETs has been assumed to be negligible. Since the lengths of these transistors were chosen to be large enough, this assumption is considered acceptable. But, this may not be the case when the scaled-down technologies are used. The lengths of the transistors, in the scaled-down technologies, are designed to be relatively small. Hence, the effect of  may not be assumed negligible. The minimum supply voltage has been improved significantly in [4], where it reached 0.45 V. However, the design in [4] has deployed MOSFETs with different threshold voltages (i.e. low threshold voltage (LVTH ) and high threshold voltage (HVTH ) MOSFETs) in order to get a reasonable value for VREF . This limits their application, where a sufficient difference between LVTH and HVTH is necessary to get a sufficient VREF . Finally, numerous limitations regarding the performance have been observed while designing the voltage reference circuit of Fig. 3. For example, the assumptions that have been made while deriving (20) prevented the circuit from achieving near zero TC. Furthermore, the MOSFET model is governed by about 40 parameters [1]. This made the limitations even more pronounced. Yet, the results obtained from the proposed circuit are promising. Therefore, this circuit can be used in many applications where a stable voltage reference is needed. Furthermore, the circuit can be improved by adding programmability options that generate multi stable reference voltages. Such programmable capability can be useful in analog circuits where multi-level reference voltages are required.

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Acknowledgement

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Authors would like to thank Dr. Feras Al-Dirini for his valuable comments and discussions. Also, the authors would like to thank Eng. Hazem Marar and Eng. Salah Al-Mousa for their technical support.

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