Design of a high performance DIP-like pin array package for logic devices

scribed. The pertinent parameters are first defined and their sensitivities are derived so that the proper design trade-offs can ultimately be made. From this procedure, a set of rules is generated for driving a computer-aided design (CAD) system. Finally there is a discussion of design optimisation and circuit and package effects on machine performance. Design of a high performance DIP-like pin array package for logic devices. CECIL W. DEISCH, JOHN F. G O G A L and JOHN W. STAFFORD IEEE Trans. Components Hybrids Mfg Technol. Chmt6 (3), 305 (September 1983) Pin array packages offer package sizes which are much smaller than their dual in-line package (DIP) equivalent. Pin array packages are also through hole mountable. A pin array package is described which is DIP-like in that it is rectangular but the input/output (I/O) pins do not fully populate its base. The package is a co-fired tungsten metalised mulfilayer ceramic package with 104 I/Os yet is only 1.16in wide by 1.88in long. Dual tier wire bond ledge s are used to minimise wire bond lengths which also enhances electrical performance. This package is used in systems where many leads must switch simultaneously on to a heavily loaded bus. Such switching may result in considerable electrical noise. To meet noise requirements the package had to have the lowest possible ground impedance. This was accomplished by dedicating 20 per cent of all pins to power and ground and by strategically positioning them on the package. Power and ground planes were also placed within the layered ceramic package to further lower the ac ground impedance. Finally, these planes were arranged to provide nearly 1000 pF high-quality built-in filter capacitance. Noise is further reduced by minimising crosstalk within the package. The presence of ground planes helps lower interlead crosstalk by factors of three to ten. Resistance and capacitance loading of the signal paths are designed to be acceptably low. A simple packaging change allows all the signal nets to be electrically probed from the top of the package. The package, depending upon its configuration and use of heat sinks, also has the capability of handling high power integrated circuits (ICs). A data-base for IC mask making N.N. KUNDU, S.N. GUPTA, A.K. BAGCHI, D.R. NAGPAL, A.V. RAMANI and W.S. KHOKLE Microelectron. J. 14 (5), 43 (1983). Photomasks are very important in the manufacturing of integrated circuits and should be of very high quality with low defect density and very good edge definition. A photomask fabrication process involves various photoimaging, processing, measurement and quality control steps. The complexity and sophistication of the process requires that either the operator be extremely skilled and conversant with all the process steps involved as per requirements of a given set of masks or that the entire process be computerised. CEERI has developed a data base for the complete processing of emulsion and hard surface masks. This has been generated using the IMAGE 1000 software ofa HP

1003 computer system and describes each process step such as, exposing with pattern generator, image repeater and contact printer. Several mask processing procedures, critical dimension measurements and quality control steps have also been included. In fact, depending on the job requirements, the operator can simply enter all parameters through the query system of the data base, which can be conveniently listed either on hard copy or on a terminal for setting up various work stations and process steps of mask making. In this paper, this data base has been described with its advantages and practical usage. IC wafer fab economics and lithography equipment selection: the inextricable link PETER DISESSA Solid. St. TechnoL 155 (December 1983) IC wafer fab economic and performance gains during the remainder of this decade will continue to be principally derived from the premiere IC production equipment decision; that is, the selection of the optimal lithography tool, or tool mix. The major treatment herein addresses the economic relationships when evaluating such a decision. The discussion illustrates the lithography functional and operational factors as they impact wafer manufacturing costs and what logically must be viewed as the ultimate IC wafer fab productivity criterion: fab cost/good die out. To accomplish this, a step-by-step overview is introduced that can serve as a guideline and aid in providing a clearer approach to a complex and confusing decision-making process.

Testing Electron-beam recrystailised polysilicon

on silicon

dioxide

TOMOYASU INQUE and KENJI SHIBATA Microelectron. J. 14 (6), 74 (1983) Lateral seeded recrystallisation of silicon layer evaporated in an ultra high vacuum has been studied experimentally by scanning electron beam annealing. Silicon layers on the seed area were grown epitaxially during the evaporation. Silicor/layers above 1 p.m thickness were successfully recrystallised, resulting in reproducible lateral epitaxy of -- 40 p.m in length. A pseudo-line shaped electron beam formed by high frequency oscillation enabled dimensional enlargement of lateral epitaxial growth to 120 p.m in length and 150/.tin in width. Crystalline properties were characterised by Rutherford backscattering measurement and electron channelling pattern observation. Automated measurement system for the investigation of surface state distribution

T.E. PRICE and L.C. KWAN Microelectron. Reliab. 23 (3), 555 (1983) A semiautomatic measurement system has been developed for studying the interface properties of MOS structures. Software has been developed to control the measurement sequence and to analyse the data. The results which are presented in tabulated and graphical form would be of value for quality control purposes and for detailed investigations of the properties of the oxidesemicondutor interface.

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