subtractor in quantum-dot cellular automata

Accepted Manuscript Design of a novel reversible structure for full adder/subtractor in quantum-dot cellular automata Fereshteh Salimzadeh, Saeed Rasouli Heikalabad PII:

S0921-4526(18)30823-8

DOI:

https://doi.org/10.1016/j.physb.2018.12.028

Reference:

PHYSB 311237

To appear in:

Physica B: Physics of Condensed Matter

Received Date: 20 September 2017 Revised Date:

16 December 2018

Accepted Date: 17 December 2018

Please cite this article as: F. Salimzadeh, S.R. Heikalabad, Design of a novel reversible structure for full adder/subtractor in quantum-dot cellular automata, Physica B: Physics of Condensed Matter (2019), doi: https://doi.org/10.1016/j.physb.2018.12.028. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

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Fereshteh Salimzadeh, Saeed Rasouli Heikalabad*

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Design of a novel Reversible structure for Adder/Subtractor in Quantum-dot Cellular Automata

Department of Computer Engineering, Tabriz Branch, Islamic Azad University, Tabriz, Iran

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*Corresponding author, [email protected]

Abstract

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Complementary Metal Oxide Semiconductor (CMOS) technology uses voltage levels for binary computation, whereas Quantum Dot-Cellular Automata (QCA) uses free electron location in the QCA cell for logic evaluation. This technology suggests very low power consumption, high speed and very dense structure for performing any logical circuit. Reversible logic is best mechanism with low power and high speed in circuit designing. Reversible gates have N input and N output lines that input lines mapped with output lines one by one. In this paper, a novel design of Reversible Full adder/subtractor with minimum number of cells has been proposed. QCADesigner software has been used to simulate the proposed design.

Introduction

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Keywords: Quantum-dot Cellular Automata (QCA); Reversible Full adder/subtractor

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Complementary Metal Oxide Semiconductor (CMOS) technology is used to get the basic physical limits in order to research Nano-scale for the future generation integrated circuits [1]. As successor to CMOS, researchers have proposed a mechanism in which computations are performed by quantum dots. This technology was first introduced in 1994 and was called quantum-dot cellular automata [2]. This technology suggests very low power consumption, high speed and very dense structure for performing any logical circuit. The Very Large Scale Integration (VLSI) circuit is one of the great features of Quantum Dot-Cellular Automata (QCA) in comparison with the current CMOS-based technology [3]. So, QCA cell performs the key role in QCA technology and it is used for logic computation and interconnection, i.e. Data transmission [4]. In QCA, unlike today’s computers that transmit information through electrical current from one point to another, the transmission of polarization status causes data transfer. In this technology, binary values are created by different specific electron arrangements at the quantum dots in a cell. Quantum cells are in the form of a square, and quantum dots are located in the corners of the square. How polarization of quantum cells represents zero and one binary. The cell is polarized by enabling the Columbic interaction with neighboring cells [5].

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Reversible circuits are circuits that do not lose information and reversible computation in a system can be performed only when the system comprises of reversible gates. These circuits can generate unique output vector from each input vector, and vice versa, that is, there is a one-toone mapping between input and output vectors [6-8].

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The most prominent application of reversible logic lies in quantum computers [9]. A quantum computer will be viewed as a quantum network (or a family of quantum networks) composed of quantum logic gates; each gate performing an elementary unitary operation on one, two or more two–state quantum systems called qubits. Each qubit represents an elementary unit of information; corresponding to the classical bit values 0 and 1 [10].

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In this paper, a novel design of Reversible Full adder/subtractor with minimum number of cells has been proposed in quantum-dot cellular automata technology. The proposed reversible Full adder/subtractor have 3 three-input XOR gates and one three-input majority gate. The proposed gate has four input lines and four output lines. The design is simulated with QCADesigner, and the evaluation results show that the proposed structure has significant improvement in area, cell numbers and delay compared to the previous structures. Briefly, the objectives of this paper are as follows: Proposing a reversible Full adder/subtractor to reduce the number of cells and the consumption area. Comparing the presented design with other state-of-the art designs in terms of cell counts, complexity, and the consumed area.

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The background of QCA-based technology and related work of QCA-based architecture are presented in Section 2. The performance of a new QCA-based circuit, the applied designs, and the various functions are presented in Section 3. Section 4 expresses the simulation results which are obtained from QCA Designer to verify the functionality of the design. Finally, the future work and conclusion are presented in Section 5.

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2. Background and Related Work

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This section covers background materials and related work in order to understand the structure of QCA and its role in reversible Full adder/subtractor designs.

2.1 Fundamentals of QCA

Some basic concepts of QCA technology, including logic gates, interconnections, and clocking are presented in this section. A QCA cell, a square-shape structure, has four quantum-dots positioned at the four corners and two electrons which are allowed to move between the dots. Due to Columbic repulsion, the electrons occupy the dots located at the diagonally opposed corners. This feature leads to two stables and possible configurations, which are represented as cell polarizations P = −1 (for “0”) and P = +1 (for “1”). Fig. 1 shows a QCA cell and the two possible polarizations [11, 19-24].

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Quantum Dot Electron 90-degree

18nm 18nm

P = +1

P=-1

Fig.1 QCA cell and two possible polarizations

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45-degree

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Two basic structures in QCA are inverter and majority gate. By placing QCA cells side-by-side, a QCA standard wire can be constructed [12, 25-29]. Fig. 2(a) shows a QCA-based wire that is designed based on 90-degree or 45-degree cells. Fig. 2(b) shows that the first inverter splits the input into two paths and it combines them which produces the opposed polarization [11]. Also, Fig. 2(b) shows that the second inverter produces the opposed polarization by placing a cell diagonally in the output path. Input Cell

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Output Cell

Fig.2 QCA wire types [11]

Output Cell

Input Cell Output Cell

Fig.3 QCA inverter gates [11]

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In conventional QCA designs, three-input and five-input majority gates play a significant role in general circuit architecture [9]. Three-input majority gate is the key logical gate in the QCAbased designs which calculates the Boolean expression. Fig. 4 shows layout of a three-input majority gate, in which output cell M acts as logical function Eq. 1 [13]. Also the two-input OR and AND gates are constructed respectively by fixing one of the inputs of the majority gate to polarization “+1” and “-1”. M (A,B,C)= AB+BC+AC

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AB

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Fig. 4(a), 3-input MG, (b) 2-input OR gate, (c) 2-input AND gate [13]

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Wire crossing is a significant issue in QCA circuit design. Three different crossing methods have been proposed, so far: Single-layer crossing: this kind of QCA crossing is implemented in one layer using both 45- degree and 90-degree QCA cells, each one dedicated to one side of a crossing. These different cells can pass over the crossing without any significant effect on each other.

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Multi-layer crossing: unlike the previous one, multi-layer method uses only 45-degree cells or 90- degree ones. One wire of the crossing is transferred to another layer and after passing through the crossing, the wire is returned to the original layer.

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Logical crossing: although this crossing is implemented on a single layer, only one type of QCA cell is required. The effects of wires of a crossing on each other are neutralized utilizing different phases in each wire. Cells with switch and hold phases are allowed to cross over the cells with release and relax phases, respectively [14].

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2.2. Related work

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Bahar et al [15] have proposed a new structure for full-subtractor. Fig 5 shows the structure of full-subtractor introduced by Bahar et al [15]. A three-input exclusive-OR gate and a three-input majority gate have been used in this structure. This structure is not reversible and only operates as full-subtractor.

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Fig. 5(a) Schematic block diagram, and (b) QCA cellular design of full-subtractor [15]

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Mosleh [16] have proposed a structure for full adder/subtractor. Fig. 6 shows the structure of full adder/subtractor introduced in this work. First, a new QCA gate with three inputs and two outputs called MV32 has been proposed in this work. This gate operates on the basis of cell interactions. Then, full adder and full adder/subtractor structures are proposed by applying different formulations, which are based on the introduced gate. Finally, a novel QCA full adder/subtractor is presented with the synergy of the proposed QCA full-adder and fullsubtractor structures as well as a proposed optimal single layer 2:1 QCA multiplexer.

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Fig. 6(a) Schematic block diagram, and (b) QCA cellular design of full adder/subtractor [16]

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Taherkhani and et al [17] have proposed a structure for reversible full adder/subtractor. Fig. 7 shows the structure of reversible full adder/subtractor introduced in this work. First, a new reversible gate with three inputs and three outputs called RQG has been proposed in this work. Then, by using an RQG and two Feynman reversible gates (FG), a novel reversible full adder/subtractor circuit with four inputs and four outputs is proposed. This design is implemented in a single layer.

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Fig.7 (a) Schematic block diagram, and (b) QCA cellular design of reversible full adder/subtractor [17]

3. Proposed reversible full adder/subtractor

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A novel design for reversible full adder/subtractor in quantum-dot cellular automata technology is presented in this section. The structure of the proposed design has four inputs and four outputs. The truth table of reversible full adder/subtractor is shown in Table 1. The input lines are Sel, A, B and Ci/Bi, and the output lines are S/D, Co/Bo, G1 and G2. Sel input is the selector and decides which of addition or subtraction operations is to be performed. A, B and Ci/Bi are the main inputs of full adder/subtractor. Inputs A and B are the values that must be summed or subtracted. Ci/Bi is considered as “Carry In” or “Borrow In” when addition or subtraction is performed, respectively. It represents the carry when Sel=0 and borrow when Sel=1. In other words, adding operation is done when Sel=0 and subtraction operation is done when Sel=1. S/D and Co/Bo are the main outputs of full adder/subtractor. Outputs G1 and G2 are garbage outputs that have been added to the output list for reversible feature. S/D is the result of addition or subtraction and Co/Bo is the value of “Carry Out” or “Borrow Out”. S/D and Co/Bo are the outputs of full adder when Sel=0 and the outputs of full subtractor when Sel=1. In the case of garbage outputs, the simplicity principle of proposed design is considered. The equations of outputs are obtained as Eq. 2 to Eq. 5. Fig. 8 shows the design of proposed structure for reversible full adder/subtractor. Three three-input XOR gates and one three-input majority gate are used to implement the proposed structure. We use the structure of three-input XOR gate presented in [18].

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Table 1.Truth table of proposed reversible full adder/subtractor

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Sel A B Ci/Bi S/D Co/Bo G1 G2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1

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S/D = Sel′ A′ B′ Ci/Bi + Sel′ A′ B Ci/Bi′ + Sel′ A B′ Ci/Bi′ + Sel′ A B Ci/Bi + Sel A′ B′ Ci/Bi + Sel A′ B Ci/Bi′ + Sel A B′ Ci/Bi′ + Sel A B Ci/Bi

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S/D = Sel′ [A′ B′ Ci/Bi + A′ B Ci/Bi′ + A B′ Ci/Bi′ + A B Ci/Bi] + Sel [A′ B′ Ci/Bi + A′ B Ci/Bi′ + A B′ Ci/Bi′ + A B Ci/Bi] S/D = Sel′ [Ci/Bi′ (A B′ + A′ B) + Ci/Bi (A′ B′ + A B)] + Sel [Ci/Bi′ (A B′ + A′ B) + Ci/Bi (A′ B′ + A B)]

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S/D = A ⊕ B ⊕ Ci/Bi

Co/Bo = Sel′ A′ B Ci/Bi + Sel′ A B′ Ci/Bi + Sel′ A B Ci/Bi′ + Sel′ A B Ci/Bi + Sel A′ B′ Ci/Bi + Sel A′ B Ci/Bi′ + Sel A′ B Ci/Bi + Sel A B Ci/Bi

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Co/Bo = Sel′ [A B + A Ci/Bi + B Ci/Bi] + Sel [A′ B + A′ Ci/Bi + B Ci/Bi] Co/Bo = Sel′ [Maj (A, B, Ci/Bi)] + Sel [Maj (A′, B, Ci/Bi)] Co/Bo = Maj [(Sel ⊕ A), B, Ci/Bi] (4)

G1 = Sel ⊕ B

G2 = A

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(b) Fig. 8 (a) Schematic block diagram, and (b) QCA cellular design of proposed reversible full adder/subtractor

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4. Simulation results and comparison

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The simulation engine is applied to coherence vector in QCADesigner tool through the use of the parameters. The values of these parameters are default values in QCADesigner. Coherence vector engine of QCADesigner tool version 2.0.3 is employed with the parameters summarized in Table 2. Table2. QCADesigner parameters for Coherence vector engine

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Value 18 nm *18 nm 1.0e-015 1.0e-016 80.0 12.90 9.80e-022 3.80e-023 2.0 11.5 0.0e+000 7.000000e-011

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Parameter Value Cell size Relaxation time Time step Radius of effect Relative permittivity Clock high Clock low Clock amplitude factor Layer separation Clock shift Total simulation time

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In this section, we described the simulation result of proposed structures. Fig. 9 shows the simulation result of the proposed reversible full adder/subtractor. As it can be seen, the operation result of proposed structure is same as the truth table.

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We compare proposed structure with previous work [17]. The implementation results are given in Table 3 contains the number of cells, occupied area and latency. The implementation results show that proposed design is better than previous one [17]. Proposed design has achieved 71% improvement in cell count. Also, proposed structure has a 71% optimization in occupied area. In addition, number of clock zones reduced 57% compared to the presented structure in [17].

Table3. Implementation results of reversible full adder/subtractor

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# of Crosswiring 6 2

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Fig. 9 Simulation result of proposed structure

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5. Conclusion

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In this paper, we proposed a novel design for reversible full adder/subtractor. QCADesigner was used to implement and simulate the proposed structure. Physical investigation confirmed the simulation results. The results show that the proposed structure provides 71% improvement in cell count and occupied area. It also provides 57% improvements in clock zones.

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