- Email: [email protected]
Design of acceleration grid power supply for CFETR negative-ion-based neutral beam injection prototype
Fusion Engineering and Design 146 (2019) 2592–2597
Contents lists available at ScienceDirect
Fusion Engineering and Design journal homepage: www.elsevier.com/locate/fusengdes
Design of acceleration grid power supply for CFETR negative-ion-based neutral beam injection prototype
T
⁎
Xueliang Zhanga, Ming Zhanga, Shaoxiang Maa, , Shu Wangb, Dongyu Wanga, Xiao Maa, Lan Zhoua, Shu Yanga, Kexun Yua, Yuan Pana a International Joint Research Laboratory of Magnetic Confinement Fusion and Plasma Physics, State Key Laboratory of Advanced Electromagnetic Engineering and Technology, School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan, 430074, China b State Grid Hubei Electric Power Company Limited Economic Research Institute, Wuhan, 430074, China
A R T I C LE I N FO
A B S T R A C T
Keywords: CFETR N-NBI Neutral point clamped inverter Step-up transformer HV diode rectifier
The planned China Fusion Engineering Test Reactor (CFETR) needs one or more Negative-ion-based Neutral Beam Injectors (N-NBIs) with a beam energy of 500 keV to heat plasma and drive current. In order to prepare for CFETR, a prototype of CFETR N-NBI is being designed to accelerate hydrogen negative ions up to 200 keV with a beam current as high as 20 A for 3600 s at max, and an Acceleration Grid Power Supply (AGPS) rated at −200 kV/25 A is needed. A single stage inverter-type high voltage power supply is adopted as AGPS of the NNBI prototype. The AGPS mainly includes a 12 pulse rectifier based on thyristor, a dual-dc-link system rated at 5 kV, a three phase three level neutral point clamped dc/ac inverter based on injection enhanced gate transistor, a three-phase set-up transformer, a high voltage uncontrolled rectifier based on avalanche diode and a high voltage R-C dc-filter. This paper describes the design of the AGPS for CFETR N-NBI prototype, focusing on the inverter, the step-up transformer and the HV diode rectifier.
1. Introduction China Fusion Engineering Test Reactor (CFETR) is a planned new fusion facility with a major mission to demonstrate full cycle of tritium self-sustained with tritium breeding ratio ≥1.2 [1]. In order to heat plasma and drive current, CFETR needs one or more Negative-ion-based Neutral Beam Injectors (N-NBIs) with a beam energy of 500 keV. However, China has no experience in developing high-power N-NBI. Aiming at laying the foundation for the development of CFETR N-NBI, a prototype of CFETR N-NBI is being designed to accelerate hydrogen negative ions up to 200 keV with a beam current as high as 20 A for 3600 s. The N-NBI prototype needs an Acceleration Grid Power Supply (AGPS) rated at −200 kV/25 A. As one of the core components of N-NBI, the AGPS is direct power source of the N-NBI’s beam energy and characterized by rapid dynamic response, highly accurate output voltage, low output voltage ripple, and fast switch-off speed when breakdown or beam-off occurs between acceleration grids [2]. Nowadays, the High Voltage Power Supply (HVPS) based on Pulse Step Modulation (PSM) method is the mainstream scheme of HVPS used in fusion engineering field [3]. The AGPS of the CFETR N-NBI prototype can also adopt PSM power supply. However, with respect to JT-60U N-NBI AGPS [4] and ITER N-NBI ⁎
AGPS [2], the CFETR N-NBI prototype adopts a single stage invertertype HVPS as its AGPS with the purpose of accumulating experience for CFETR. The proposed scheme of the AGPS is shown in Fig. 1, the AGPS consists mainly of phase-controlled rectifier (12 pulse), three phase three level Neutral Point Clamped (NPC) inverter, step-up transformer, high voltage uncontrolled rectifier and high voltage R-C filter. Table 1 lists the major design parameters of the AGPS for the CFETR N-NBI prototype. In order to meet the requirements, the AGPS control system will gather the output voltage and dc-link voltage for a feedback control. For the purpose of limiting the output dc current component from dc/ac inverter to less than 1% of the rated output current of the inverter, a direct feedback control of this component is realized by measured primary phase current of the transformer. What’s more, a distributed core snubber is foreseen to limit the short-circuit current and surge energy when breakdown occurs between acceleration grids. As the inverter, the step-up transformer and the HV diode rectifier used in the AGPS are characterized by complex structure and strict technical requirements, they need to be carefully designed and manufactured. The design of the AGPS is underway, and some components have already started the prototype verification phase. Although the circuit topology of this AGPS is similar to the topology of the AGPS for
Corresponding author. E-mail address: [email protected] (S. Ma).
https://doi.org/10.1016/j.fusengdes.2019.04.050 Received 2 October 2018; Received in revised form 11 April 2019; Accepted 11 April 2019 Available online 01 May 2019 0920-3796/ © 2019 Elsevier B.V. All rights reserved.
Fusion Engineering and Design 146 (2019) 2592–2597
X. Zhang, et al.
Fig. 1. The AGPS scheme for CFETR N-NBI prototype.
tests have been carried out on IEGT using double pulse method [8]. The comparison between soft-switching and hard-switching test results showed that the inverter of the AGPS can adopt hard-switching mode when the circuit's stray inductance can be restricted at a low level.
Table 1 Major design parameters of the AGPS. Specifications
Values
Input
Voltage Frequency Range Stability Ripple Rise time Settling time 25 A@max Rated value Ripple Frequency Dc current component Connection type Turn tatio Usc 3600 s @max < 100 μs < 10 J
Output voltage
Output current Dc-link voltage Inverter Step-up transformer
Pulse length Switch-off time Fault energy
10 kV 50 Hz 0 kV˜-200 kV < ± 2% < 10% (< ± 5%) < 80ms < 50ms
2.1. Structural design One phase leg of the inverter is shown in Fig.2, where Cdc is dc-link capacitors, Cc is clamp capacitor, Rp is clamp resistance, Dp1,2 are clamp diodes, S1-4 are IEGTs and D1-4 are antiparallel diodes of IEGTs. Cdc is 12 m F and contains 12 self-healing metallized film capacitors with 2 series 6 parallel. Rp is 20kΩ and can prevent the clamp failure of Dp1,2. The IEGTs adopt ST1500GXH24 [9] produced by Toshiba and clamp diodes adopt ABB’s 5SDF20L4520 [10]. The IEGT drivers use SK08110 customized by Firstack with RG(on) = 5.1Ω and RG(off) = 10Ω. The goal of the structural design is to realize the low-inductance structure of the power circuit. The three-level NPC structure contains two different commutation loops as illustrated in Fig. 9(a). The loop 1 contains two devices while the loop 2 involves four devices. The inductances Lσ1 and Lσ2 are used to represent the concentrated stray inductances of the two loops, including the inductance in the semiconductor stacks (Lstack1, Lstack2), the Equivalent Series Inductance (ESL) of the dc-link capacitors (LCdc), and the inductance in bus bar (Lbus1, Lbus2). As the values of Lstack1, Lstack2 and LCdc are relatively fixed, the key to low-inductance design is to reduce Lbus1 and Lbus2. The connection between the dc-link capacitors and the inverter legs adopts a carefully designed laminated busbar, which is shown in Fig. 3. Table 2 summarizes the inductance values of each part of the two loops. The values of Lstack1, Lstack2, Lbus1 and Lbus2 are obtained using the Finite Element Method (FEM) with ANSYS/Q3D, while the value of LCdc is provided by capacitor supplier. So, Lσ1 is 371.6 nH and Lσ2 is 363.8 nH.
5000 V < ± 5% 150 Hz < 1% △/Y 1:23.5 ≈14%
ITER N-NBI, their engineering designs are quite different, especially for inverters. ITER uses IGCT-based inverters, while the AGPS discussed in this paper adopts IEGT-based inverter. Due to adequate testing and careful design, the IEGT-based inverter designed in this paper has the advantages of simple structure, fast dynamic response and high reliability. Based on the design showed in this paper, the AGPS for CFETR NNBI prototype can be reliably switched off within 100 μs when breakdown or beam-off occurs between acceleration grids, which is very meaningful for protecting the N-NBI prototype and the AGPS itself. The following three parts will briefly introduce the design of the inverter, the step-up transformer and the HV diode rectifier. 2. Design of the TPTL NPC inverter The AGPS is a single stage inverter-type HVPS, both the voltage regulation and high-speed switching are controlled by the inverter at low voltage side [5]. It can be said that the performance of the AGPS is determined by the inverter to a great extent. Referring to the medium voltage converters widely used in industrial fields, the TPTL NPC scheme is chosen as the inverter scheme. For the purpose of making full use of the dc-link voltage and reducing the switching frequency of the inverter, the inverter is regulated by asymmetrical duty cycle modulation [6] at 150 Hz. The inverter frequency is mainly determined by the difficulty of manufacturing the step-up transformer, and the efficiency and dynamic characteristics of the AGPS are taken into account. After comparing the high-power semiconductor devices on the market [7], Injection Enhanced Gate Transistor (IEGT) is used as the main switch of the inverter. In order to lay foundation for the inverter design, a lot of
Fig. 2. One phase leg of the inverter. 2593
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Table 3 Thermal resistance of the devices in Fig. 9(a). Thermal Impedance
IEGT
Rth
S1-4 D1-4
Diode
Dp1,2
Ri(K/kW) τi(s) Ri(K/kW) τi(s) Ri(K/kW) τi(s)
i=1
i=2
i=3
i=4
4.157 0.6663 10.634 0.7117 3.708 0.5336
1.858 0.0615 4.797 0.0632 1.426 0.0670
0.642 0.0055 1.622 0.0056 0.686 0.0074
0.220 0.0005 0.556 0.0005 0.176 0.0011
Fig. 3. Laminated busbar of the inverter. Table 2 Inductance values of each part. Lstack1
Lstack2
Lbus1
Lbus2
LCdc
53.5nH
91.3nH
235.1 nH
189.5nH
83nH
Fig. 5. Simulation result of temperature of the heatsink.
2.2. Thermal design are all in a safe range. Temperature is the most important stressor involves failure among the inverter components, especially in semiconductor devices. Therefore, the inverter of the AGPS is cooled by carefully designed aluminum water coolers showed in Fig. 2(b). Fig.4 shows the typical equivalent thermal circuit of a power semiconductor device, where Rth(j-c), Rth(c-h) and Rth(h-a) are the thermal resistance from junction-to-case, case-to-heatsink, heatsink-to-ambient respectively. Four-order Foster RC network of thermal resistance of the devices in Fig. 3(a) provided by manufacturers listed in Table 3, in which Rth is Rth(j-h) for IEGT while Rth is Rth(j-c) for diode Dp1,2. Rth(c-h) of diode Dp1,2 adopts typical value of 3 K/kW. Rth(h-a) is 4.05 K/kW for all devices, which is determined by the structure of heatsink and calculated by FEM with ANSYS/Icepak, and one of the simulation results is showed in Fig. 5. In order to evaluate the temperature of semi-conductor devices used in the inverter under rated working condition, an electro-thermal model of the AGPS is built in PLECS [11] and many simulations are carried out. Fig. 6 shows the voltage and current simulation waveform of IEGTs and clamp diodes, from which it can be seen that the loss of IEGTs consist of conduction loss Pcond and turn-off loss Poff while the loss of diodes are equal to conduction loss Pcond. Fig. 7 shows the transient junction temperature of the one phase-leg of the inverter. The mean power loss Ploss, the mean junction temperature Tj and the maximum temperature Tj-max of each semiconductor device are listed in Table 4, where the initial temperature of water flowing into the heatsink is set to 25℃. It can be concluded that the junction temperature of all power semiconductor devices of the inverter
2.3. Test of the phase-leg A phase-leg showed in Fig. 2 has been assembled and some functional test has been carried out with a so-called four-switch action double-pulse method [12]. The circuit of the test bench is showed in Fig. 2(a) and an inductive load is connected between U and O port. Fig. 8 is the picture of the test bench. Fig. 9 shows the phase current and selected device voltages of the phase-leg running at 5000 V dc-link voltage and 2000 A peak phase current. The phase-leg can work normally and the maximum turn-off voltages of the outer IEGT and inner IEGT are 3.02 kV and 3.26 kV respectively. Both the peak voltages are lower than the IEGT withstanding voltage of 4.5 kV and have a large safety margin, which means the low-inductance design of the inverter is reliable. The inverter of the AGPS must be switched off as quickly as possible to limit the energy delivered to the grids during breakdown transient process. In [2], the switch-off time is defined and the maximum switchoff time of the NPC inverter is showed in Fig.10. The maximum detection time tdetection is estimated as 50 μs with some margin. IEGT can be reliably turned off in 10 μs, so the maximum turn-off time toff is set as 15 μs. The minimal on-time of single IEGT is tested many times and demonstrated that 15 μs’s minimal on-time is safe for IEGT. In order to evaluate the minimal on-time of IEGT in three-level NPC phase-leg, some tests also carried out on the assembled phase-leg. One of the test results is showed in Fig.11, the S1 is tested by an on-time of 15 μs at 2500 V/1800 A and the overvoltage is at a very safe level. What’s more, we consulted Toshiba and they suggested that the minimal on-time tonmin is set to 20 μs. Therefore, the switch-off time of the inverter of AGPS is less than 100 μs, which is much less than that of the inverters based on Integrated Gate Commutated Thyristors (IGCT). 3. Design of the step-up transformer The step-up transformer should not only increase the voltage at the output of the inverter up to required level, but also isolate the lowvoltage side and high-voltage side to ensure the safety of the equipment at low-voltage side. The Δ-Y configuration, which requires the smallest
Fig. 4. Typical equivalent thermal circuit. 2594
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Fig. 6. Voltage and current of IEGTs and clamp diodes.
Fig. 9. Functional test result of the phase-leg. Fig. 7. Transient junction temperature of the one phase-leg of the inverter. Table 4 Ploss and Tj of the devices in Fig. 9(a). Semiconductor devices
Ploss (kW) Tj (℃) Tj-max (℃)
Outer IEGTs
Inner IEGTs
Dp1,2
S1,4
D1,4
S2,3
D2,3
1.035 36.28 37.56
0.023 29.54 29.67
1.054 36.45 37.60
0.023 29.71 29.73
0.059 25.76 25.83
Fig. 10. Maximum switch-off time of the inverter.
Fig. 8. Test bench of the phase-leg.
Fig. 11. Minimal on-time test result.
turn ratio for step-up application and has the smallest switch current rating [13], is adopted for the step-up transformer. As the inverter regulated by asymmetrical duty cycle modulation, the primary side and secondary side line voltage of the transformer are multilevel ladder wave with variable duty cycle. Fig.12 shows the no-load voltage waveform of the transformer when duty cycle of the inverter m = 1, where Vdc is dc-link voltage and n is the turn ratio of the step-up transformer. When same core flux is generated, the ladder-wave voltage showed in Fig. 12(a) can be equivalent to a sine-wave voltage by Eq. (1).
Fig. 12. Voltage waveform of transformer at no load.
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Fig. 13. Phase current of the inverter.
Fig. 17. Preliminary design of the HV diode rectifier.
Fig. 18. Circuit diagram of one diode arm. Fig. 14. Equivalent circuit when breakdown occurs.
3.48 kV. Because the turn ratio of the transformer is 1:23.5, the rated secondary side line voltage is 141.65 kV and calculated by Eq. (2).
V1 =
π Vdc 3 2
(1)
V2 =
3 V1 n
(2)
The short-circuit impedance Usc is a key parameter of the step-up transformer. Although it can limit short-circuit current, it can also cause voltage loss. The determination of the Usc is the result of compromise between short-circuit current limitation and voltage loss. Fig. 13 shows the output phase current waveform of the inverter when the AGPS works at rated operating condition. When breakdown occurs between acceleration grids, the current flowing through the main switches of the inverter will rise rapidly until the inverter is switched off. The worst case for over-current is that the breakdown occurs when the output phase current of the inverter reaches the maximum 1671 A. Fig.13 also shows the schematic waveform of the short-circuit current. As ST1500GXH24 IEGTs can cut off a maximum
Fig. 15. Designed step-up transformer.
Considering the ± 6% fluctuation of the dc-link voltage, the minimum Root Mean Square (RMS) of the equivalent sine voltage of the transformer primary side is 3.48 kV while the maximum value is 3.92 kV, so the rated primary side line voltage of the step-up transformer is set as
Fig. 16. Interphase electric field of HV windings, a. AC short duration test, b. Lightning impulse test, c. Switching impulse test. 2596
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which is installed in an transformer-like oil tank and the structure details are under design. The rectifier is composed of 6 diode arms, each arm contains 13 modules connected in series and each module consists of 22 diodes in series, uses a total of 1716 diodes. In order to balance the voltage distribution between the series-connected diodes and protect them, a balancing resistor and a RC snubber showed in Fig.18 is connected with each diode in parallel. Combined with engineering experience and the diode manufacturer's suggestion, it was designed that Csi = 0.47μF, Rsi = 200Ω and Rbi = 200kΩ, where i = 1˜286. The design of the HV diode rectifier has not yet been fully completed and is in the stage of program demonstration and simulation verification.
current of 3000 A safely and are used as the main switches of the inverter, the maximum short-circuit current flowing through the inverter must be limited to less than 3000 A. The equivalent circuit of the AGPS when breakdown occurs is showed in Fig. 14, where Lsc1 is the short-circuit inductance of the stepup transformer at the primary side. It’s assumed that all the active switches of the inverter are switched off reliably after a time delay of tdelay = 100 μs from the breakdown. The over-current at the inverter output can be calculated by Eq. (3) and the Lsc1 is calculated by Eq. (4), in which S=6MVA is the transformer capacity while f = 150 Hz is the inverter frequency. Inserting △I = 3000−1671 = 1329 A into Eq. (3) and Eq. (4), it can be got that the Usc must larger than 11.72% to limited the maximum short-circuit current to a safety range. The Usc is determined to be 14% after discussed with the transformer manufacturer.
ΔI =
Vdc tdelay 1.5Lsc1
Lsc1 =
Usc S V12 × 2πf
5. Conclusions (3)
In this paper the design of the AGPS is briefly discussed, focusing on the TPTL inverter, the step-up transformer and the HV diode rectifier. The low-inductance structure design and thermal design of the TPTL inverter were carefully introduced, and a phase-leg of the inverter has been assembled and tested to verify the design. The engineering design of the step-up transformer is based on the simulation and calculation of its key parameters. Meanwhile, the circuit design and the preliminary structure design of the HV diode rectifier were briefly introduced. The designed AGPS can be reliably switched off within 100 μs when breakdown or beam-off occurs between acceleration grids, which is very meaningful for protecting the acceleration grids. The design of the AGPS is underway and is expected to be completed by the first half of 2019.
(4)
In order to evaluate whether Usc = 14% is feasible, the maximum output voltage Vo of the AGPS under load is calculated by Eq. (5) [14], where Io = 25 A is the rated output current of the AGPS while Vdc,min = 5000 × 0.94 = 4700 V is the lowest voltage of the dc-link. The result is Vo = 209.72 kV, which means the voltage loss caused by short-circuit impendence is acceptable.
Vo =
2Vdc,min 18 − 2 ⋅f ⋅Lsc1⋅Io n n
(5)
Based on the calculation of the basic parameters discussed above, the engineering design of the step-up transformer shown in Fig. 15 has been complete. The insulation level of the step-up transformer is LI950AC395 / LI75AC35, with an insulation margin of 40%. In order to reduce the eddy current loss and prevent the core from overheating, high quality grain oriented cold-rolled silicon steel sheets are used and flux barriers are added. Low-voltage winding adopts self-bonding continuously transposed conductors with single helical structure to reduced eddy current loss while high voltage winding uses transposition conductors to control harmonic loss. Two electrostatic shield are added to reduce the effect of the oscillation voltage caused by the accelerator grids breakdown. What’s more, many electric, magnetic, thermal and mechanical simulation analyses were carried out to verify the design of the transformer. Fig. 16 shows a set of electric field simulation results, which proves that the main insulation design is reliable.
Acknowledgments This work is supported by the National Key R&D Program of China (No. 2017YFE0300104) and the National Natural Science Foundation of China (No. 51707073). References [1] B. Wan, et al., Physics design of CFETR: determination of the device engineering parameters, IEEE Trans. Plasma Sci. 42 (3) (2014) 495–502. [2] L. Zanotto, et al., Assessment of performance of the acceleration grid power supply of the ITER neutral beam injector, Fusion Eng. Des. 84 (7-11) (2009) 2037–2041. [3] M. Schmid, et al., Past and future upgrades of the gyrotron high voltage cathode power supplies at the Forschungszentrum Karlsruhe, Fusion Eng. Des. 84 (7) (2009) 1734–1738. [4] M. Hanada, et al., Development and design of the negative-ion-based NBI for JT-60 Super Advanced, J. Plasma Fusion Res. SER. 9 (2010). [5] M. Mizuno, et al., Inverter type high voltage DC power supply for negative-ionbased neutral beam injectors[C]// fusion engineering, 1989, Proceedings. IEEE Thirteenth Symposium on. IEEE 1 (1989) 574–577. [6] F. Liu, et al., Modified three-phase three-level dc/dc converter with zero-voltageswitching characteristic-adopting asymmetrical duty cycle control, IEEE Trans. Power Electron. 29 (12) (2014) 6307–6318. [7] Z. Chen, et al., Analysis and experiments for IGBT, IEGT, and IGCT in Hybrid DC Circuit Breaker, IEEE Trans. Ind. Electron. 65 (4) (2018) 2883–2892. [8] M. Portesine, et al., Optimized diode design for IGBT’s and GCT’s switching circuits, Proc. 9th Eur. Conf. Power Electron. Applicat 4 (2001) 379–388. [9] Toshiba Press Pack IEGT ST1500GXH24, Toshiba, Datasheet, (2016) 9. [Online]. Available: http://www.toshiba.com. [10] Fast recovery diode 5SDF20L4520,” ABB Switzerland Ltd., Datasheet, Doc. (2019) No. 5SYA1186-02, Jan. 17. [Online]. Available: www.abb.com. [11] https://www.plexim.com. [12] G. Yang, et al., A novel four-switch action double-pulse test method for high-voltage high-power three-level converters, Proc. Csee 35 (3) (2015) 695–701 (in Chinese). [13] H. Kim, et al., A three-phase zero-voltage and zero-current switching DC–DC converter for fuel cell applications, Ieee Trans. Power Electron. 25 (2) (2010) 391–398. [14] V. Toigo, et al., Progress of the ITER NBI acceleration grid power supply reference design, Fusion Eng. Des. 88 (6-8) (2013) 956–959. [15] K. Watanabe, et al., Design of Neutral Beam Injection Power Supplies for ITER (No. JAERI-TECH–2000-033)[R], Japan Atomic Energy Research Inst., 2000.
4. Design of the HV diode rectifier In order to convert the ladder-wave voltage of the step-up transformer secondary side to dc high voltage of 200 kV, the HV diode rectifier should be made up of a large number of low voltage diodes in series. The withstand voltage Varm,max of one diode arm of the HV rectifier is about 510 kV and can be calculated by Eq. (6). Vo,max is the maximum transient voltage of the AGPS at breakdown and assumed as 250 kV with a large margin, ftest = 1.15 is the test safety factor, fbalance is the voltage balance rate and set to 0.85, and fsatety is the safety margin with a value of 1.5.
Varm,max = (Vo,max × ftest ÷ fbalance ) × fsafety
(6)
IXYS’s avalanche diode DSA35-18 A and DSAI35-18 A with withstand voltage of 1.8 kV are used as the basic elements of the HV rectifier because of their good ability to absorb reverse surge power and a certain automatic voltage sharing ability when used in series. Refer to JAERI's design of the HV diode rectifier for ITER N-NBI AGPS published in 2000 [15], a HV rectifier showed in Fig. 17 is preliminarily designed,
2597
Contents lists available at ScienceDirect
Fusion Engineering and Design journal homepage: www.elsevier.com/locate/fusengdes
Design of acceleration grid power supply for CFETR negative-ion-based neutral beam injection prototype
T
⁎
Xueliang Zhanga, Ming Zhanga, Shaoxiang Maa, , Shu Wangb, Dongyu Wanga, Xiao Maa, Lan Zhoua, Shu Yanga, Kexun Yua, Yuan Pana a International Joint Research Laboratory of Magnetic Confinement Fusion and Plasma Physics, State Key Laboratory of Advanced Electromagnetic Engineering and Technology, School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan, 430074, China b State Grid Hubei Electric Power Company Limited Economic Research Institute, Wuhan, 430074, China
A R T I C LE I N FO
A B S T R A C T
Keywords: CFETR N-NBI Neutral point clamped inverter Step-up transformer HV diode rectifier
The planned China Fusion Engineering Test Reactor (CFETR) needs one or more Negative-ion-based Neutral Beam Injectors (N-NBIs) with a beam energy of 500 keV to heat plasma and drive current. In order to prepare for CFETR, a prototype of CFETR N-NBI is being designed to accelerate hydrogen negative ions up to 200 keV with a beam current as high as 20 A for 3600 s at max, and an Acceleration Grid Power Supply (AGPS) rated at −200 kV/25 A is needed. A single stage inverter-type high voltage power supply is adopted as AGPS of the NNBI prototype. The AGPS mainly includes a 12 pulse rectifier based on thyristor, a dual-dc-link system rated at 5 kV, a three phase three level neutral point clamped dc/ac inverter based on injection enhanced gate transistor, a three-phase set-up transformer, a high voltage uncontrolled rectifier based on avalanche diode and a high voltage R-C dc-filter. This paper describes the design of the AGPS for CFETR N-NBI prototype, focusing on the inverter, the step-up transformer and the HV diode rectifier.
1. Introduction China Fusion Engineering Test Reactor (CFETR) is a planned new fusion facility with a major mission to demonstrate full cycle of tritium self-sustained with tritium breeding ratio ≥1.2 [1]. In order to heat plasma and drive current, CFETR needs one or more Negative-ion-based Neutral Beam Injectors (N-NBIs) with a beam energy of 500 keV. However, China has no experience in developing high-power N-NBI. Aiming at laying the foundation for the development of CFETR N-NBI, a prototype of CFETR N-NBI is being designed to accelerate hydrogen negative ions up to 200 keV with a beam current as high as 20 A for 3600 s. The N-NBI prototype needs an Acceleration Grid Power Supply (AGPS) rated at −200 kV/25 A. As one of the core components of N-NBI, the AGPS is direct power source of the N-NBI’s beam energy and characterized by rapid dynamic response, highly accurate output voltage, low output voltage ripple, and fast switch-off speed when breakdown or beam-off occurs between acceleration grids [2]. Nowadays, the High Voltage Power Supply (HVPS) based on Pulse Step Modulation (PSM) method is the mainstream scheme of HVPS used in fusion engineering field [3]. The AGPS of the CFETR N-NBI prototype can also adopt PSM power supply. However, with respect to JT-60U N-NBI AGPS [4] and ITER N-NBI ⁎
AGPS [2], the CFETR N-NBI prototype adopts a single stage invertertype HVPS as its AGPS with the purpose of accumulating experience for CFETR. The proposed scheme of the AGPS is shown in Fig. 1, the AGPS consists mainly of phase-controlled rectifier (12 pulse), three phase three level Neutral Point Clamped (NPC) inverter, step-up transformer, high voltage uncontrolled rectifier and high voltage R-C filter. Table 1 lists the major design parameters of the AGPS for the CFETR N-NBI prototype. In order to meet the requirements, the AGPS control system will gather the output voltage and dc-link voltage for a feedback control. For the purpose of limiting the output dc current component from dc/ac inverter to less than 1% of the rated output current of the inverter, a direct feedback control of this component is realized by measured primary phase current of the transformer. What’s more, a distributed core snubber is foreseen to limit the short-circuit current and surge energy when breakdown occurs between acceleration grids. As the inverter, the step-up transformer and the HV diode rectifier used in the AGPS are characterized by complex structure and strict technical requirements, they need to be carefully designed and manufactured. The design of the AGPS is underway, and some components have already started the prototype verification phase. Although the circuit topology of this AGPS is similar to the topology of the AGPS for
Corresponding author. E-mail address: [email protected] (S. Ma).
https://doi.org/10.1016/j.fusengdes.2019.04.050 Received 2 October 2018; Received in revised form 11 April 2019; Accepted 11 April 2019 Available online 01 May 2019 0920-3796/ © 2019 Elsevier B.V. All rights reserved.
Fusion Engineering and Design 146 (2019) 2592–2597
X. Zhang, et al.
Fig. 1. The AGPS scheme for CFETR N-NBI prototype.
tests have been carried out on IEGT using double pulse method [8]. The comparison between soft-switching and hard-switching test results showed that the inverter of the AGPS can adopt hard-switching mode when the circuit's stray inductance can be restricted at a low level.
Table 1 Major design parameters of the AGPS. Specifications
Values
Input
Voltage Frequency Range Stability Ripple Rise time Settling time 25 A@max Rated value Ripple Frequency Dc current component Connection type Turn tatio Usc 3600 s @max < 100 μs < 10 J
Output voltage
Output current Dc-link voltage Inverter Step-up transformer
Pulse length Switch-off time Fault energy
10 kV 50 Hz 0 kV˜-200 kV < ± 2% < 10% (< ± 5%) < 80ms < 50ms
2.1. Structural design One phase leg of the inverter is shown in Fig.2, where Cdc is dc-link capacitors, Cc is clamp capacitor, Rp is clamp resistance, Dp1,2 are clamp diodes, S1-4 are IEGTs and D1-4 are antiparallel diodes of IEGTs. Cdc is 12 m F and contains 12 self-healing metallized film capacitors with 2 series 6 parallel. Rp is 20kΩ and can prevent the clamp failure of Dp1,2. The IEGTs adopt ST1500GXH24 [9] produced by Toshiba and clamp diodes adopt ABB’s 5SDF20L4520 [10]. The IEGT drivers use SK08110 customized by Firstack with RG(on) = 5.1Ω and RG(off) = 10Ω. The goal of the structural design is to realize the low-inductance structure of the power circuit. The three-level NPC structure contains two different commutation loops as illustrated in Fig. 9(a). The loop 1 contains two devices while the loop 2 involves four devices. The inductances Lσ1 and Lσ2 are used to represent the concentrated stray inductances of the two loops, including the inductance in the semiconductor stacks (Lstack1, Lstack2), the Equivalent Series Inductance (ESL) of the dc-link capacitors (LCdc), and the inductance in bus bar (Lbus1, Lbus2). As the values of Lstack1, Lstack2 and LCdc are relatively fixed, the key to low-inductance design is to reduce Lbus1 and Lbus2. The connection between the dc-link capacitors and the inverter legs adopts a carefully designed laminated busbar, which is shown in Fig. 3. Table 2 summarizes the inductance values of each part of the two loops. The values of Lstack1, Lstack2, Lbus1 and Lbus2 are obtained using the Finite Element Method (FEM) with ANSYS/Q3D, while the value of LCdc is provided by capacitor supplier. So, Lσ1 is 371.6 nH and Lσ2 is 363.8 nH.
5000 V < ± 5% 150 Hz < 1% △/Y 1:23.5 ≈14%
ITER N-NBI, their engineering designs are quite different, especially for inverters. ITER uses IGCT-based inverters, while the AGPS discussed in this paper adopts IEGT-based inverter. Due to adequate testing and careful design, the IEGT-based inverter designed in this paper has the advantages of simple structure, fast dynamic response and high reliability. Based on the design showed in this paper, the AGPS for CFETR NNBI prototype can be reliably switched off within 100 μs when breakdown or beam-off occurs between acceleration grids, which is very meaningful for protecting the N-NBI prototype and the AGPS itself. The following three parts will briefly introduce the design of the inverter, the step-up transformer and the HV diode rectifier. 2. Design of the TPTL NPC inverter The AGPS is a single stage inverter-type HVPS, both the voltage regulation and high-speed switching are controlled by the inverter at low voltage side [5]. It can be said that the performance of the AGPS is determined by the inverter to a great extent. Referring to the medium voltage converters widely used in industrial fields, the TPTL NPC scheme is chosen as the inverter scheme. For the purpose of making full use of the dc-link voltage and reducing the switching frequency of the inverter, the inverter is regulated by asymmetrical duty cycle modulation [6] at 150 Hz. The inverter frequency is mainly determined by the difficulty of manufacturing the step-up transformer, and the efficiency and dynamic characteristics of the AGPS are taken into account. After comparing the high-power semiconductor devices on the market [7], Injection Enhanced Gate Transistor (IEGT) is used as the main switch of the inverter. In order to lay foundation for the inverter design, a lot of
Fig. 2. One phase leg of the inverter. 2593
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Table 3 Thermal resistance of the devices in Fig. 9(a). Thermal Impedance
IEGT
Rth
S1-4 D1-4
Diode
Dp1,2
Ri(K/kW) τi(s) Ri(K/kW) τi(s) Ri(K/kW) τi(s)
i=1
i=2
i=3
i=4
4.157 0.6663 10.634 0.7117 3.708 0.5336
1.858 0.0615 4.797 0.0632 1.426 0.0670
0.642 0.0055 1.622 0.0056 0.686 0.0074
0.220 0.0005 0.556 0.0005 0.176 0.0011
Fig. 3. Laminated busbar of the inverter. Table 2 Inductance values of each part. Lstack1
Lstack2
Lbus1
Lbus2
LCdc
53.5nH
91.3nH
235.1 nH
189.5nH
83nH
Fig. 5. Simulation result of temperature of the heatsink.
2.2. Thermal design are all in a safe range. Temperature is the most important stressor involves failure among the inverter components, especially in semiconductor devices. Therefore, the inverter of the AGPS is cooled by carefully designed aluminum water coolers showed in Fig. 2(b). Fig.4 shows the typical equivalent thermal circuit of a power semiconductor device, where Rth(j-c), Rth(c-h) and Rth(h-a) are the thermal resistance from junction-to-case, case-to-heatsink, heatsink-to-ambient respectively. Four-order Foster RC network of thermal resistance of the devices in Fig. 3(a) provided by manufacturers listed in Table 3, in which Rth is Rth(j-h) for IEGT while Rth is Rth(j-c) for diode Dp1,2. Rth(c-h) of diode Dp1,2 adopts typical value of 3 K/kW. Rth(h-a) is 4.05 K/kW for all devices, which is determined by the structure of heatsink and calculated by FEM with ANSYS/Icepak, and one of the simulation results is showed in Fig. 5. In order to evaluate the temperature of semi-conductor devices used in the inverter under rated working condition, an electro-thermal model of the AGPS is built in PLECS [11] and many simulations are carried out. Fig. 6 shows the voltage and current simulation waveform of IEGTs and clamp diodes, from which it can be seen that the loss of IEGTs consist of conduction loss Pcond and turn-off loss Poff while the loss of diodes are equal to conduction loss Pcond. Fig. 7 shows the transient junction temperature of the one phase-leg of the inverter. The mean power loss Ploss, the mean junction temperature Tj and the maximum temperature Tj-max of each semiconductor device are listed in Table 4, where the initial temperature of water flowing into the heatsink is set to 25℃. It can be concluded that the junction temperature of all power semiconductor devices of the inverter
2.3. Test of the phase-leg A phase-leg showed in Fig. 2 has been assembled and some functional test has been carried out with a so-called four-switch action double-pulse method [12]. The circuit of the test bench is showed in Fig. 2(a) and an inductive load is connected between U and O port. Fig. 8 is the picture of the test bench. Fig. 9 shows the phase current and selected device voltages of the phase-leg running at 5000 V dc-link voltage and 2000 A peak phase current. The phase-leg can work normally and the maximum turn-off voltages of the outer IEGT and inner IEGT are 3.02 kV and 3.26 kV respectively. Both the peak voltages are lower than the IEGT withstanding voltage of 4.5 kV and have a large safety margin, which means the low-inductance design of the inverter is reliable. The inverter of the AGPS must be switched off as quickly as possible to limit the energy delivered to the grids during breakdown transient process. In [2], the switch-off time is defined and the maximum switchoff time of the NPC inverter is showed in Fig.10. The maximum detection time tdetection is estimated as 50 μs with some margin. IEGT can be reliably turned off in 10 μs, so the maximum turn-off time toff is set as 15 μs. The minimal on-time of single IEGT is tested many times and demonstrated that 15 μs’s minimal on-time is safe for IEGT. In order to evaluate the minimal on-time of IEGT in three-level NPC phase-leg, some tests also carried out on the assembled phase-leg. One of the test results is showed in Fig.11, the S1 is tested by an on-time of 15 μs at 2500 V/1800 A and the overvoltage is at a very safe level. What’s more, we consulted Toshiba and they suggested that the minimal on-time tonmin is set to 20 μs. Therefore, the switch-off time of the inverter of AGPS is less than 100 μs, which is much less than that of the inverters based on Integrated Gate Commutated Thyristors (IGCT). 3. Design of the step-up transformer The step-up transformer should not only increase the voltage at the output of the inverter up to required level, but also isolate the lowvoltage side and high-voltage side to ensure the safety of the equipment at low-voltage side. The Δ-Y configuration, which requires the smallest
Fig. 4. Typical equivalent thermal circuit. 2594
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Fig. 6. Voltage and current of IEGTs and clamp diodes.
Fig. 9. Functional test result of the phase-leg. Fig. 7. Transient junction temperature of the one phase-leg of the inverter. Table 4 Ploss and Tj of the devices in Fig. 9(a). Semiconductor devices
Ploss (kW) Tj (℃) Tj-max (℃)
Outer IEGTs
Inner IEGTs
Dp1,2
S1,4
D1,4
S2,3
D2,3
1.035 36.28 37.56
0.023 29.54 29.67
1.054 36.45 37.60
0.023 29.71 29.73
0.059 25.76 25.83
Fig. 10. Maximum switch-off time of the inverter.
Fig. 8. Test bench of the phase-leg.
Fig. 11. Minimal on-time test result.
turn ratio for step-up application and has the smallest switch current rating [13], is adopted for the step-up transformer. As the inverter regulated by asymmetrical duty cycle modulation, the primary side and secondary side line voltage of the transformer are multilevel ladder wave with variable duty cycle. Fig.12 shows the no-load voltage waveform of the transformer when duty cycle of the inverter m = 1, where Vdc is dc-link voltage and n is the turn ratio of the step-up transformer. When same core flux is generated, the ladder-wave voltage showed in Fig. 12(a) can be equivalent to a sine-wave voltage by Eq. (1).
Fig. 12. Voltage waveform of transformer at no load.
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Fig. 13. Phase current of the inverter.
Fig. 17. Preliminary design of the HV diode rectifier.
Fig. 18. Circuit diagram of one diode arm. Fig. 14. Equivalent circuit when breakdown occurs.
3.48 kV. Because the turn ratio of the transformer is 1:23.5, the rated secondary side line voltage is 141.65 kV and calculated by Eq. (2).
V1 =
π Vdc 3 2
(1)
V2 =
3 V1 n
(2)
The short-circuit impedance Usc is a key parameter of the step-up transformer. Although it can limit short-circuit current, it can also cause voltage loss. The determination of the Usc is the result of compromise between short-circuit current limitation and voltage loss. Fig. 13 shows the output phase current waveform of the inverter when the AGPS works at rated operating condition. When breakdown occurs between acceleration grids, the current flowing through the main switches of the inverter will rise rapidly until the inverter is switched off. The worst case for over-current is that the breakdown occurs when the output phase current of the inverter reaches the maximum 1671 A. Fig.13 also shows the schematic waveform of the short-circuit current. As ST1500GXH24 IEGTs can cut off a maximum
Fig. 15. Designed step-up transformer.
Considering the ± 6% fluctuation of the dc-link voltage, the minimum Root Mean Square (RMS) of the equivalent sine voltage of the transformer primary side is 3.48 kV while the maximum value is 3.92 kV, so the rated primary side line voltage of the step-up transformer is set as
Fig. 16. Interphase electric field of HV windings, a. AC short duration test, b. Lightning impulse test, c. Switching impulse test. 2596
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which is installed in an transformer-like oil tank and the structure details are under design. The rectifier is composed of 6 diode arms, each arm contains 13 modules connected in series and each module consists of 22 diodes in series, uses a total of 1716 diodes. In order to balance the voltage distribution between the series-connected diodes and protect them, a balancing resistor and a RC snubber showed in Fig.18 is connected with each diode in parallel. Combined with engineering experience and the diode manufacturer's suggestion, it was designed that Csi = 0.47μF, Rsi = 200Ω and Rbi = 200kΩ, where i = 1˜286. The design of the HV diode rectifier has not yet been fully completed and is in the stage of program demonstration and simulation verification.
current of 3000 A safely and are used as the main switches of the inverter, the maximum short-circuit current flowing through the inverter must be limited to less than 3000 A. The equivalent circuit of the AGPS when breakdown occurs is showed in Fig. 14, where Lsc1 is the short-circuit inductance of the stepup transformer at the primary side. It’s assumed that all the active switches of the inverter are switched off reliably after a time delay of tdelay = 100 μs from the breakdown. The over-current at the inverter output can be calculated by Eq. (3) and the Lsc1 is calculated by Eq. (4), in which S=6MVA is the transformer capacity while f = 150 Hz is the inverter frequency. Inserting △I = 3000−1671 = 1329 A into Eq. (3) and Eq. (4), it can be got that the Usc must larger than 11.72% to limited the maximum short-circuit current to a safety range. The Usc is determined to be 14% after discussed with the transformer manufacturer.
ΔI =
Vdc tdelay 1.5Lsc1
Lsc1 =
Usc S V12 × 2πf
5. Conclusions (3)
In this paper the design of the AGPS is briefly discussed, focusing on the TPTL inverter, the step-up transformer and the HV diode rectifier. The low-inductance structure design and thermal design of the TPTL inverter were carefully introduced, and a phase-leg of the inverter has been assembled and tested to verify the design. The engineering design of the step-up transformer is based on the simulation and calculation of its key parameters. Meanwhile, the circuit design and the preliminary structure design of the HV diode rectifier were briefly introduced. The designed AGPS can be reliably switched off within 100 μs when breakdown or beam-off occurs between acceleration grids, which is very meaningful for protecting the acceleration grids. The design of the AGPS is underway and is expected to be completed by the first half of 2019.
(4)
In order to evaluate whether Usc = 14% is feasible, the maximum output voltage Vo of the AGPS under load is calculated by Eq. (5) [14], where Io = 25 A is the rated output current of the AGPS while Vdc,min = 5000 × 0.94 = 4700 V is the lowest voltage of the dc-link. The result is Vo = 209.72 kV, which means the voltage loss caused by short-circuit impendence is acceptable.
Vo =
2Vdc,min 18 − 2 ⋅f ⋅Lsc1⋅Io n n
(5)
Based on the calculation of the basic parameters discussed above, the engineering design of the step-up transformer shown in Fig. 15 has been complete. The insulation level of the step-up transformer is LI950AC395 / LI75AC35, with an insulation margin of 40%. In order to reduce the eddy current loss and prevent the core from overheating, high quality grain oriented cold-rolled silicon steel sheets are used and flux barriers are added. Low-voltage winding adopts self-bonding continuously transposed conductors with single helical structure to reduced eddy current loss while high voltage winding uses transposition conductors to control harmonic loss. Two electrostatic shield are added to reduce the effect of the oscillation voltage caused by the accelerator grids breakdown. What’s more, many electric, magnetic, thermal and mechanical simulation analyses were carried out to verify the design of the transformer. Fig. 16 shows a set of electric field simulation results, which proves that the main insulation design is reliable.
Acknowledgments This work is supported by the National Key R&D Program of China (No. 2017YFE0300104) and the National Natural Science Foundation of China (No. 51707073). References [1] B. Wan, et al., Physics design of CFETR: determination of the device engineering parameters, IEEE Trans. Plasma Sci. 42 (3) (2014) 495–502. [2] L. Zanotto, et al., Assessment of performance of the acceleration grid power supply of the ITER neutral beam injector, Fusion Eng. Des. 84 (7-11) (2009) 2037–2041. [3] M. Schmid, et al., Past and future upgrades of the gyrotron high voltage cathode power supplies at the Forschungszentrum Karlsruhe, Fusion Eng. Des. 84 (7) (2009) 1734–1738. [4] M. Hanada, et al., Development and design of the negative-ion-based NBI for JT-60 Super Advanced, J. Plasma Fusion Res. SER. 9 (2010). [5] M. Mizuno, et al., Inverter type high voltage DC power supply for negative-ionbased neutral beam injectors[C]// fusion engineering, 1989, Proceedings. IEEE Thirteenth Symposium on. IEEE 1 (1989) 574–577. [6] F. Liu, et al., Modified three-phase three-level dc/dc converter with zero-voltageswitching characteristic-adopting asymmetrical duty cycle control, IEEE Trans. Power Electron. 29 (12) (2014) 6307–6318. [7] Z. Chen, et al., Analysis and experiments for IGBT, IEGT, and IGCT in Hybrid DC Circuit Breaker, IEEE Trans. Ind. Electron. 65 (4) (2018) 2883–2892. [8] M. Portesine, et al., Optimized diode design for IGBT’s and GCT’s switching circuits, Proc. 9th Eur. Conf. Power Electron. Applicat 4 (2001) 379–388. [9] Toshiba Press Pack IEGT ST1500GXH24, Toshiba, Datasheet, (2016) 9. [Online]. Available: http://www.toshiba.com. [10] Fast recovery diode 5SDF20L4520,” ABB Switzerland Ltd., Datasheet, Doc. (2019) No. 5SYA1186-02, Jan. 17. [Online]. Available: www.abb.com. [11] https://www.plexim.com. [12] G. Yang, et al., A novel four-switch action double-pulse test method for high-voltage high-power three-level converters, Proc. Csee 35 (3) (2015) 695–701 (in Chinese). [13] H. Kim, et al., A three-phase zero-voltage and zero-current switching DC–DC converter for fuel cell applications, Ieee Trans. Power Electron. 25 (2) (2010) 391–398. [14] V. Toigo, et al., Progress of the ITER NBI acceleration grid power supply reference design, Fusion Eng. Des. 88 (6-8) (2013) 956–959. [15] K. Watanabe, et al., Design of Neutral Beam Injection Power Supplies for ITER (No. JAERI-TECH–2000-033)[R], Japan Atomic Energy Research Inst., 2000.
4. Design of the HV diode rectifier In order to convert the ladder-wave voltage of the step-up transformer secondary side to dc high voltage of 200 kV, the HV diode rectifier should be made up of a large number of low voltage diodes in series. The withstand voltage Varm,max of one diode arm of the HV rectifier is about 510 kV and can be calculated by Eq. (6). Vo,max is the maximum transient voltage of the AGPS at breakdown and assumed as 250 kV with a large margin, ftest = 1.15 is the test safety factor, fbalance is the voltage balance rate and set to 0.85, and fsatety is the safety margin with a value of 1.5.
Varm,max = (Vo,max × ftest ÷ fbalance ) × fsafety
(6)
IXYS’s avalanche diode DSA35-18 A and DSAI35-18 A with withstand voltage of 1.8 kV are used as the basic elements of the HV rectifier because of their good ability to absorb reverse surge power and a certain automatic voltage sharing ability when used in series. Refer to JAERI's design of the HV diode rectifier for ITER N-NBI AGPS published in 2000 [15], a HV rectifier showed in Fig. 17 is preliminarily designed,
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