Design of second-generation current conveyors employing bacterial foraging optimization

Microelectronics Journal 41 (2010) 616–626

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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Design of second-generation current conveyors employing bacterial foraging optimization Amitava Chatterjee a,b,n, Mourad Fakhfakh c, Patrick Siarry a a

Laboratoire Images, Signaux et Syste mes Intelligents (LiSSi, EA 3956), Universite´ Paris-Est Cre´teil Val de Marne, 61 avenue du Ge´ne´ral de Gaulle, 94010 Cre´teil, France Electrical Engineering Department, Jadavpur University, Kolkata 700032, India c University of Sfax, Tunisia b

a r t i c l e in f o

a b s t r a c t

Article history: Received 20 October 2009 Received in revised form 14 June 2010 Accepted 21 June 2010 Available online 10 July 2010

The present paper deals with the optimal sizing of CMOS positive second-generation current conveyors (CCII +) employing an optimization algorithm. A contemporary non-gradient stochastic optimization algorithm, called bacterial foraging optimization (BFO) algorithm, has been employed to obtain the optimal physical dimensions of the constituent PMOS and NMOS transistors of the CCII +. The optimization problem has been cast as a bi-objective minimization problem, where we attempt to simultaneously minimize the parasitic X-port input resistance (RX) and maximize the high end cut-off frequency of the current signal (fci). The results have been presented for a large selection of bias currents (I0) and our proposed algorithm could largely outperform a similar algorithm, recently proposed, employing particle swarm optimization (PSO) algorithm and also the differential evolution (DE) algorithm. & 2010 Elsevier Ltd. All rights reserved.

Keywords: Second-generation current conveyor Bacterial foraging optimization CMOS Parasitic X-port input resistance High end cut-off frequency of the current signal

1. Introduction Second-generation current conveyors were introduced in 1970 [1,2] and gradually, over a period of time, they have gained immense popularity as a great candidate choice for current mode analog blocks. The current conveyors (CCs) are well-known analog current mode circuits (CMCs), which are abundantly used in amplifiers, oscillators, filters, wave shaping circuits etc. [3]. CCs enjoy great acceptance in the design of voltage and power starved circuits, as in medical electronics and space instrumentation, because of their low-voltage and low-power architectures. A CC is basically a three port (X, Y, Z) structure and it can be classified in accordance with the characteristics of its X, Y, and Z ports. CCs are also very popular in development of built-in self test (BIST) structures, used for the monitoring of currents in various branches of a circuit and are largely used as current sensors, used for the purpose of checking power supply current to ascertain health of a circuit [3]. For quite some time now, several research works have been primarily focused to obtain enhancement of the performances of these CCs fabricated. However, till now, it is strongly felt that the domain of designing high

n Corresponding author at: Electrical Engineering Department, Jadavpur University, Kolkata 700032, India. E-mail addresses: [email protected] (A. Chatterjee), [email protected] (M. Fakhfakh), [email protected] (P. Siarry).

0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.06.013

performance integrated CC circuits is still open and the need is ever growing in CMOS technology [4] where improving high end frequency response of current mode circuits is mostly appreciated. In this paper, we focus on determination of optimal sizing of CMOS positive translinear loop second-generation current conveyors (CCII+ ) [4–6]. This automated design procedure strives to attain the optimal physical dimensions of all the PMOS and NMOS transistors employed in the physical realization of the CCII +. As mentioned in the previous paragraph, the design of a high performance CCII+ architecture requires that the bandwidth available for current signal should be as high as possible, i.e. one needs to maximize the high end cut-off frequency for the current waveform (fci). At the same time, another important factor is that the input resistance at port X i.e. RX is ideally zero, but always non-zero in practical realization. This RX must also be as small as possible. Hence the optimization problem is formulated as a bi-objective minimization problem, where we attempt to simultaneously minimize the parasitic input resistance RX and maximize the cut-off frequency fci. To the best of our knowledge and belief, few works have been reported till date, which focus on optimization of the physical dimensions of the CCII +, to attain enhanced performance [7,8]. In [7], a steepest descent based optimization algorithm was used to iteratively adjust the W/L ratios and the capacitance values to obtain an optimum performance for the filter designed using CCII. In [8], a heuristic based iterative solution was proposed where, in each iteration,

A. Chatterjee et al. / Microelectronics Journal 41 (2010) 616–626

random solutions are generated and their suitabilities are evaluated utilizing some performance criteria. In this work, we propose to utilize bacterial foraging optimization (BFO) algorithm, a recently proposed stochastic non-gradient type optimization algorithm, to learn the desired physical dimensions of the MOS transistors, so that the desired objective is fulfilled to the maximum extent. The bi-objective minimization problem is solved employing the BFO algorithm, by utilizing a weighting approach, which combines the two conflicting objectives to produce a comprehensive objective function. In BFO algorithm, the optimization strategy is based on the concept that for those animals which can locate, handle and ingest food better than other animals, the propagation of genes is favored and they are more likely to enter into a reproduction mechanism [9]. The algorithm works employing four stages: (i) chemotaxis, (ii) swarming, (iii) reproduction, and (iv) elimination and dispersal steps. It is the chemotactic behavior of E. coli bacteria which plays the most crucial part and requires efficient biomimicing to successfully evolve an optimization strategy. In the present work, we demonstrate how BFO can be successfully employed to determine the optimum design of second-generation current conveyors and we demonstrate how this algorithm could outperform a similar approach proposed in [10], where another popular non-gradient type optimization strategy, called particle swarm optimization (PSO), was employed to design an identical second generation current conveyor system and also differential evolution (DE) algorithm employed for the same design problem. To demonstrate the utility of the proposed system, the simulations were carried out for a large set of bias currents (I0) and in most of these cases BFO could emerge as the winning solution. The rest of the paper is presented as follows. In section 2, we present a brief introduction of CMOS second generation current conveyors and their mathematical models employed for performing the necessary optimization function. Section 3 presents the bacterial foraging optimization algorithm employed in this work to obtain the optimal physical configurations of the NMOS and PMOS transistors. The performance evaluation is presented in section 4. Section 5 concludes the paper.

2. Second generation current conveyors and their mathematical models Current conveyors were introduced in 1970 [1]. Nowadays, they form, arguably, the most famous building block in analog current mode circuits (CMCs) [2,4]. It is a well-known fact that the voltage mode circuits (VMCs), like op-amps, voltage-to-frequency converters (VFCs), voltage comparators etc. are not suitable for high frequency operations, because of their constraints due to low bandwidths. Such problems arise in VMCs because of the presence of stray and circuit capacitances [3]. CMCs have been proven to be better performers than VFCs because the circuit operation is primarily dependent on the currents and hence it is possible to design circuits using CMCs that can operate over a wide dynamic range. Among these very popular CMC configurations, current conveyors, and specially the second generation current conveyors (CCIIs), stand out. As a result, significant success in utilizing CCIIs, to design basic building blocks for development of voltage/ current mode signal processing circuits, has been obtained in recent times [11–14]. A Current Conveyor (CC) is a three terminal active block. The conventional representation of a CC is shown in Fig. 1(a). Fig. 1(b) and (c) show, respectively, the equivalent nullator/norator representations of a CCII + [5,15] and a CCII  [5], which reproduce the ideal behavior of the corresponding CC. Nullor equivalent circuits of the other kinds of CCs can be found in [5].

617

Basically, a CC ensures the functionality of conveying the voltage from port Y to port X and conveying the current from port X to port Z. Due to the presence of the parasitic elements, performances of a practical CC differ from the ideal ones. The performances of real life current conveyors, i.e. CCs designed at the transistor level, are affected by inherent parasitic elements. These parasitic elements are commonly modeled by three impedances ZX, ZY and ZZ connected to the corresponding ports. Fig. 2 shows the equivalent model of a CC. Accordingly, the relationship between the CC ports can be expressed as follows: 2 3 1 2 3 2 3 g 0 6 ZY 7 VY IY 6 7 6V 7 6 a Z 6 7 0 74 IX 7 ð1Þ X 4 X 5¼6 5 6 7 1 4 5 VZ IZ b 0 ZY For a ¼ + 1, the CC is called a direct CC, whereas, when a ¼  1, the CC is called an indirect one. The factor b models the nature of current transfer between X and Z ports. If b ¼1, the CC is said to be positive. It is called a negative CC, when b ¼ 1. Finally, when g ¼1, the CC is known as a first generation one. It is called a second generation CC when g ¼0. In this work we deal with a CMOS translinear loop based positive second generation current conveyor (CCII + ) [4], whose transistor level implementation is shown in Fig. 3 [6]. In Fig. 3, transistors M1–M4 instantiate the translinear loop and ensure the voltage transfer between Y and X terminals. I0 is the CC bias current. I0 is mirrored through transistors M9–M13 in the left branch of the translinear loop. Transistors M5–M8 are also called current mirrors and these transistors are specifically utilized to reproduce at port Z, the current applied at port X. As aforementioned and as depicted in Fig. 2, the CC presents inherent parasitic elements when it is designed at the transistor level. It has been proven that, among these parasitic elements, RX is the most dominant one that significantly affects the CC performances [3,4,6]. It has also been confirmed that it is primarily the current bandwidth that limits the range of frequency application of a CC, because it is already known that the voltage bandwidth is intrinsically higher than the current bandwidth [6]. Thus, in this work we focus on optimizing most influential performances, i.e. minimizing the parasitic X-port resistance (RX) and maximizing the highest cut-off frequency for current (fci). These influential parameters vary with the geometric dimensions of the MOS transistors and our primary objective is to obtain the optimal values of the geometric dimensions of MOS transistors forming the CCII. The main constraints and the component objective functions are detailed below: 2.1. Main constraints Transistor saturation conditions: The mandatory operating conditions necessitate that all the CCII transistors must operate in the saturation mode. For these reasons, the saturation constraints for all MOSFETs were individually determined. For instance, expression (2) gives constraints on M2 and M8 transistors: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi I0 VDD I0 9VTP 9 r ð2Þ KP WP =LP 2 KN WN =LN Here WN/LN gives the aspect ratio of the corresponding NMOS transistor and WP/LP gives the aspect ratio of the corresponding

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Y

Y

X

Z

CC

Z

X

Y

Z

X

r=1ohm

r=1ohm

Fig. 1. (a) General representation of current conveyor, (b) the nullor equivalency of an ideal CCII  , and (c) the nullor equivalency of an ideal CCII + .

Zx

Cx X

Vx

Ix

Lx

CC

Iy

Vy

Y

ideal

Xi

Rx

Z

Zi

Iz

Yi

Cy

Cz

Ry Zy

Vz

Fig. 2. Equivalent model of a CC.

VDD M10

M9

M8

M1

M7

M2

Y

X

Z

I0 M3

M13

M12

M4

M11

M5

M6 VSS

Fig. 3. A conventional translinear loop based CMOS CCII+ [6].

PMOS transistor. For all NMOS transistors, we have considered identical WN and LN values because these NMOS transistors are all identical. Similarly for all PMOS transistors, we have considered identical WP and LP values, because these PMOS transistors are all identical. KN, KP, and VTP are the technology parameters. VDD is the DC voltage power supply. 2.2. Component objective functions

 RX: the value of the X-port input parasitic resistance (to be minimized) is given as RX 



1 gm2 þgm4

ð4Þ

For our system we could achieve satisfactory performance with the first choice of parameters a ¼ b ¼1. The suitable expression of fci is obtained for the system by employing a symbolic analyzer [16] and the expression contains large number of terms. Because of the presence of these large number of terms, the explicit expression of fci is not given here.

Rz

Zz

real CC

to minimize is configured as   1 fobj ¼ a þ bRX fci

ð3Þ

where gm stands for the transconductance of the corresponding MOS transistor. fci: the highest cut-off frequency for current (to be maximized).

As our objective is to simultaneously minimize Rx and maximize fci and since both these quantities are essentially positive, we configure the optimization problem as a bi-objective optimization problem and the optimization problem is solved as a minimization problem. Here the objective function that we desire

3. The bacterial foraging optimization (BFO) algorithm According to foraging theory, the animals search for and obtain nutrients in such a fashion that the energy intake per unit time is maximized, so that the animals get enough nutrient sources to survive and, at the same time, they can have spare time for other activities [9]. Hence, it is well-known that those animals which have poor foraging capability, get eliminated and those animals which have strong foraging capability, have their genes propagated for further reproduction procedure. An analog of this foraging problem has been formulated as an optimization problem by employing optimal foraging theory, to propose a new evolutionary optimization algorithm [9,17,18]. The idea is to biomimic the foraging behavior of a common type of bacteria, E. coli, popularly known as E. Coli [18]. The movement of a E. Coli bacterium in a three-dimensional space is usually characterized by alternate phases of running and tumbling. The basic difference lies in the fact that in actual bacterial scenario the bacterial population is of about 109 and the number of directions they traverse is that of a three-dimensional space. But when an analogous optimization algorithm, based on bacterial foraging behavior, is developed, the simulated population is usually much smaller and the dimension of the problem is very often more than three. This optimization procedure comprises four basic steps: (i) chemotaxis, (ii) swarming, (iii) reproduction and (iv) elimination and dispersal. The optimization technique consists of determining the minimum of a function J(y) in a high-dimensional space, where y denotes the position of a bacterium in that high-dimensional space. Fig. 4 presents the entire algorithm in a concise form [9,19]. Step I: chemotaxis step: In this step, each bacterium either experiences a tumble followed by another tumble or a tumble followed by a run. Let yi ðj,k,lÞ A Rp represents ith bacterium (i¼ 1,2,y, S) in jth chemotactic, kth reproduction and lth elimination–dispersal step. Let J(i,j,k,l) represent the cost associated with this position of the bacterium. The new position of a bacterium in the chemotaxis step is given as

yi ðj þ 1,k,lÞ ¼ yi ðj,k,lÞ þ CðiÞjðjÞ

ð5Þ

where j(j) denotes a unit length random direction to represent the tumble and determine the future direction of movement and

A. Chatterjee et al. / Microelectronics Journal 41 (2010) 616–626

________________________________________________________________________

________________________________________________________________________ Fig. 4. The bacterial foraging optimization (BFO) algorithm [9,19].

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C(i) denotes the run-length, i.e. chemotactic step size. If the cost J at yi(j+ 1,k,l) gets lower and lower than the cost at just the preceding position i.e. yi(j,k,l), then the bacterium will keep taking successive steps in that direction. However, the bacterium is not allowed to take indefinite number of successive steps in the same direction, if the cost value keeps getting lower and lower. This movement in the same direction is constrained by a parameter called maximum number of permissible successive steps, Ns. Hence according to the models developed for the chemotactic actions of the bacteria [18], if in a neutral medium, a bacterium shows alternate phenomena of tumbling and running, this phenomenon is similar to the criterion of search. Similarly, a swim up the nutrient gradient or a long duration of swim indicates that the bacterium is seeking to move to more and more favorable environments. On the other hand, a search phenomenon of avoiding unsuitable environments is characterized by a swim down a nutrient gradient. Step II: swarming step: In this step, the attraction–repulsion behavior of a group of E. coli cells swimming together is modeled. Here cell-released attractants are employed by each cell to signal other nearby cells to swarm with it. At the same time, the same cell can repel a nearby cell by consuming nearby nutrients and two cells cannot simultaneously physically be present at the same location. This combined cell-to-cell attraction and repelling effect is given by " !# p S S X X X i i i Jcc ðy, y ðj,k,lÞÞ ¼ dattract exp wattract ðym ym Þ2 i¼1

þ

m¼1

i¼1 S X i¼1

hrepellant expðwrepellant

p X

i

ðym ym Þ2 Þ

ð6Þ

m¼1

This quantity is added to the actual cost value J (to be minimized) and this presents a time-varying nature for J. Step III: reproduction step: In this step, the bacteria population is sorted in ascending order of accumulated cost and the 50% of least healthy bacteria die and each of the remaining 50% healthier bacteria split into two bacteria, such that each two child bacteria thus reproduced are placed at the same location. Step IV: elimination–dispersal step: In this step, each bacterium is subjected to elimination-dispersal with a probability of ped, where the bacterium may be dispersed into an unexplored region of environment or search space. While this may destroy the progress achieved through the chemotactic process thus far, it may happen that the bacterium may find itself closer to new source of nutrients. After every Nc chemotactic steps are completed, one reproduction step is undertaken and after Nre reproduction steps are completed, one elimination–dispersal step is undertaken. Like most other stochastic optimization algorithms, the performance of the BFO algorithm too depends on the judicious choice of its free parameters. Among these free parameters, the parameters of the chemotactic steps are very important because this step is implemented many times compared to reproduction and elimination–dispersal steps. Here, C(i), the step size, plays a role very similar to that of the learning rate in a neural network. For a small value of C(i) the convergence will get slow but once it finds a local minimum, it is very likely to stick to it. On the other hand, a high value of C(i) means that the algorithm will take too big jump in every iteration and there is every possibility that it may miss local minima [9]. Another factor is Nc, which determines the number of chemotaxis steps and also plays a crucial role. Usually for a small value of Nc the result depends more on chance, whereas higher values of Nc ensure that the optimization progress takes place, as desired, with added computational burden. The third very

important free parameter is Ns. Usually a small value of Ns provides good performance by providing a bias in the random walk. However, too high value of Ns should be undesirable as it will produce too much bias in a given direction for the random walk and the algorithm may loose the essence of its stochastic behavior.

4. Performance evaluation The optimum values for the physical dimensions of the MOS transistors i.e. WN and LN values for each NMOS transistor and WP

Table 1 Design parameters obtained for the CCII along with associated optimum parameters of the objective function, by employing BFO for five sample runs, with bias current kept fixed at I0 ¼50 mA. Run no.

LN (mm)

WN (mm)

LP (mm)

WP (mm)

fci (GHz)

RX (ohm)

#1 #2 #3 #4 #5

0.55 0.58 0.58 0.55 0.58

7.88 7.62 7.98 7.83 7.72

0.35 0.35 0.35 0.35 0.38

12.96 12.17 12.62 12.82 12.68

1.2432 1.2255 1.1967 1.2454 1.1625

857 880 860 860 891

Table 2 Design parameters obtained for the CCII along with associated optimum parameters of the objective function, by employing BFO for five sample runs, with bias current kept fixed at I0 ¼100 mA. Run no.

LN (mm)

WN (mm)

LP (mm)

WP (mm)

fci (GHz)

RX (ohm)

#1 #2 #3 #4 #5

0.53 0.54 0.54 0.55 0.53

7.73 7.89 7.94 7.90 7.84

0.35 0.35 0.35 0.35 0.35

12.78 12.64 12.60 12.73 12.84

1.8129 1.7757 1.7726 1.7582 1.8074

608 603 601 605 602

Table 3 Design parameters obtained for the CCII along with associated optimum parameters of the objective function, by employing BFO for five sample runs, with bias current kept fixed at I0 ¼150 mA. Run No.

LN (mm)

WN (mm)

LP (mm)

WP (mm)

fci (GHz)

RX (ohm)

#1 #2 #3 #4 #5

0.56 0.57 0.55 0.56 0.58

11.82 11.75 11.76 11.86 11.66

0.36 0.35 0.36 0.35 0.36

19.36 18.38 19.41 19.44 18.97

1.6993 1.7155 1.7304 1.7362 1.6741

409 409 408 405 414

Table 4 Design parameters obtained for the CCII along with associated optimum parameters of the objective function, by employing BFO for five sample runs, with bias current kept fixed at I0 ¼200 mA. Run no.

LN (mm)

WN (mm)

LP (mm)

WP (mm)

fci (GHz)

RX (ohm)

#1 #2 #3 #4 #5

0.55 0.54 0.57 0.53 0.54

15.67 15.85 15.83 15.21 15.44

0.35 0.35 0.35 0.35 0.35

25.31 25.47 24.76 25.27 25.08

1.7574 1.7866 1.7185 1.8464 1.7989

304 300 304 305 305

A. Chatterjee et al. / Microelectronics Journal 41 (2010) 616–626

and LP values for each PMOS transistor are obtained for a series of bias current i.e. I0 values. For our simulations, the technology under consideration is CMOS AMS 0.35 mm, voltage supply

Table 5 Design parameters obtained for the CCII along with associated optimum parameters of the objective function, by employing BFO for five sample runs, with bias current kept fixed at I0 ¼ 250 mA. Run no.

LN (mm)

WN (mm)

LP (mm)

WP (mm)

fci (GHz)

RX (ohm)

#1 #2 #3 #4 #5

0.55 0.55 0.54 0.53 0.54

15.81 15.76 15.80 15.42 15.50

0.35 0.35 0.35 0.35 0.35

25.47 25.47 25.28 25.65 25.89

1.9638 1.9600 1.9911 2.0363 2.0129

270 271 269 272 272

Table 6 Design parameters obtained for the CCII along with associated optimum parameters of the objective function, by employing BFO for five sample runs, with bias current kept fixed at I0 ¼ 300 mA. Run no.

LN (mm)

WN (mm)

LP (mm)

WP (mm)

fci (GHz)

RX (ohm)

#1 #2 #3 #4 #5

0.53 0.52 0.53 0.53 0.53

17.86 17.51 17.93 17.95 17.95

0.35 0.35 0.35 0.36 0.35

29.86 28.98 29.30 29.76 29.71

2.0677 2.1218 2.0657 2.0395 2.0654

231 232 230 231 230

621

specification is  2.5 V/+ 2.5 V. The set of bias currents considered is I0A[50,100,150,200,250,300] mA. Tables 1–6 show the optimal design parameters, i.e. the optimal physical dimensions obtained for the CCII, along with the associated optimum values obtained for the parameters considered in the objective function i.e. RX and fci, by employing BFO algorithm, for six different values of I0 under consideration in each case. Like all other stochastic optimization algorithms, the performance of BFO algorithm too depends on random initialization of the candidate solutions at the beginning of its implementation. Hence, for each case under consideration, the BFO algorithm is implemented for five sample runs and each table reports results obtained for each of these five runs for each such case. Then, the best performing run is shown in bold to highlight the best results obtained. To verify these results obtained using BFO algorithm, we implemented SPICE simulations for the CCII model under consideration, with optimal parameters determined using the best performing BFO algorithm, in each of these six cases, and obtained the exact values of RX and fci, which we should expect to obtain, if the CCII+ configuration is physically realized with those corresponding optimal physical dimensions of those NMOS and PMOS transistors. Also, to provide a proper comparison of these results obtained by using BFO algorithm, the results should be compared with similar competing stochastic optimization algorithms that can be potentially employed for solving this problem. We conducted similar simulations using two contemporary, popular, stochastic optimization algorithms called particle swarm optimization (PSO) algorithm and differential evolution (DE) algorithm. Tables 7 and 8 show comparisons of the best results obtained with BFO algorithm vis-a -vis the PSO algorithm and the

Table 7 A comparison of best results obtained with BFO algorithm vis-a -vis PSO algorithm for different operational conditions. Sl. no.

I0 (mA)

1.

50

2.

100

3.

150

4.

200

5.

250

6.

300

Results from Performance Conditions

Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations

Algorithms Algorithms Algorithms Algorithms Algorithms Algorithms

fci (GHz)

RX (ohm)

BFO

PSO [10]

BFO

PSO [10]

1.245 1.228 1.812 1.629 1.736 1.581 1.846 1.639 2.036 1.772 2.121 1.825

0.866 0.840 1.802 1.620 1.721 1.564 2.027 1.774 1.940 1.750 2.042 1.788

860 1044 608 815 405 546 305 410 272 377 231 324

1376 1821 633 848 435 597 338 471 272 382 230 324

Table 8 A comparison of best results obtained with BFO algorithm vis-a -vis DE algorithm, for different operational conditions. Sl. No.

I0 (mA)

1.

50

2.

100

3.

150

4.

200

5.

250

6.

300

Results from Performance Conditions

Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations Direct Results from Optimization Results from SPICE Simulations

Algorithms Algorithms Algorithms Algorithms Algorithms Algorithms

fci (GHz)

RX (ohm)

BFO

DE

BFO

DE

1.245 1.228 1.812 1.629 1.736 1.581 1.846 1.639 2.036 1.772 2.121 1.825

1.184 1.181 1.729 1.543 1.735 1.569 1.686 1.543 2.006 1.763 2.055 1.748

860 1044 608 815 405 546 305 410 272 377 231 324

865 1060 607 821 406 548 305 413 273 382 232 324

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DE algorithm, respectively, for the same operational conditions. The comparison in result is presented for both the situations, where (i) results of RX and fci are obtained directly from the optimization algorithm and (ii) results of RX and fci are obtained from SPICE simulations, utilizing CCII + models with optimal sizes determined from the optimization algorithm. Figs. 5 and 6 show the SPICE simulation results for the variation of current gain Iz/Ix (in dB) with frequency, for the CCII + model, with optimal sizes

determined from both the competing optimization algorithms, with sample I0 values of 50 and 300 mA. Figs. 7 and 8 show the corresponding SPICE simulation results for the variation of RX with frequency, for the same CCII + model, with the same optimal sizes determined from all the competing optimization algorithms, with sample I0 values kept same, i.e. 50 and 300 mA. A careful study of Table 7 reveals that for direct results obtained using optimization algorithms, for four I0 conditions of

15 -0

-20

-40 -55 1.0KHz

10KHz

100KHz

1.0MHz

10KHz

100KHz

1.0MHz

10MHz Frequency

100MHz

1.0GHz

10GHz

10MHz

100MHz

1.0GHz

10GHz

15 -0

-20

-40 -55 1.0KHz

Frequency 15 -0

-20

-40 -55 1.0KHz

10KHz

100KHz

1.0MHz

10MHz

100MHz Frequency

1.0GHz

10GHz

Fig. 5. SPICE simulation results, for the I0 ¼ 50 mA case, showing variation of current gain Iz/Ix (in dB) vs. frequency for the optimal sizing suggested by (a) BFO, (b) PSO, and (c) DE algorithm.

A. Chatterjee et al. / Microelectronics Journal 41 (2010) 616–626

623

15 -0

-20

-40 -55 1.0KHz

10KHz

100KHz

1.0MHz

10MHz

100MHz

1.0GHz

10GHz

10MHz Frequency

100MHz

1.0GHz

10GHz

10MHz

100MHz

1.0GHz

10GHz

Frequency 15 -0

-20

-40 -55 1.0KHz

10KHz

100KHz

1.0MHz

10KHz

100KHz

1.0MHz

15 -0

-20

-40 -55 1.0KHz

Frequency Fig. 6. SPICE simulation results, for the I0 ¼ 300 mA case, showing variation of current gain Iz/Ix (in dB) vs. frequency for the optimal sizing suggested by (a) BFO, (b) PSO, and (c) DE algorithm.

50, 100, 150, and 250 mA conditions, BFO could attain simultaneously better results for both RX and fci i.e. it attained lower RX and higher fci values, when compared to the performances attained by the PSO algorithm. For an I0 condition of 200 mA, BFO could attain a lower value of RX compared to the PSO algorithm, however, PSO was successful in attaining a higher fci value compared to BFO. For an I0 condition of 300 mA, PSO could attain a lower value of RX compared to the BFO algorithm,

although the difference was almost negligibly small. On the other hand, BFO was successful in attaining a higher fci value compared to PSO. Hence when we compare direct results obtained using optimization algorithms, BFO has, in most cases, outperformed PSO algorithm. A similar trend in results could be observed when compared with the DE algorithm, as shown in Table 8. Here, for direct results, in each case, BFO algorithm could achieve a higher fci value compared to DE. In case of the value of RX, in almost all

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A. Chatterjee et al. / Microelectronics Journal 41 (2010) 616–626

1.2K

0.8K

0.4K

0 1.0KHz

10KHz

100KHz

1.0MHz

10MHz Frequency

100MHz

1.0GHz

10GHz

100MHz

1.0GHz

10GHz

100MHz

1.0GHz

10GHz

2.0K

1.0K

0 1.0KHz

10KHz

100KHz

1.0MHz

10MHz

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cases BFO and DE produced comparable results, except only in case of I0 ¼50 mA, when BFO could clearly achieve a smaller value compared to DE algorithm. Hence it can be inferred that BFO has mostly outperformed DE algorithm too. A similar trend in results is visible when we compare the results obtained by performing SPICE simulations, utilizing optimal sizing of physical MOS transistors, obtained from competing optimization algorithms. In this situation also, for four I0 conditions of 50, 100, 150, and 250 mA conditions, BFO could

attain simultaneously better results for both RX and fci, when compared to the performances attained by the PSO algorithm. Here also, for an I0 condition of 200 mA, BFO could attain a lower value of RX compared to the PSO algorithm and PSO was successful in attaining a higher fci value compared to BFO. For an I0 condition of 300 mA, BFO was successful in attaining a higher fci value compared to PSO and both BFO and PSO produced same values of RX. Hence, for these sets of results also, BFO has largely outperformed PSO algorithm. Over all, all these sets of results

A. Chatterjee et al. / Microelectronics Journal 41 (2010) 616–626

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Fig. 8. SPICE simulation results, for the I0 ¼300 mA case, showing variation of RX (in ohm) vs. frequency for the optimal sizing suggested by (a) BFO, (b) PSO algorithm, and (c) DE algorithm.

aptly demonstrate the utility of BFO algorithm in determining optimal sizing of second generation current conveyors, which can lead to enhanced performance in obtaining satisfactory higher fci value and lower RX value. When the results of SPICE simulations of circuits designed utilizing optimal sizing of physical MOS transistors, obtained from BFO and DE algorithms, were compared, it was found that BFO could comfortably outperform DE in obtaining a higher fci value and a lower RX value in all cases except for the situation with I0 ¼300 mA, when both BFO and DE

algorithms obtained the same RX value. Hence these results reiterate the utility of using BFO algorithm in obtaining optimal sizing of CCII + parameters, compared to PSO and DE algorithms.

5. Conclusion In this work, we have successfully demonstrated how CMOS positive second generation Current Conveyors (CCII +) can be

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optimally designed for enhanced performance. The design is directed to simultaneously minimize the parasitic X-port input resistance (RX) and maximize the high end cut-off frequency of the current signal (fci). The problem is solved using bacterial foraging optimization (BFO) algorithm, a recently developed nongradient type stochastic optimization algorithm. This algorithm solves a bi-objective optimization algorithm, to obtain the optimal physical dimensions of the constituent PMOS and NMOS transistors of a CCII +. A series of simulation experiments, conducted for several bias currents (I0), effectively demonstrated that the proposed algorithm could produce satisfactorily better results in comparison to the results produced by the PSO algorithm in [10] and the DE algorithm. For comparing the performances of the optimal sizing design algorithms, for each set of optimal parameters determined from each optimization algorithm, the simulation testing has been carried out using SPICE, so that a uniform platform could be used for simulation testing of performances of competing algorithms. However, it should be noted that it is preferable to test the new CCIIs with a CAD system suitable for electronic circuits operating above 100 KHz, because the SPICE software may not be appropriate for simulation of circuits at 1 GHz and above, because they do not consider many parasitic effects. However, if such a CAD system is considered for simulation testing of all designs, then all such designs should get theoretically affected by identical inclusion of parasitic effects, and hence it is expected that, for such a uniform simulation platform chosen, BFO will again emerge to provide the winning solution among competing algorithms. Another interesting aspect will be to build sample circuits using CCIIs, designed by employing BFO and other competing algorithms. This will help to demonstrate the effectiveness of the proposed method for sizing CCIIs in real practice. The authors wish to undertake this research in near future and would like to focus on that implementation work in a future research paper.

Acknowledgements Amitava Chatterjee was with Laboratoire Images, Signaux et Syste mes Intelligents (LiSSi, EA 3956), Universite´ Paris XII Val de Marne, 61 avenue du Ge´ne´ral de Gaulle, 94010 Cre´teil, France, as an Enseignant Invite´ (Invited Teacher), when this work was performed. He was on leave from Electrical Engineering Department, Jadavpur University, Kolkata 700032, India.

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