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Design of shift register delays for random asynchronous data input
NUCLEAR
INSTRUMENTS
AND METHODS
lO 3 (i972) i57-165; ©
NORTH-HOLLAND
PUBLISHING
CO.
DESIGN OF S H I F T REGISTER DELAYS FOR RANDOM ASYNCHRONOUS DATA INPUT* K. G. P O R G E S and S. J. R U D N I C K
Argonne Nattonal Laboratory, 9700 South Cass Avenue, Argonne, llhnots 60439, U S.A. Received 4 April 1972
The utdmatlon of shift registers for purposes of providing fixed and stable delay m nuclear data processing IS illustrated here by two specific apphcatlons, one requiring delays of the order of seconds and the other reqmring delays in the microsecond range. In the first case considered, the chief problem Is to prowde the capability of handling large random rates without undue digital dropout loss, in a dewce which does not reqmre an excesswe number of shift register bits. The solution proposed is a combma-
hon of cychcally operated parallel tracks with derandomizers. In the second case the required delay can be produced with a relatwely modest number of bits, but the problem to be overcome is the hmited time resoluuon of the device, determined by the minimum shifting period This is shown to be amenable to amprovement through a staggered shifting system which allows a subdwlSlOn of the shift period.
1. Introduction The increasing availabihty of shift registers of large capacity and high speed, promoted by MS[ and LSI fabrication techniques, suggests their use in connection with a number of nuclear count processing systems which require a fixed delay. Compared to other available means of obtaining such a delay, shift registers can claim superior long-term stabihty, freedom from maintenance or recalibration requirements, insensitivity to temperature and other environmental factors, and versatility. On the other hand, shift registers used with high random input rates are subject to digital dropout loss, and the inherent time cesolution of + (1/J'), where f=shift frequency, becomes a drawback in some applications. Both these problems diminish as the shift frequency is increased. Maintaining a specified delay while increasing the shift frequency, however, calls for increasing the number of bits m the shift register commensurately. Thts may make the unit prohibitively expensive, even when MSI units currently selhng for a few cents per bit are used. Moreover, the maximum guaranteed frequency for currently available MS[ units is about 20 MHz. These problems can be alleviated by certain stratagems, described in this report. By arranging parallel shift register tracks and adding appropriate derandomizing circuitry, the number of bits required to obtain a certain delay at specified dropout level can be reduced by an order of magnitude. In another arrangement, also involving parallel tracks, the time resolution can be made smaller than 1If. The schemes are illustrated through two specific applicauons, in which other means of producing the * Work performed under the auspices of the U.S. Atomic Energy Commission.
required delay have been employed in existing systems. Replacement of these delays by shift registers would not necessarily improve the short-term performance of the systems, but would eliminate maintenance and cahbration problems. Maintenance problems are particularly serious in safety and surveillance instrumentation designed to detect a rare transient in the count rate of a detector channel, indicating some malfunction or failure which must be coped with expeditiously. If such channels are not highly reliable, they may either result in an intolerably high level of false alarms or turn out to be msufficiently sensitive when a real incident occurs; moreover, the record of such a transient can be so distorted as to render diagnosis of the trouble inconclusive. The following section describes the application of a shift register delay to this kind of instrumentation. The required delay amounts to several seconds, which strongly emphasizes the need to design the system for economy in shift register bit number. Other applications where delays must remain highly constant over long periods occur in fast coincidence systems and time-of-flight acquisition systems. Such measurements are usually made under conditions which make digital dropout a lesser problem than resolution; at the same time, the total delay required is usually small enough to de-emphasize the need to design for minimum number of shift register bits. A shift register delay with improved t~me resolution is described in the third section of this report. 2. Application of digital delay in an excursion monitor channel A practical application of a digital delay amounting to the order of seconds is based on the operational 157
158
K. G. P O R G E S A N D S. J. R U D N I C K
characteristics of certain surveillance channels employed in nuclear reactor plants or similar installations, e.g., fuel reprocessing plants. In these plants one finds a number of nuclear detector channels each of which normally delivers a count rate at some background level. As the result of some malfunction or failure m the plant, transients may appear in the count rate. The intensity and shape of the transients, in conjunction with other information, can be used to diagnose the trouble and must therefore be recorded. The customary technique of obtaining a continuous channel count rate record is to convert counts into an analog current by means of a count rate meter circuit; the current is used, in turn, to drive a recording device such as a chart recorder. Normally the chart recorder would run at, say, 0.5 in./min or 60 ft/24 h. This corresponds to a tolerable paper consumption rate and still produces a readable record of transients lasting several minutes. However, the type of transients described above may build up in or last rather less than a second. To be able to make any references from the shape of the record, the paper feed rate would thus have to be stepped up to something like 1 in./s, which evidently cannot be maintained continuously but must be actuated by the transient itself. The speed-up time of suitable chart recorders, viz, oscillographs, amounts to more than one second, moreover the unit which trips the system, of whatever design, can only act when the transient has reached some distance from the normal background level and thus inevitably misses the imtial rise. These two considerations call for temporary information storage of the order of a few seconds, which is most readily implemented by direct digital storage of counts. A system of this description was developed for a fuel element rupture detector (FERD) system, installed in the EBR-I[ plant~). The outputs of several neutron detection channels were directly written on a continuous magnetic tape loop 2) and read out by another head after substantial delay. In continuous use, however, the tape transport developed serious wear problems. Such difficulties are clearly avoided by the substitution o f a shift register delay. However, to provide a practical shift register delay unit at competitive cost, particularly for systems which employ a number of detector channels, reduction of the required number of shift register bits is essential. A shift register delay of reasonable cost can also effectively complement more sophisticated means of information storage such as an on-line computer. Of course, given sufficient capacity the computer itself could perform all necessary functions including temporary storage. In practice, the cost of using the computer
in this way must be compared to the cost of providing shift register units for temporary storage and reserving the computer for permanent storage and other on-line tasks. The performance requirements for a typical excursion monitor may be summarized as follows: a) delay: up to several seconds, allowing for the delayed triggering of the alarm, providing a record of background just ahead of the transient for reference, and possibly allowing for paper feed speedup of a chart recorder; b) time resolution: 2 ms, to record the detailed structure of the transient; c) input rate: background 10-100 cps; transients up to l 0 3 cps; d) maximum dropout loss: 5% should be acceptable at peak input rate; 10% may not be excessive, however, in conjunction with a correction program calculating input from the record. The remainder of this section addresses itself to the task of determining how these specifications can be met at minimum cost. Shift register delays, scalers, and magnetic tape recorders all develop digital dropout losses in conjunction with random input. The reduction of such losses by cychc switching between tracks was described in detail in a previous publication concerned with scalers or direct digital magnetic tape recording3). We shall develop similar formulae for shift register delay, where a somewhat different s~tuation obtains: for a scaler, a fixed deadtime follows every count, while a shift register delay can record at most one input per shift period 1/f. To avoid unnecessary complexity we shall neglect the additional losses which occur in practice due to the deadtime of the circuitry ahead of the shift register. As a first task, we consider the dropout loss for the single shift register channel shown in fig. 1. For the moment we shall ignore the derandomizer circuit shown to the left of the dotted line; the rest of the circuit is a schematic of an elementary shift register delay including a buffer 4' 2). The buffer ensures that each random input introduces one and only one pulse into the shift register during its live time and blocks all inputs between the first arrival and the end of a given shift period. The clock drives the shift register at a regular frequency f, resulting in a delay Td=m/f, where m = number of bits. The mean input rate n, considered here as a fixed parameter, determines the mean fraction n/f= N of the register capacity occupied by counts in the absence of dropout loss. Let c = output rate and
SHIFT REGISTER
DELAYS FOR RANDOM
ASYNCHRONOUS
SHIFT REGISTER
BUFFER
RANDOM INPUT F ~
159
DATA INPUT
~
+SV
I
B
;
ITS MS, OR LSI
DELAYED SERIAL ,I ~ ^ ,OUTPUT ~ OUT I
I'-'--I~-
i ._J
L_
DERANDOMIZER
JOE ~t.=J ZN
a~
CLOCK
Fig. l. Shift register delay s h o w i n g i n p u t buffer a n d d e r a n d o m l z e r to reduce losses at high r a n d o m i n p u t rates, as explained m the text.
Pk = e-N(Nk/k!); then the rate at which inputs are lost in the shift register comes to
(n--c) = f ~ P k ( k - 1 ) ,
(1)
k=2
inasmuch as k - l inputs are dropped whenever exactly k inputs appear in a shift duration lff. Rearranging eq. (1), we find the fractional loss 11 for a single track,
ll = [(n--c)/n]l = (1 --e-N)--(Q/g)e -N,
(2)
where we have put
Q(N) = eN--(1 + N ) = ½N2(1 + ~ N + ~-~-N2 +...).
(3)
As n is considered a fixed parameter and Td is also specified, eq. (2) can be used to calculate the minimum number of shift register bits m required to keep dropout loss to a specified level; the frequencyfis thereupon determined by the required delay. For example, one finds that for n-----10 3 and Td=2 s, some 2 x 104 bits must be provided to keep drop out loss under 5%. This makes for a rather expensive system, offering a time resolution of 0.1 ms, considerably better than strictly required. Time resolution can be traded for a smaller bit
number by providing several parallel shift reg]ster tracks. While it might appear at first blush that such paralleling of tracks would require even more bits, it will be shown that in fact the loss per bit is dramatically reduced, owing to an effect which is the equivalent of the "regularizing" action of scalers3). Similar considerations apply to cyclic distribution of random input on magnetic tape z' 3). A two-track shift register delay is shown in fig. 2. The input is applied to a simple bmary distributor which sends alternate pulses to the two buffers; a single clock drives both tracks synchronously. The outputs must be recombined out of phase as pulses present in both tracks would otherwise overlap and result in a single output. Alternatively the tracks could be driven out of phase. It may be noted that the performance of a multitrack shift register delay is equivalent to that of a multiscaler which has a maximum capacity per scaler equal to the number of tracks. Either system tends to group pulses, thus losing time resolution. For two tracks, the fractional counting loss comes to
12 = ~ ( k - 2 ) P k / N = l x - ( Q / N ) e -N,
(4)
k=2
l~ = l, -1 -- (Q/N) e-N + (e-N/2N) ×{½N2+...[NJ-1/(j--1)!]}.
(5)
K. O. PORGESANDS.J. RUDNICK
160 BUFFER I
SHIFT REGISTER I OUTPUT GATES
I
DISTRIBUTOR
B,TS
I
I
MS,OR ,
1
I~
I
__~CLOCK
I ,N RANDOM
~
U2_
DELAYED T
__1
I
BUFFER 2
SHIFT REGISTER 2
0
r I
(~-,) B,TS
I
MS, OR,S,
I
ss
I
m
Td = ~
+
150 ~+l/f
/-I/Oaf )
Fig. 2. Shift register delay using two-track distribution for the purpose of reducing losses at high random input rates.
To illustrate the general dependence of dropout loss on the parameter N, which amounts to the duty cycle of the shift register delay, eqs. (2), (4) and (5) have been plotted against a representative range of values for N, in fig. 3. These plots, similar to plots for cyclic distribution of random counts between parallel tracks of scalers3), exhibit asymptotic approach to unity for large values of N; for small N, each curve approaches the leading term of the expansion, NJ/(j + 1)!. It may be noted that a single track, in order not to exceed 10% dropout loss, must keep N smaller than about 0.2, whereas two parallel tracks can tolerate N values five times larger at comparable loss. On the other hand, the use of increasing numbers of parallel tracks tends to produce an increasingly modest relative improvement. The effect of this on overall economy of design is more directly shown if one considers Ta and n as
specified parameters and plots the minimum total number of shift register bits m t (including all tracks) which would be required to keep losses below specified limits of 1%, 5% and 10%. This is done in fig. 4 in which the ratio m t / n T d i s plotted against the number of parallel channels j. In practical terms a delay of 2 s = Td, input rate of 103=n and maximum dropout of 5%, would require some 20 k bits in a single track system, but only 6 k bits in two tracks, or 3 k bits per track, when the system depicted in fig. 2 is used. Distribution amongst four tracks reduces this further to 3.6 k, or 900 per track. At the same time, however, the digital time resolution r = 1/f=jTd/mt decreases. For six tracks, for example, the 5% dropout level is reached with 2.7 k bits or 450 bits per track, hence 4.4 ms time resolution. This may be adequate for some transient records but not for others. I f one further
SHIFT REGISTER DELAYS FOR RANDOM ASYNCHRONOUS DATA INPUT
10
I
,
I
I'
L,,
I
161
probability w o f finding the derandomizer store empty at the time a particular shift occurs:
I
w = (P0 + P J ) w + Po(1 - w).
(6)
Rearranging and using eq (3), we obtain w = (1 + Q ) - I .
The fractional loss lid for one channel equipped with derandomizer thus comes to
01
t,d = ~')
) z
w X
[&(k-2)/N]+(1-w)
k=2
I
03
•2).
(8)
According to eq. (8) one would expect the loss to lie between that for the track without derandomizer, and that appropriate for a two-track system as described above. A plot o f eq. (8), presented in fig. 5, confirms this; eq. (8) is plotted as curve A, while the fractional losses for various numbers o f multiple channels are replotted from fig. 3 as broken lines. Below the 10% level, the loss o f a single channel equipped with derandomizer is only slightly larger than the corresponding loss for a two-track arrangement at the same number N. Thus, the derandomizer channel can produce a certain
COl~!
i 02
Y~ [ & ( k - 1 ) / N ]
k=3
= 11 - w ( l l -
0 301 OI
(7)
04
05
I0
15
20
~5
N
Fig. 3. Fractional loss 13=[(n-c)/n]j against N = n / f for J=l through j = 6 parallel tracks, n=random input rate, f=shlft frequency, c = output rate.
takes into account the cost o f the additional circuitry reqmred to distribute inputs and recombine outputs, it appears that a four-track system, easily implemented with three binary stages in the distributor, is about as far as practical systems may reasonably go. This concluslon is strengthened by the posslbihties inherent in derandomlzers6'7), which we shall now discuss. A derandomizer suitable for present purposes is shown in fig. 1 to the left of the broken hne; the schematic also suggests how one m a y add further stages, to provide second or higher-order dewces. One can then further combine derandomizers and multltrack distribution to obtain the most economical overall system. As indicated in fig. 1, the action o f the derandomizer is to hold the second input arriving within a given shift interval, and to release this at the beginning o f the next interval. I f no input arrives during that interval, the derandomizer has merely shifted registration o f one input by one shift period. If the following interval receives one input, the latter is again shifted; if two inputs, the second input is dropped. F r o m this description we can put down the a priori
5 -/= OI
E ~, 05
--1 ./=10
] _ _
I I
I 2
I 3
[ - -
I 4
i 5
6
J
Fig. 4. Number of bits mt required in all per unit nTd (Td= reqmred delay, n=random input rate), for j = l through ] = 6 parallel tracks, and fractional loss lj=0.01, 0.05 and 0.10, respectively.
162
K. G. P O R G E S A N D S. J. R U D N I C K
bability that b o t h stores are full. One readily deduces the relations
I0
(9)
w l = w l ( P o + P I ) + w2Po,
(10)
w2=wxPz+w2Pl+(1-wj-w2)Po,
and P1 -- P2) P1) + ( 1 - w l - w z ) (
(1 - - w l - - w 2 ) = w l (1 - - P o -
OI
+wz(1 - P o -
1-Po)"
(11)
Solving for Wl a n d wz a n d i n t r o d u c i n g again eq. (3), we find that
001
w l = [ ( Q + 1) 2 - ½ N 2 ] -1,
(12)
w2 = QWl.
(13)
The fractional loss with single t r a c k a n d d o u b l e der a n d o m i z e r , llad, thus becomes
ljdd
= w113 + w212 + (1 - w 1 -- W2)[ 1 = l~-Qwl(ll-12)-wl(lx-13).
015
02
05
N
I
15
2
3
(14)
This is clearly seen to lie between I s a n d /3, as again confirmed b y fig. 5 in which eq. (14) is p l o t t e d as curve B. The n u m b e r o f bits required for specified
Fig. 5. Fractional loss ly for certain combinations of derandomlzers and parallel tracks Losses for parallel tracks without derandomlzers are redrawn from fig. 3 as broken lines, for j--1,2,3,4 and 6. Curve A (lla): single track w~th one derandomizer stage; curve B (haa) single track wxth two derandomizer stages; curve C (12a): two parallel tracks with one derandomlzer stage on each track; curve D (12aa): two parallel tracks with two derandomizer stages on each track. Note that curves A and B converge to 1 = 1 at high values of n / f whereas curves C and D approach j = 2 at high rates; for low rates A approaches ./=2, B aproaches j = 3 , C approaches j = 4 and D approaches j = 6 .
(a)
(b) I
- - ( 1 = 05from fig 4) --
I I I I
---
I
I I
X: OI
i
5
I I I
--
I
d r o p o u t level with a p p r o x i m a t e l y o n e - h a l f to twothirds o f the total n u m b e r o f bits which w o u l d be r e q u i r e d for the split t r a c k system, a n d is therefore clearly superior. T h e relative n u m b e r o f bits req u i r e d for 1%, 5% a n d 10% d r o p o u t has again been p l o t t e d as a b a r g r a p h in fig. 6(a), with c o r r e s p o n d i n g n u m b e r s for 5% d r o p o u t m a system w i t h o u t d e r a n d o mizer d r a w n as a b r o k e n line. T o i m p r o v e p e r f o r m a n c e still further, we m a y a d d a n o t h e r stage to the d e r a n d o m i z e r as suggested in fig. 1. The second store is used only when the first store is full b u t has p r i o r i t y in releasing its contents to the shift register. Let Wl = p r o b a b i l i t y t h a t b o t h stores are e m p t y at the time a p a r t i c u l a r shift occurs a n d w2 = p r o b a b i l i t y that the first store is full a n d the second store e m p t y ; then 1 - W x - w2 -- c o m p l e m e n t a r y p r o -
I
q
,
./= 05
Ol 2
./:
I0
'
II
.
m l=
I
2
I I
2
Fig. 6 Number of shift register bits mt required in all per unit nTd for (a) one and two parallel tracks wlth single derandom]zer
per track and (b) one and two parallel tracks with double derandom~zer on each track.
S H I F T R E G I S T E R DELAYS FOR R A N D O M A S Y N C H R O N O U S D A T A I N P U T
dropout levels of 1%, 5% and 10% is shown in fig. 6(b). The required number of bits appears comparable with a sixfold track spht w~thout derandomizer, cf. fig. 4; at the same time, the digital resolution is about one-sixth of that for six parallel channels. While it is evidently more profitable to pursue higher order derandomizers, rather than split track arrangements, the best overall performance is obtained by combining both techniques. We shall thus consider the performance of two-track systems, equipped with first- and second-order derandomizers for each track. For two tracks with first-order derandomizer in each track, the probabihty w for each track that the derandomizer store is empty can be written
w= w(Po+Pl + P 2 + ½ P 3 ) + (
1 - - w ) [Po+½P1].
(15)
The fractional loss may be deduced to come to 12d = W214 + w(1 - w) ('/2 + '/4) -'}-(1 -- w)2'/2
= wl,+(1-w)12,
(16)
which falls between 12 and 14. Eq. (16) has been plotted in fig. 5 as curve C and the corresponding minimum bit number for specified dropout loss is shown in fig. 6(a), j = 2 . The required number of bits appears to be comparable to the case of one track with second-order derandomizer. The final case developed here is a second order derandomlzer on each of two tracks. The probabilities Wl and WE are readily found by arguments similar to those used above,
wl = ½wl(Po + P1 + P 2 ) + ( P o + P t + P 2 + P 3 ) +½w2Po+(Po+PO,
(17)
14'2 = ½w1P3 + P,* + ½w2P1 + (P2 + P6)
+ ½ ( 1 - w l - w 2 ) P o + ( P o + P O.
(18)
The ensuing fractional loss is also readily written down, /2da = w~16 + w l w 2(14 + 16) + w 2214 --]-( 1
-
+ (1 -
w 1 --
w2) Wl(l 2 --[-1 6 )
w 1 -
w2)
w2(/2 + 14) + (1 - w 1 - w2)2/2
= wll6+w214+(I-wl-w2)l = 12 - Wl(/2 -- 16) -- w2(/2 - - / 4 ) ,
2
(19)
which resembles eq. (14) in structure, but indicates that the fractional loss lies between /2 and /6. Eq. (19) is plotted in fig. 5 as curve D. The corresponding minimum number of bits required to achieve 1%, 5% or 10% dropout with nTd= 1 is shown in fig. 6(b), j=2. For the numerical example considered above, Td=2 s and n = 10 3, 2.3 k bits are required at the 5%
163
dropout level, which results in a resolution of better than 0.9 ms. The performance of this unit is thus rather better than the typical requirements enumerated above. Further combinations of track splitting and derandomizer circuitry are readily treated by mathematical procedures similar to the foregoing. As evident, however, from eqs. (17) through (19), the equations rapidly become more complex. As long as the system is relatively straightforward, these equations are quite easily used in a response unfolding program which can restore the input; for more complex circuitry unfolding is correspondingly more difficult; such circuits might thus aim at a 1% maximum dropout. In closing this section a somewhat different scheme for obtaining a true delayed record of a transient may be mentioned: the regularizing action of scalers, mentioned above, can be made use of by inscribing data m a scaled down channel in parallel with a direct channel3). Digital count rate meters including scaledown have been employed for several years in reactor power level monitoring. The direct channel need not have full overload handling capability and could thus be constructed for a high dropout level at peak signal; the scaled-down channel can be readily designed for less than 1% dropout at full signal. Equations which give the fractional loss for prescaling, in several tracks, have been previously presented3). A set of prescalers with successively higher orders of scaledown, feeding into parallel channels, evidently produces a quasilogarithmic record; the fractional dropout loss of this record varies only slightly over a wide range, much as the statistical error. Instruments of this kind have been constructed for reactor power monitoringa). For transient monitors which may have to be duplicated many times to service many detector channels, the elementary shift register delay schemes described above would provide adequate readout at considerably smaller cost and complexity. 3. Precision delays in the microsecond range Delays in the range from 0.1 to 10 /~s are required in the processing of nuclear detector pulses by various logic systems, generally when the decision to accept the event must be based on slow-acting circuitry but timing precision must be maintained. For example, the time difference between pulses may itself be the information developed by the experiment, as in particle velocity spectroscopy by T O F (Time-of-Flight). In such an experiment it is sometimes possible to discriminate between different particles by pulse shape, which requires the collection of all the charge delivered by a photomultiplier in response to a scintillation for
164
K. G. PORGES AND S. J. R U D N I C K
comparison to the fraction dehvered during the early part of the response. Many different schemes have been described to implement this comparison, but all these inevitably require a time of the order of 1 #s to deliver a verdict. The timing precision, on the other hand, is limited only by the characteristics of available scintillators, photomultipliers and fast circuitry, and can be kept to a few nanoseconds. Thus, the requirements for a typical delay of this kind are as follows: a) delay: up to a few microseconds to allow time for the decision logic system; b) time resolution: a few nanoseconds, maintained with high stability. Digital dropout is usually less important because acquisition rates are inevitably slow. In customary arrangements of such systems, a number of stratagems are employed to avoid the requirement of a precise delay. For example, the time difference between pulses may be converted to an analog pulse, which may then be delayed by means not requiring high timing precision, before being applied to the decision gate. Similarly, a coincidence system may obtain timing signals from the crossover of doubly-differentiated slow pulses; this results in a fast coincidence at about the same time the pulse height decision is available. Where necessary, precise delays of the order of a few hundred nsec are readily provided by coaxial cable. However, it is not always convenient or possible to avoid the requirement of precise delays m excess of
RAN OMI I INPUT IRETRIGGERABLEI-,-C°--IMONOSTABLE I ]
1 ps; this makes the question of means to provide such delays of somewhat more than academic interest. Coaxial cables, with typical propagation constants of 20 cm/ns are not very suitable for delays of several microseconds 9,to). Delay lines, amounting to distriL buted LC circuits, provide delay to pulse rise-nine ratios of only 50 to 100 and thus fail to achieve the specified timing precision. Both delay lines and coaxial cable exhibit a certain temperature dependence of the delay. A widely used alternative means of providing long delays with excellent timing develops timing pulses from the trailing edge of a monostable triggered by the signal source. Th~s has the further advantage of allowing convenient adjustment of the delay over a wide range. When high rates are encountered in such channels, the paralysis introduced by the monostable (equal to or longer than the delay) may cause unacceptable deadtime losses. As considered in the preceding section, these losses are readily reduced to insignificance by providing a statable number of tracks with cychc switching 3 , n ) (formulae and graphs, similar to the equations and figures of the preceding section, which allow one to determine the number of tracks required to obtain negligible losses at a given input rate are presented in ref. 3). However, such a unit requires a very careful equalization and occasional recalibration of delays in all channelsl~). The use of shift register delay avoids such calibration requirements. In the preceding discussion of delays of the order of
DELAYED
40-BIT SHIFTREGISTER
I
40-BIT SHIFTREGISTER
i L_(
40-BIT SHIFTREGISTER
II
-~BITSHIFTREGISTER
I
40-BIT SHIFTREGISTER
• TRIMTO PRODUCE IOns PROPAGATIODELAY N Fig. 7. Shift register delay with five parallel tracks, for better rime resolution.
T
SHIFT REGISTER DELAYS FOR RANDOM A S Y N C H R O N O U S DATA I N P U T
seconds with millisecond resolution, the driving frequency could be assumed to be freely adjustable to provide the required delay with any particular number of shift register bits. For the microsecond regime, however, the resolution available at reasonable cost is limited by the maximum frequency of about 20 Mhz at which currently available MSI devices are guaranteed to operate. This results in a minimum uncertainty of 50 ns; dropout of random inputs is given by eq. (2) w i t h / = 2 × 107. A shift register delay consisting of a single track thus comes off poorly when comparing resolution and dropout with cable delay (which is limited in these performance parameters only by the pulse width). However, the resolution of a shift register delay can be improved by a scheme involving a number of parallel tracks which are fed input pulses in parallel rather than in rotation Such a scheme is illustrated in fig 7. Input pulses, shaped to a width of 50 ns (plus the maximum shift register setup time) are applied to each of k identical tracks which are shifted cyclically in staggered fashion. The maximum and minimum shift register setup times must differ by less than (50/k) ns. The output of the first A N D gate is a pulse which straddles the input delayed by m/f and has a duration of either Ilk/" or 2/k/, depending on the exact phase relationship between input and clock pulses. Thus the timing uncertainty is reduced, in principle, to l/kJ. For a 20 MHz system, th~s amounts to 10 ns with 5 tracks. The output network shown in fig. 7 serves to produce a uniform output pulse of width l/kf, when pulses delivered to it have either 1/kf or 2/k/ width. As fat as resolution of closely spaced inputs is concerned, two (or more) incident pulses separated by
165
at least 2/kf result in a signal at least 3/kf wide, from which the output network then produces two pulses. In closing, ~t nmy be melationed that shift registers with several microseconds delay can be usefully employed in fast coincidence systems to measure the accidental rate concurrently with the true plus accidental rate, by providing a delay in one channel which extends by a reasonable margin beyond the deadtime of the opposite channel. In a fast slow system, this may amount to 10ps. The timing precision is relatively umnlportant for this measurement, but the improved resolution and reduced loss l esultlng from the use of parallel tracks, as discussed here, may be helpful References 1) K. Porges, Proc. Conf Safety, fuels and core design o] large, fast power reactors, ANL-7120 (1965) 863. 2) K Porges and (3 McGmnls, IEEE Tranb Nucl Scl. NS-13, no 1 (1966) 454. :~) K Porges, C. J. Rush and C. E. Caya, Nucl. Instr. and Meth. 78 (1970) 115 4) S. J. Rudmck, P. L. Mlchaud and K G Porges, Nucl. Instr. and Meth 71 (1969) 196. 5) N Pacdlo, T Ferrari and P Lorenzl, Nucl. Instr. and Meth. 92 (1971) 13 6) A Arbel, A Suhaml and B. Sabbah, Nucl. Instr. and Meth. 41 (1966) 292. 7) Elron, Ltd; Model STB-N-3. 8) F Staub and F. Meier, Neue Techmk (Kerntechmk) B/2 (1969) 48. 9) Q. Kerns, F KIrsten and C. Wmmgstad, UCRL-3307 (1959) revised. 1()) K Porges, ANL Report, In press. H) A. DeVolpl, G Caya, C. Rush and S. Rudmck, Rev. Scl. Instr 42 (1971) 684.
INSTRUMENTS
AND METHODS
lO 3 (i972) i57-165; ©
NORTH-HOLLAND
PUBLISHING
CO.
DESIGN OF S H I F T REGISTER DELAYS FOR RANDOM ASYNCHRONOUS DATA INPUT* K. G. P O R G E S and S. J. R U D N I C K
Argonne Nattonal Laboratory, 9700 South Cass Avenue, Argonne, llhnots 60439, U S.A. Received 4 April 1972
The utdmatlon of shift registers for purposes of providing fixed and stable delay m nuclear data processing IS illustrated here by two specific apphcatlons, one requiring delays of the order of seconds and the other reqmring delays in the microsecond range. In the first case considered, the chief problem Is to prowde the capability of handling large random rates without undue digital dropout loss, in a dewce which does not reqmre an excesswe number of shift register bits. The solution proposed is a combma-
hon of cychcally operated parallel tracks with derandomizers. In the second case the required delay can be produced with a relatwely modest number of bits, but the problem to be overcome is the hmited time resoluuon of the device, determined by the minimum shifting period This is shown to be amenable to amprovement through a staggered shifting system which allows a subdwlSlOn of the shift period.
1. Introduction The increasing availabihty of shift registers of large capacity and high speed, promoted by MS[ and LSI fabrication techniques, suggests their use in connection with a number of nuclear count processing systems which require a fixed delay. Compared to other available means of obtaining such a delay, shift registers can claim superior long-term stabihty, freedom from maintenance or recalibration requirements, insensitivity to temperature and other environmental factors, and versatility. On the other hand, shift registers used with high random input rates are subject to digital dropout loss, and the inherent time cesolution of + (1/J'), where f=shift frequency, becomes a drawback in some applications. Both these problems diminish as the shift frequency is increased. Maintaining a specified delay while increasing the shift frequency, however, calls for increasing the number of bits m the shift register commensurately. Thts may make the unit prohibitively expensive, even when MSI units currently selhng for a few cents per bit are used. Moreover, the maximum guaranteed frequency for currently available MS[ units is about 20 MHz. These problems can be alleviated by certain stratagems, described in this report. By arranging parallel shift register tracks and adding appropriate derandomizing circuitry, the number of bits required to obtain a certain delay at specified dropout level can be reduced by an order of magnitude. In another arrangement, also involving parallel tracks, the time resolution can be made smaller than 1If. The schemes are illustrated through two specific applicauons, in which other means of producing the * Work performed under the auspices of the U.S. Atomic Energy Commission.
required delay have been employed in existing systems. Replacement of these delays by shift registers would not necessarily improve the short-term performance of the systems, but would eliminate maintenance and cahbration problems. Maintenance problems are particularly serious in safety and surveillance instrumentation designed to detect a rare transient in the count rate of a detector channel, indicating some malfunction or failure which must be coped with expeditiously. If such channels are not highly reliable, they may either result in an intolerably high level of false alarms or turn out to be msufficiently sensitive when a real incident occurs; moreover, the record of such a transient can be so distorted as to render diagnosis of the trouble inconclusive. The following section describes the application of a shift register delay to this kind of instrumentation. The required delay amounts to several seconds, which strongly emphasizes the need to design the system for economy in shift register bit number. Other applications where delays must remain highly constant over long periods occur in fast coincidence systems and time-of-flight acquisition systems. Such measurements are usually made under conditions which make digital dropout a lesser problem than resolution; at the same time, the total delay required is usually small enough to de-emphasize the need to design for minimum number of shift register bits. A shift register delay with improved t~me resolution is described in the third section of this report. 2. Application of digital delay in an excursion monitor channel A practical application of a digital delay amounting to the order of seconds is based on the operational 157
158
K. G. P O R G E S A N D S. J. R U D N I C K
characteristics of certain surveillance channels employed in nuclear reactor plants or similar installations, e.g., fuel reprocessing plants. In these plants one finds a number of nuclear detector channels each of which normally delivers a count rate at some background level. As the result of some malfunction or failure m the plant, transients may appear in the count rate. The intensity and shape of the transients, in conjunction with other information, can be used to diagnose the trouble and must therefore be recorded. The customary technique of obtaining a continuous channel count rate record is to convert counts into an analog current by means of a count rate meter circuit; the current is used, in turn, to drive a recording device such as a chart recorder. Normally the chart recorder would run at, say, 0.5 in./min or 60 ft/24 h. This corresponds to a tolerable paper consumption rate and still produces a readable record of transients lasting several minutes. However, the type of transients described above may build up in or last rather less than a second. To be able to make any references from the shape of the record, the paper feed rate would thus have to be stepped up to something like 1 in./s, which evidently cannot be maintained continuously but must be actuated by the transient itself. The speed-up time of suitable chart recorders, viz, oscillographs, amounts to more than one second, moreover the unit which trips the system, of whatever design, can only act when the transient has reached some distance from the normal background level and thus inevitably misses the imtial rise. These two considerations call for temporary information storage of the order of a few seconds, which is most readily implemented by direct digital storage of counts. A system of this description was developed for a fuel element rupture detector (FERD) system, installed in the EBR-I[ plant~). The outputs of several neutron detection channels were directly written on a continuous magnetic tape loop 2) and read out by another head after substantial delay. In continuous use, however, the tape transport developed serious wear problems. Such difficulties are clearly avoided by the substitution o f a shift register delay. However, to provide a practical shift register delay unit at competitive cost, particularly for systems which employ a number of detector channels, reduction of the required number of shift register bits is essential. A shift register delay of reasonable cost can also effectively complement more sophisticated means of information storage such as an on-line computer. Of course, given sufficient capacity the computer itself could perform all necessary functions including temporary storage. In practice, the cost of using the computer
in this way must be compared to the cost of providing shift register units for temporary storage and reserving the computer for permanent storage and other on-line tasks. The performance requirements for a typical excursion monitor may be summarized as follows: a) delay: up to several seconds, allowing for the delayed triggering of the alarm, providing a record of background just ahead of the transient for reference, and possibly allowing for paper feed speedup of a chart recorder; b) time resolution: 2 ms, to record the detailed structure of the transient; c) input rate: background 10-100 cps; transients up to l 0 3 cps; d) maximum dropout loss: 5% should be acceptable at peak input rate; 10% may not be excessive, however, in conjunction with a correction program calculating input from the record. The remainder of this section addresses itself to the task of determining how these specifications can be met at minimum cost. Shift register delays, scalers, and magnetic tape recorders all develop digital dropout losses in conjunction with random input. The reduction of such losses by cychc switching between tracks was described in detail in a previous publication concerned with scalers or direct digital magnetic tape recording3). We shall develop similar formulae for shift register delay, where a somewhat different s~tuation obtains: for a scaler, a fixed deadtime follows every count, while a shift register delay can record at most one input per shift period 1/f. To avoid unnecessary complexity we shall neglect the additional losses which occur in practice due to the deadtime of the circuitry ahead of the shift register. As a first task, we consider the dropout loss for the single shift register channel shown in fig. 1. For the moment we shall ignore the derandomizer circuit shown to the left of the dotted line; the rest of the circuit is a schematic of an elementary shift register delay including a buffer 4' 2). The buffer ensures that each random input introduces one and only one pulse into the shift register during its live time and blocks all inputs between the first arrival and the end of a given shift period. The clock drives the shift register at a regular frequency f, resulting in a delay Td=m/f, where m = number of bits. The mean input rate n, considered here as a fixed parameter, determines the mean fraction n/f= N of the register capacity occupied by counts in the absence of dropout loss. Let c = output rate and
SHIFT REGISTER
DELAYS FOR RANDOM
ASYNCHRONOUS
SHIFT REGISTER
BUFFER
RANDOM INPUT F ~
159
DATA INPUT
~
+SV
I
B
;
ITS MS, OR LSI
DELAYED SERIAL ,I ~ ^ ,OUTPUT ~ OUT I
I'-'--I~-
i ._J
L_
DERANDOMIZER
JOE ~t.=J ZN
a~
CLOCK
Fig. l. Shift register delay s h o w i n g i n p u t buffer a n d d e r a n d o m l z e r to reduce losses at high r a n d o m i n p u t rates, as explained m the text.
Pk = e-N(Nk/k!); then the rate at which inputs are lost in the shift register comes to
(n--c) = f ~ P k ( k - 1 ) ,
(1)
k=2
inasmuch as k - l inputs are dropped whenever exactly k inputs appear in a shift duration lff. Rearranging eq. (1), we find the fractional loss 11 for a single track,
ll = [(n--c)/n]l = (1 --e-N)--(Q/g)e -N,
(2)
where we have put
Q(N) = eN--(1 + N ) = ½N2(1 + ~ N + ~-~-N2 +...).
(3)
As n is considered a fixed parameter and Td is also specified, eq. (2) can be used to calculate the minimum number of shift register bits m required to keep dropout loss to a specified level; the frequencyfis thereupon determined by the required delay. For example, one finds that for n-----10 3 and Td=2 s, some 2 x 104 bits must be provided to keep drop out loss under 5%. This makes for a rather expensive system, offering a time resolution of 0.1 ms, considerably better than strictly required. Time resolution can be traded for a smaller bit
number by providing several parallel shift reg]ster tracks. While it might appear at first blush that such paralleling of tracks would require even more bits, it will be shown that in fact the loss per bit is dramatically reduced, owing to an effect which is the equivalent of the "regularizing" action of scalers3). Similar considerations apply to cyclic distribution of random input on magnetic tape z' 3). A two-track shift register delay is shown in fig. 2. The input is applied to a simple bmary distributor which sends alternate pulses to the two buffers; a single clock drives both tracks synchronously. The outputs must be recombined out of phase as pulses present in both tracks would otherwise overlap and result in a single output. Alternatively the tracks could be driven out of phase. It may be noted that the performance of a multitrack shift register delay is equivalent to that of a multiscaler which has a maximum capacity per scaler equal to the number of tracks. Either system tends to group pulses, thus losing time resolution. For two tracks, the fractional counting loss comes to
12 = ~ ( k - 2 ) P k / N = l x - ( Q / N ) e -N,
(4)
k=2
l~ = l, -1 -- (Q/N) e-N + (e-N/2N) ×{½N2+...[NJ-1/(j--1)!]}.
(5)
K. O. PORGESANDS.J. RUDNICK
160 BUFFER I
SHIFT REGISTER I OUTPUT GATES
I
DISTRIBUTOR
B,TS
I
I
MS,OR ,
1
I~
I
__~CLOCK
I ,N RANDOM
~
U2_
DELAYED T
__1
I
BUFFER 2
SHIFT REGISTER 2
0
r I
(~-,) B,TS
I
MS, OR,S,
I
ss
I
m
Td = ~
+
150 ~+l/f
/-I/Oaf )
Fig. 2. Shift register delay using two-track distribution for the purpose of reducing losses at high random input rates.
To illustrate the general dependence of dropout loss on the parameter N, which amounts to the duty cycle of the shift register delay, eqs. (2), (4) and (5) have been plotted against a representative range of values for N, in fig. 3. These plots, similar to plots for cyclic distribution of random counts between parallel tracks of scalers3), exhibit asymptotic approach to unity for large values of N; for small N, each curve approaches the leading term of the expansion, NJ/(j + 1)!. It may be noted that a single track, in order not to exceed 10% dropout loss, must keep N smaller than about 0.2, whereas two parallel tracks can tolerate N values five times larger at comparable loss. On the other hand, the use of increasing numbers of parallel tracks tends to produce an increasingly modest relative improvement. The effect of this on overall economy of design is more directly shown if one considers Ta and n as
specified parameters and plots the minimum total number of shift register bits m t (including all tracks) which would be required to keep losses below specified limits of 1%, 5% and 10%. This is done in fig. 4 in which the ratio m t / n T d i s plotted against the number of parallel channels j. In practical terms a delay of 2 s = Td, input rate of 103=n and maximum dropout of 5%, would require some 20 k bits in a single track system, but only 6 k bits in two tracks, or 3 k bits per track, when the system depicted in fig. 2 is used. Distribution amongst four tracks reduces this further to 3.6 k, or 900 per track. At the same time, however, the digital time resolution r = 1/f=jTd/mt decreases. For six tracks, for example, the 5% dropout level is reached with 2.7 k bits or 450 bits per track, hence 4.4 ms time resolution. This may be adequate for some transient records but not for others. I f one further
SHIFT REGISTER DELAYS FOR RANDOM ASYNCHRONOUS DATA INPUT
10
I
,
I
I'
L,,
I
161
probability w o f finding the derandomizer store empty at the time a particular shift occurs:
I
w = (P0 + P J ) w + Po(1 - w).
(6)
Rearranging and using eq (3), we obtain w = (1 + Q ) - I .
The fractional loss lid for one channel equipped with derandomizer thus comes to
01
t,d = ~')
) z
w X
[&(k-2)/N]+(1-w)
k=2
I
03
•2).
(8)
According to eq. (8) one would expect the loss to lie between that for the track without derandomizer, and that appropriate for a two-track system as described above. A plot o f eq. (8), presented in fig. 5, confirms this; eq. (8) is plotted as curve A, while the fractional losses for various numbers o f multiple channels are replotted from fig. 3 as broken lines. Below the 10% level, the loss o f a single channel equipped with derandomizer is only slightly larger than the corresponding loss for a two-track arrangement at the same number N. Thus, the derandomizer channel can produce a certain
COl~!
i 02
Y~ [ & ( k - 1 ) / N ]
k=3
= 11 - w ( l l -
0 301 OI
(7)
04
05
I0
15
20
~5
N
Fig. 3. Fractional loss 13=[(n-c)/n]j against N = n / f for J=l through j = 6 parallel tracks, n=random input rate, f=shlft frequency, c = output rate.
takes into account the cost o f the additional circuitry reqmred to distribute inputs and recombine outputs, it appears that a four-track system, easily implemented with three binary stages in the distributor, is about as far as practical systems may reasonably go. This concluslon is strengthened by the posslbihties inherent in derandomlzers6'7), which we shall now discuss. A derandomizer suitable for present purposes is shown in fig. 1 to the left of the broken hne; the schematic also suggests how one m a y add further stages, to provide second or higher-order dewces. One can then further combine derandomizers and multltrack distribution to obtain the most economical overall system. As indicated in fig. 1, the action o f the derandomizer is to hold the second input arriving within a given shift interval, and to release this at the beginning o f the next interval. I f no input arrives during that interval, the derandomizer has merely shifted registration o f one input by one shift period. If the following interval receives one input, the latter is again shifted; if two inputs, the second input is dropped. F r o m this description we can put down the a priori
5 -/= OI
E ~, 05
--1 ./=10
] _ _
I I
I 2
I 3
[ - -
I 4
i 5
6
J
Fig. 4. Number of bits mt required in all per unit nTd (Td= reqmred delay, n=random input rate), for j = l through ] = 6 parallel tracks, and fractional loss lj=0.01, 0.05 and 0.10, respectively.
162
K. G. P O R G E S A N D S. J. R U D N I C K
bability that b o t h stores are full. One readily deduces the relations
I0
(9)
w l = w l ( P o + P I ) + w2Po,
(10)
w2=wxPz+w2Pl+(1-wj-w2)Po,
and P1 -- P2) P1) + ( 1 - w l - w z ) (
(1 - - w l - - w 2 ) = w l (1 - - P o -
OI
+wz(1 - P o -
1-Po)"
(11)
Solving for Wl a n d wz a n d i n t r o d u c i n g again eq. (3), we find that
001
w l = [ ( Q + 1) 2 - ½ N 2 ] -1,
(12)
w2 = QWl.
(13)
The fractional loss with single t r a c k a n d d o u b l e der a n d o m i z e r , llad, thus becomes
ljdd
= w113 + w212 + (1 - w 1 -- W2)[ 1 = l~-Qwl(ll-12)-wl(lx-13).
015
02
05
N
I
15
2
3
(14)
This is clearly seen to lie between I s a n d /3, as again confirmed b y fig. 5 in which eq. (14) is p l o t t e d as curve B. The n u m b e r o f bits required for specified
Fig. 5. Fractional loss ly for certain combinations of derandomlzers and parallel tracks Losses for parallel tracks without derandomlzers are redrawn from fig. 3 as broken lines, for j--1,2,3,4 and 6. Curve A (lla): single track w~th one derandomizer stage; curve B (haa) single track wxth two derandomizer stages; curve C (12a): two parallel tracks with one derandomlzer stage on each track; curve D (12aa): two parallel tracks with two derandomizer stages on each track. Note that curves A and B converge to 1 = 1 at high values of n / f whereas curves C and D approach j = 2 at high rates; for low rates A approaches ./=2, B aproaches j = 3 , C approaches j = 4 and D approaches j = 6 .
(a)
(b) I
- - ( 1 = 05from fig 4) --
I I I I
---
I
I I
X: OI
i
5
I I I
--
I
d r o p o u t level with a p p r o x i m a t e l y o n e - h a l f to twothirds o f the total n u m b e r o f bits which w o u l d be r e q u i r e d for the split t r a c k system, a n d is therefore clearly superior. T h e relative n u m b e r o f bits req u i r e d for 1%, 5% a n d 10% d r o p o u t has again been p l o t t e d as a b a r g r a p h in fig. 6(a), with c o r r e s p o n d i n g n u m b e r s for 5% d r o p o u t m a system w i t h o u t d e r a n d o mizer d r a w n as a b r o k e n line. T o i m p r o v e p e r f o r m a n c e still further, we m a y a d d a n o t h e r stage to the d e r a n d o m i z e r as suggested in fig. 1. The second store is used only when the first store is full b u t has p r i o r i t y in releasing its contents to the shift register. Let Wl = p r o b a b i l i t y t h a t b o t h stores are e m p t y at the time a p a r t i c u l a r shift occurs a n d w2 = p r o b a b i l i t y that the first store is full a n d the second store e m p t y ; then 1 - W x - w2 -- c o m p l e m e n t a r y p r o -
I
q
,
./= 05
Ol 2
./:
I0
'
II
.
m l=
I
2
I I
2
Fig. 6 Number of shift register bits mt required in all per unit nTd for (a) one and two parallel tracks wlth single derandom]zer
per track and (b) one and two parallel tracks with double derandom~zer on each track.
S H I F T R E G I S T E R DELAYS FOR R A N D O M A S Y N C H R O N O U S D A T A I N P U T
dropout levels of 1%, 5% and 10% is shown in fig. 6(b). The required number of bits appears comparable with a sixfold track spht w~thout derandomizer, cf. fig. 4; at the same time, the digital resolution is about one-sixth of that for six parallel channels. While it is evidently more profitable to pursue higher order derandomizers, rather than split track arrangements, the best overall performance is obtained by combining both techniques. We shall thus consider the performance of two-track systems, equipped with first- and second-order derandomizers for each track. For two tracks with first-order derandomizer in each track, the probabihty w for each track that the derandomizer store is empty can be written
w= w(Po+Pl + P 2 + ½ P 3 ) + (
1 - - w ) [Po+½P1].
(15)
The fractional loss may be deduced to come to 12d = W214 + w(1 - w) ('/2 + '/4) -'}-(1 -- w)2'/2
= wl,+(1-w)12,
(16)
which falls between 12 and 14. Eq. (16) has been plotted in fig. 5 as curve C and the corresponding minimum bit number for specified dropout loss is shown in fig. 6(a), j = 2 . The required number of bits appears to be comparable to the case of one track with second-order derandomizer. The final case developed here is a second order derandomlzer on each of two tracks. The probabilities Wl and WE are readily found by arguments similar to those used above,
wl = ½wl(Po + P1 + P 2 ) + ( P o + P t + P 2 + P 3 ) +½w2Po+(Po+PO,
(17)
14'2 = ½w1P3 + P,* + ½w2P1 + (P2 + P6)
+ ½ ( 1 - w l - w 2 ) P o + ( P o + P O.
(18)
The ensuing fractional loss is also readily written down, /2da = w~16 + w l w 2(14 + 16) + w 2214 --]-( 1
-
+ (1 -
w 1 --
w2) Wl(l 2 --[-1 6 )
w 1 -
w2)
w2(/2 + 14) + (1 - w 1 - w2)2/2
= wll6+w214+(I-wl-w2)l = 12 - Wl(/2 -- 16) -- w2(/2 - - / 4 ) ,
2
(19)
which resembles eq. (14) in structure, but indicates that the fractional loss lies between /2 and /6. Eq. (19) is plotted in fig. 5 as curve D. The corresponding minimum number of bits required to achieve 1%, 5% or 10% dropout with nTd= 1 is shown in fig. 6(b), j=2. For the numerical example considered above, Td=2 s and n = 10 3, 2.3 k bits are required at the 5%
163
dropout level, which results in a resolution of better than 0.9 ms. The performance of this unit is thus rather better than the typical requirements enumerated above. Further combinations of track splitting and derandomizer circuitry are readily treated by mathematical procedures similar to the foregoing. As evident, however, from eqs. (17) through (19), the equations rapidly become more complex. As long as the system is relatively straightforward, these equations are quite easily used in a response unfolding program which can restore the input; for more complex circuitry unfolding is correspondingly more difficult; such circuits might thus aim at a 1% maximum dropout. In closing this section a somewhat different scheme for obtaining a true delayed record of a transient may be mentioned: the regularizing action of scalers, mentioned above, can be made use of by inscribing data m a scaled down channel in parallel with a direct channel3). Digital count rate meters including scaledown have been employed for several years in reactor power level monitoring. The direct channel need not have full overload handling capability and could thus be constructed for a high dropout level at peak signal; the scaled-down channel can be readily designed for less than 1% dropout at full signal. Equations which give the fractional loss for prescaling, in several tracks, have been previously presented3). A set of prescalers with successively higher orders of scaledown, feeding into parallel channels, evidently produces a quasilogarithmic record; the fractional dropout loss of this record varies only slightly over a wide range, much as the statistical error. Instruments of this kind have been constructed for reactor power monitoringa). For transient monitors which may have to be duplicated many times to service many detector channels, the elementary shift register delay schemes described above would provide adequate readout at considerably smaller cost and complexity. 3. Precision delays in the microsecond range Delays in the range from 0.1 to 10 /~s are required in the processing of nuclear detector pulses by various logic systems, generally when the decision to accept the event must be based on slow-acting circuitry but timing precision must be maintained. For example, the time difference between pulses may itself be the information developed by the experiment, as in particle velocity spectroscopy by T O F (Time-of-Flight). In such an experiment it is sometimes possible to discriminate between different particles by pulse shape, which requires the collection of all the charge delivered by a photomultiplier in response to a scintillation for
164
K. G. PORGES AND S. J. R U D N I C K
comparison to the fraction dehvered during the early part of the response. Many different schemes have been described to implement this comparison, but all these inevitably require a time of the order of 1 #s to deliver a verdict. The timing precision, on the other hand, is limited only by the characteristics of available scintillators, photomultipliers and fast circuitry, and can be kept to a few nanoseconds. Thus, the requirements for a typical delay of this kind are as follows: a) delay: up to a few microseconds to allow time for the decision logic system; b) time resolution: a few nanoseconds, maintained with high stability. Digital dropout is usually less important because acquisition rates are inevitably slow. In customary arrangements of such systems, a number of stratagems are employed to avoid the requirement of a precise delay. For example, the time difference between pulses may be converted to an analog pulse, which may then be delayed by means not requiring high timing precision, before being applied to the decision gate. Similarly, a coincidence system may obtain timing signals from the crossover of doubly-differentiated slow pulses; this results in a fast coincidence at about the same time the pulse height decision is available. Where necessary, precise delays of the order of a few hundred nsec are readily provided by coaxial cable. However, it is not always convenient or possible to avoid the requirement of precise delays m excess of
RAN OMI I INPUT IRETRIGGERABLEI-,-C°--IMONOSTABLE I ]
1 ps; this makes the question of means to provide such delays of somewhat more than academic interest. Coaxial cables, with typical propagation constants of 20 cm/ns are not very suitable for delays of several microseconds 9,to). Delay lines, amounting to distriL buted LC circuits, provide delay to pulse rise-nine ratios of only 50 to 100 and thus fail to achieve the specified timing precision. Both delay lines and coaxial cable exhibit a certain temperature dependence of the delay. A widely used alternative means of providing long delays with excellent timing develops timing pulses from the trailing edge of a monostable triggered by the signal source. Th~s has the further advantage of allowing convenient adjustment of the delay over a wide range. When high rates are encountered in such channels, the paralysis introduced by the monostable (equal to or longer than the delay) may cause unacceptable deadtime losses. As considered in the preceding section, these losses are readily reduced to insignificance by providing a statable number of tracks with cychc switching 3 , n ) (formulae and graphs, similar to the equations and figures of the preceding section, which allow one to determine the number of tracks required to obtain negligible losses at a given input rate are presented in ref. 3). However, such a unit requires a very careful equalization and occasional recalibration of delays in all channelsl~). The use of shift register delay avoids such calibration requirements. In the preceding discussion of delays of the order of
DELAYED
40-BIT SHIFTREGISTER
I
40-BIT SHIFTREGISTER
i L_(
40-BIT SHIFTREGISTER
II
-~BITSHIFTREGISTER
I
40-BIT SHIFTREGISTER
• TRIMTO PRODUCE IOns PROPAGATIODELAY N Fig. 7. Shift register delay with five parallel tracks, for better rime resolution.
T
SHIFT REGISTER DELAYS FOR RANDOM A S Y N C H R O N O U S DATA I N P U T
seconds with millisecond resolution, the driving frequency could be assumed to be freely adjustable to provide the required delay with any particular number of shift register bits. For the microsecond regime, however, the resolution available at reasonable cost is limited by the maximum frequency of about 20 Mhz at which currently available MSI devices are guaranteed to operate. This results in a minimum uncertainty of 50 ns; dropout of random inputs is given by eq. (2) w i t h / = 2 × 107. A shift register delay consisting of a single track thus comes off poorly when comparing resolution and dropout with cable delay (which is limited in these performance parameters only by the pulse width). However, the resolution of a shift register delay can be improved by a scheme involving a number of parallel tracks which are fed input pulses in parallel rather than in rotation Such a scheme is illustrated in fig 7. Input pulses, shaped to a width of 50 ns (plus the maximum shift register setup time) are applied to each of k identical tracks which are shifted cyclically in staggered fashion. The maximum and minimum shift register setup times must differ by less than (50/k) ns. The output of the first A N D gate is a pulse which straddles the input delayed by m/f and has a duration of either Ilk/" or 2/k/, depending on the exact phase relationship between input and clock pulses. Thus the timing uncertainty is reduced, in principle, to l/kJ. For a 20 MHz system, th~s amounts to 10 ns with 5 tracks. The output network shown in fig. 7 serves to produce a uniform output pulse of width l/kf, when pulses delivered to it have either 1/kf or 2/k/ width. As fat as resolution of closely spaced inputs is concerned, two (or more) incident pulses separated by
165
at least 2/kf result in a signal at least 3/kf wide, from which the output network then produces two pulses. In closing, ~t nmy be melationed that shift registers with several microseconds delay can be usefully employed in fast coincidence systems to measure the accidental rate concurrently with the true plus accidental rate, by providing a delay in one channel which extends by a reasonable margin beyond the deadtime of the opposite channel. In a fast slow system, this may amount to 10ps. The timing precision is relatively umnlportant for this measurement, but the improved resolution and reduced loss l esultlng from the use of parallel tracks, as discussed here, may be helpful References 1) K. Porges, Proc. Conf Safety, fuels and core design o] large, fast power reactors, ANL-7120 (1965) 863. 2) K Porges and (3 McGmnls, IEEE Tranb Nucl Scl. NS-13, no 1 (1966) 454. :~) K Porges, C. J. Rush and C. E. Caya, Nucl. Instr. and Meth. 78 (1970) 115 4) S. J. Rudmck, P. L. Mlchaud and K G Porges, Nucl. Instr. and Meth 71 (1969) 196. 5) N Pacdlo, T Ferrari and P Lorenzl, Nucl. Instr. and Meth. 92 (1971) 13 6) A Arbel, A Suhaml and B. Sabbah, Nucl. Instr. and Meth. 41 (1966) 292. 7) Elron, Ltd; Model STB-N-3. 8) F Staub and F. Meier, Neue Techmk (Kerntechmk) B/2 (1969) 48. 9) Q. Kerns, F KIrsten and C. Wmmgstad, UCRL-3307 (1959) revised. 1()) K Porges, ANL Report, In press. H) A. DeVolpl, G Caya, C. Rush and S. Rudmck, Rev. Scl. Instr 42 (1971) 684.