Design of system-on-glass for poly-Si TFT OLEDs using mixed-signals simulation

Displays 30 (2009) 17–22

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Design of system-on-glass for poly-Si TFT OLEDs using mixed-signals simulation Young-Jun Yun a, Byung-Geun Jun b, Yong-Kyeom Kim b, Jung-Won Lee b, Yong-Min Lee c,* a b c

School of Engineering, University of Durham, South Road, Durham DH1 3LE, United Kingdom CAE Team, Corporate R&D Center, Samsung SDI CO., LTD, 428-5, Gongse-dong, Giheung-gu, Yongin-si, Gyeonggi-do, South Korea Division of Electronic Engineering, Sunmoon University, 100 Galsan-Ri, Tangjung-Myun, Asan, Chungcheong Namdo 336-708, South Korea

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Article history: Received 11 October 2007 Received in revised form 10 April 2008 Accepted 13 May 2008 Available online 20 June 2008 Keywords: AMOLED LTPS TFT System-on-glass Mixed-signals simulation IR-drop

a b s t r a c t AMOLEDs (active-matrix organic light emitting diodes) employing poly-Si TFT have been used to integrate peripheral circuits on a glass to reduce the cost through the use of dead space on the glass. The system-on-glass (SOG) development provides enormous challenges to the developers, usually verifying the SOG by transistor-level simulation. IR-drop modeling is needed to reduce the uniformity degradation in the OLED image quality. This paper presents a full panel simulation technique for OLED driver and pixels that is integrated on a glass using the mixed-signals circuit design and the proposed process shows excellent capabilities relating to the capacity and the speed. Ó 2008 Elsevier B.V. All rights reserved.

1. Introduction In the design of active-matrix organic light emitting diodes (OLEDs), there is a need of full panel simulation to see full panel’s characteristics before manufacture and to reduce design lead time and cost. The use of poly-Si TFTs for OLEDs allows peripheral circuits to be integrated on a glass substrate at low cost and reduces the number of external driver ICs. With the prospect of such integration, it is likely that emerging system-on-glass (SOG) design projects will incorporate more and more both analog and digital circuits, such as digital-to-analog converters (DACs) [1], DC–DC converters, frame-memory [2], and timing controllers (TCONs). SOG design is currently focused on analog design strategies and consequently, transistor-level simulation techniques. As a good reason for this analog focus, it is argued that poly-Si TFTs are not yet stable enough for standardization and analog simulation makes the best use of their characteristics. However, the methods are slow, require intensive labor and have limited capacity. For example, an SOG circuit for a QVGA one-chip mobile driver IC without GRAM contains more than 200,000 transistors. SPICE’s capacity is not only limited to about 100,000 transistors, but it also takes a long time to run a simulation. Thus, the restrictions involved currently lead engineers to simulate circuits partially, increasing the risk of re-spins. Therefore, it is inevitable to introduce new methodologies for full panel simulation in SOG design and analysis.

* Corresponding author. E-mail address: [email protected] (Y.-M. Lee). 0141-9382/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.displa.2008.05.003

To achieve full panel simulation from peripheral circuits to pixel, we need to model the OLED pixel, pixel driving circuits and the RC delay model. Main issue in the modeling is the IR-drop on the OLED panel, which degrades uniformity of the image quality. IRdrop is the voltage drop due to current passing through the resistances of metal lines and cathode plates in an AMOLED panel. Thus, the IR-drop modeling should be included in the full panel simulation. In this paper we introduce mixed-signals circuit design to achieve full panel simulation, using the example of a display driver integrated on a glass. We believe that this technique, mixed-signals simulation, offers major advances in capacity and speed over existing techniques and allows for the analysis of the whole signal, from peripheral circuits to the OLEDs [3]. The mixed-signals simulation has been used for system-on-chip (SOC) [4,5] but this is the first time the mixed-signals simulation is applied to SOG design for poly-Si TFT OLEDs to our knowledge. 2. Experimental We conducted our experiment based on the simulation of the data and the scan drivers for a 2.000 QVGA (320  240) OLED integrated on a glass to improve design performance using the mixed-signals simulation strategy against traditional SPICE simulation. Fig. 1 illustrates a block diagram of a scan driver and its simulation methods. The scan driver has three main circuit blocks. The first, the shift register block, functions as a scan pattern generation and includes a shift register and a 3-input NAND circuit. The

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Fig. 1. Block diagram of a scan driver and its simulation methods.

second block, the level shifter, converts low-voltage signals to high-voltage data. The third block is the output buffer that drives relatively large capacitance and resistive load. For the scan driver simulation, the shift registers were simulated as digital blocks using VHDL and the level shifters were simulated as analog behavioral model blocks using VHDL-AMS. The output buffer blocks were simulated as analog blocks using SPICE. Fig. 2 shows a block diagram of a data driver and its simulation methods. The data driver has five main circuit blocks. The shift register makes sampling clock for the 1st latch. The 1st latch, called a sampling latch, samples data by sampling the clock. The 2nd latch holds data sampled by the 1st latch until the load signal is triggered. The DAC converts 6-bit digital signals to analog signals according to the reference voltage. Finally, the buffer drives a display panel with exact gamma voltage control. In addition to these circuit blocks, a 1:2 DEMUX circuit and electrostatic discharge prevention circuits are also included in the data driver simulation. To run the data driver simulation, the digital blocks for the shift registers, the 1st latch for sampling and the 2nd latch for holding were modeled by VHDL. SPICE was used for the digital-to-analog converters (DACs) and the output buffers to guarantee the accuracy of the data driver. For a SPICE vs. mixed-signals simulation comparison, the ELDO program was used for SPICE simulation with the level RPI 62 polySi TFT model. For the scan driver, it usually takes too long time to simulate the whole 240-stage-output with SPICE. In general 20 stages are simulated for verification of the circuit design. On the other hand, the data driver has 360 DAC outputs but only one DAC output can normally be simulated by SPICE due to time and capacity limitations. However, we used the full outputs of both for the SPICE vs. mixed-signals simulation comparison.

For IR-drop modeling, we consider the metal lines in the OLED panel as the distributed T-model. When we calculate RC delay of an arbitrary metal line, we suppose the RC value of the metal line is minutely distributed across the whole metal line. Thus, we can apply Elmore RC delay calculation model [6]. With the distribution model of the metal line we can infer the time constant of the metal line as RC/2. Using T or G model, we can convince RC/2 time constant keeping total R and C value of the metal line. The cathode plate in OLED can be divided into unit cells with a lumped element model for each cell that consists of an equivalent circuit with R, L, C, and G components for a rectangular structure [7,8] and each unit cell can be represented using either T or G model. But L and G components can be ignored because the operating maximum frequency of the panel is less than 50 kHz. Fig. 3 shows the equivalent circuit of a sub-pixel that is used for pixel simulation. The outputs of the mixed-signals simulation were used as a part of netlist of the OLED panel for the full panel simulation. Fast-SPICE is used for the full panel simulation with a full panel netlist, and an Image view program is used to see the image quality of the simulation result. 3. Results and discussion For the mixed-signals simulation of the scan driver, the level shifter circuit block was modeled with an analog behavioral model using VHDL-AMS. Fig. 4 shows the rising and the falling delay characteristics of the level shifter block conducted by ELDOTM in SPICE and ADVance MSTM in VHDL-AMS. The modeling used a simple ramp type of the pulse in which the rising time and the falling time were, respectively, 170 and 176 ns in the threshold of 2.5 V. There was a maximum error value of 110 ns when the pulse falls. Precision modeling can remove this error, but that is beyond the scope of this paper. Then, the scan driver was run through mixed-signals simulation using ADVance MS. As a result, the digital and the analog behavioral model were substituted, respectively, for the shift register and the level shifter block, even though there was no change to the output buffer. This took 3276 s in the digital/analog behavioral modeling mixed-signals simulation, approximately 19 times faster than SPICE. The number of the components used in mixed-signals simulation was only 1975 s which were 18% of the components used in SPICE simulation. The comparison between the SPICE and the mixed-signals simulation was summarized in Table 1. Fig. 5 shows the output waveform of the scan driver at 240th stage with both SPICE and mixed-signals simulation. The maxi-

Fig. 2. Block diagram of a data driver and its simulation methods.

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Table 1 The comparison of a scan driver simulation between mixed-signals simulation and SPICE

Transient time (s) Number of nodes Number of components Simulation time (s)

Fig. 3. The equivalent circuit of AMOLED sub-pixel including current-supply metal line and cathode-plate resistances.

mum timing difference of the scan signals between SPICE and mixed-signals modeling was 38.3 ns. It is thought that the time difference will have no serious effect on the whole system timing. For the mixed-signals simulation of the data driver, the timing of the modeled shift registers and latches were examined. Fig. 6 shows the rising time comparison of the unit shift register blocks and the unit latch, respectively, between SPICE and mixed-signals

SPICE

Mixed-signals simulation

0.034 69,657 10,616 61,686

0.034 10,584 1975 3276

simulation. The timing difference of the latch between SPICE and mixed-signals modeling was less than 2 ns. As a result of the modeling, the components of the data driver were reduced to about 25%, from 162,038 to 40,393. The full data driver simulation was undertaken using ADVance MS in 21,504 s, whereas SPICE failed completely, since the number of components exceeded computer memory and SPICE capacity, highlighting SPICE’s limitation. The mixed-signals simulation of the full data driver with the 360 output channels with 1:2 DEMUX for the QVGA resolution is shown in Fig. 7. The HEN signal is a load signal for the holding latch and the PRE signal is a pre-charge signal for fast charging. DMO (for odd pixels), and DME (for even pixels) signals are enable signals for DEMUX. V(ROUT[239]) and V(ROUT[240]) are output waveforms of the 239th and 240th red sub-pixel, respectively. It is thought that the result shows a good accuracy for the full panel simulation. Fig. 8 shows the result of IR-drop simulation depending on the placement and material changes of VDD metal lines. As shown in Fig. 8(a), there were 24 gray level differences in the panel when the VDD metal line is placed on the top side of the panel only. However, if the VDD metal lines are placed on both top and bottom side of the panel as shown in Fig. 8(b), the variation of the gray level was reduced to 9 levels, which can still cause a problem in the image quality. When the material of the VDD and VSS metal lines are changed to

Fig. 4. The delay characteristics of a level shifter simulated by mixed-signals simulation and SPICE.

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Fig. 5. The output waveform of the scan driver at 240th stage with both SPICE and mixed-signals simulation.

Fig. 6. Rising time comparison between SPICE and mixed-signals simulation of (a) an unit shift register, (b) an unit latch.

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Fig. 7. The output waveform of the full data driver at 240th stage simulated by mixed-signals simulation.

Fig. 8. The IR-drop simulation results for QVGA resolution display according to the placement and material changes of VDD metal lines (a) VDD metal line is placed on the top side only, (b) VDD metal lines are placed on both top and bottom side of a panel, (c) the material of VDD and VSS metal lines are changed to ITO/Ag alloy.

ITO/Ag alloy, the variation of the gray level was reduced to 2 levels as shown in Fig. 8(c). From the IR-drop simulation, we concluded that the uniformity enhancement in the OLED panel could be achieved by using the low resistance of ITO/Ag alloy as metal lines, which was about 20% less than that of ITO metal lines.

4. Conclusions We applied the mixed-signals simulation to reduce cost and design lead time in designing SOG panel for poly-Si TFT OLEDs. Using the mixed-signals simulation we achieved full panel simulation

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from peripheral circuits to the OLED panel with the circuit design of the integrated scan and data driver for QVGA mobile AMOLED. The simulation results of the scan driver state that the mixed-signals simulation is 19 times faster than the SPICE simulation with fairly good accuracy. The full data driver circuit was run by mixed-signals simulation, whereas SPICE failed completely. IRdrop effect was included in OLED pixel modeling and uniformity degradation of the OLED panel could be improved by the full panel simulation.

Acknowledgment This work was supported by the Sunmoon University Research Grant of 2008.

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