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Design of Viterbi Decoder Based on FPGA
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Physics Procedia
Physics Procedia 00 (2011) Physics Procedia 24000–000 (2012) 1243 – 1247 www.elsevier.com/locate/procedia
2012 International Conference on Applied Physics and Industrial Engineering
Design of Viterbi Decoder Based on FPGA WANG Xiumin，ZHANG Yang, CHEN Haowei College of Information Engineering China Jiliang University Hangzhou,China
Abstract The minimum bit width of the path metrics at the premise of not affecting the performance are calculated out, in order to reduce the storage resources cost in the design of convolutional code decoders. A simple method is proposed to judge the state nodes which the decoder can reach at each clock cycle during the setup process. Simulation platform to verify the proposed scheme has been set up with the matlab software , after that a decoder of (2,1,8) convolutional code with generating polynomial (561,753) is designed. Result of comparison with other designs shows that the scheme proposed greatly improves the throughput of the decoder at the cost of fewer resources.
© 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of ICAPIE Organization © 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [name organizer] Committee. Keywords: FPGA, convolutional code, viterbi, Verilog HDL
1. Introduction Convolutional code is a commonly used forward error-correction code in deep space communication system and wireless communication system[1-4]. It is also adopted in the wireless digital cellular communication standard of IS - 95、CDMA[3]. The turbo code which is applied in the third generation wireless communication system is also derived from convolutional code[5-6]. There are two algorithms to implement the decoder of convolutional code i.e. Viterbi algorithm and sequence decoding algorithm[7]. Decoders based on sequence decoding algorithm has simpler structure, but their output delay time is uncertain, so they are only applied in non-real time area. Viterbi algorithm is the most likelihood decoding algorithm for the convolutional code. Its principle is to find out a path of the most similarity with the received code sequence by searching all the possible paths in the trellis graph. It is an effective algorithm for the realization of decoders of convolutional code whose constraint length is no larger than 10. According to the methods used to measure the similarity, decoders of convolutional code
1875-3892 © 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of ICAPIE Organization Committee. doi:10.1016/j.phpro.2012.02.186
1244
WANG Xiumin et al. / Physics Procedia 24 (2012) 1243 – 1247 Author name / Physics Procedia 00 (2011) 000–000
can also be divided into two types: hard decision decoders which measure the similarity by hamming distance and soft decision decoders which measure by Euclidean distance[7-8] . 2. Key problems in designing viterbi decoder and solutions 2.1 Working procedural of the viterbi decoder[6] z z z
Calculate the branch metric BM of each state node. i.e. the similarity of the output code word of the state node which transfers to the current state and the code word received at current time. In the case of binary hard decision , BM is the hamming distance between the two code words. Calculate the similarity of the most likelihood path of each state node i.e. path metric PM . Decoding output and update of the surviving path of each state node.
2.2 Key problems in designing viterbi decoder and solutions 1) Realization of the startup process. (2,1,8) convoluitional code decoder has 256 state nodes. When dealing with the ith code word (i is an integer larger than 0 but smaller than 9) input during the startup process.. only 2i state nodes can be reached [8] For these 2i state nodes , there is only one node can reach each of them. The state node transition diagram is as shown in Fig.1 The key problem is how to decide which state node can be reached and therefore should be dealt with . It is found out that if and only if the lowest (8-i) bits of the binary form of the state value of one node are all 0s , then it can be reached after dealing of the ith code word. According to this point , a simple method is designed in this paper for the judgment. Set a register variant sd0 whose initial value is assigned 0x7f, i.e. its MSB is set 0 and all the other bits are set 1. sd0 is right shifted by 1 bit after dealing of each input code word. When deciding whether the jth state node (j=1,2,…255) should be dealt. the only thing should be don is to calculate the bitwise and result of (j-1) and sd0. if it is 0, then the state node should be dealt , otherwise turn to deal with the next (j+1) th state node directly. 2) Overflow of the path metric[4, 10] .Since the path metric of each state node is increasing all the time and they are of different sizes , as the decoding process continues , the path metric with the largest value will overflow first . when this happens, errors will occur in the decoding result. So how to solve this problem is the second key problem. After analyzing the trellis graph of decoding process, the author find out that when adopting hard decision method ,the difference between the maximum and minimum value of the 256 path metrics is input 0
state i
state（2*i） input 1
state (i+ 128)
Figure 1 State node transition diagram of the (2,1,8)convolutional code decoder
no larger than 15. If the width of variants used to store the path metrics are 5 bits ,then at the time the largest path metric reaches 31 and will overflow ,the minimum path metric is no little than 16, By subtracting 16 from all the 256 path metrics. the path metric of any state node will no longer overflow. We can judge whether a path metric is no smaller than 16 simply by the value of its most significant bit (MSB). 3) Storage of the surviving path of each state node. There are two medias can be used to store the surviving path and path metric of each state node when implementing convolutional code decoders with
WANG Xiumin et al. / Physics Procedia 24 (2012) 1243 – 1247 Author name / Physics Procedia 00 (2011) 000–000
FPGA: RAM and registers. Correspondingly there are two decoding output strategies : trackback method and direst output method[9,11]. When adopting the first method ,the circuit synthesized will has a simpler interconnection and lower working power, cost less ship area. The shortcoming of it is that every time it output a bit of decoding result , a length of decoding depth which is usually five to ten times constraint length of the convolutional code should be trackbacked , so its decoding speed is slower. When using the second method, the decoding result can be output directly as soon as the decoding depth is reached. So the decoding speed is much faster. and it is suitable for high speed application. its shortcoming is that it costs larger chip area and consumes higher power . to achieve a high speed , the second method is selected in the design. 3. Verification of tbe scheme According to the strategies described above, A simulation model is setup on the matlab 7.0.1 software platform, and then the performance of the decoder under Gaussian white noise channel is tested. The whole test system is divided into five modules: source code generating module ,encoding module ,modulating ,noise-adding, demodulating and decision module ,decoding output module ,and bit error rate calculation module The working procedural of the test system is as shown in Fig.2. The source code generating module generate random sequence with almost equal number of 0s and 1s .The encoding module encode the random sequence of data into frames. The modulating ,noiseadding, demodulating and decision module simulate the whole process the encoded convolutional code going through before decoding by the decoder at the receiver end, which includes modulating, transmission in the Gaussian white noise channel ,demodulation at receiver end. The decoding module decode the data sequence generated after decision into a sequence composed of 0s and 1s . The bit error rate(BER) calculation module calculates the bit error rate of the decoder under specified Gaussian white noise channel. Considering that the BER will gets smaller and smaller as the SNR increases , a total number of 1000 frames of data is
Figure 2 Working procedural of the test system
used to test the performance of (2,1,8) convolutional code under each type of Gaussian white noise channel with a specified SNR. Therefore the total number of data tested under each SNR is 100*1000=100000. The performance of the decoder under the channel with SNR 0 db. 0.5 db，1 db， 1.5 db，2 db，2.5 db，3db is tested respectively. The curve output is as shown in Fig.3 , from which we can see clearly that as the value of SNR increases, the corresponding value of BER decreases. When the SNR reaches 2.3db ,the value of BER is about 10-4 which is agrees with the theoretical value. Therefore the solutions proposed in this paper is correct. 4. FPGA Implementation and Hardware Simulation On the integrated development platform Quartus2, the code of both encoder and decoder are written, and then complied and synthesized. When the input information bits are 100000000, the encoder outputs the codeword bits 313321013 after one clock cycle’s delay. The input of the decoder is then obtained by inverting the first 5 successive bits of this codeword. The simulation result is shown in Fig 4.
1245
1246
WANG Xiumin et al. / Physics Procedia 24 (2012) 1243 – 1247 Author name / Physics Procedia 00 (2011) 000–000
According to the principle in error-correcting encoding . When the minimum distance between any two codeword in a Linear block code is dmin, then the number of error bits the code can correct is no more than [(dmin-1)/2]. Since the equivalent minimum distance of (561,753) convolutional code is 12, it should be able to correct any 5 successive bits errors. From the waveform above , it can be seen that after a delay of 47 clock cycles, the decoder correct all the errors ,So the design of the decoder is correct. 5. Performance of the decoder When selecting EP1S20F484C5 as the target device, the synthesis report shows that the decoder consumes 14226 logic elements and can working at the highest working frequency of 102MHz. In contrast , when using RAM to store the path metrics and selecting APEX EP20K200 as the target device ,the design proposed in[10] consumes totally 2200 logic elements and 16 block RAMs, the working frequency is only 40MHz and the corresponding decoding rate is 588 kb/s.
Figure 3 Performance of the designed (2,1,8) convoluitional code decoder
Figure 4 hardware simulation result of the designed (2,1,8) convoluitional code decode
At the cost of only a few hardware, the design proposed in this paper obtains a high improvement in performance. 6. Conclusion An effective method for the implementation of the setup process of viterbi decoders is proposed. The minimum data width to store the path metrics of each state node is calculated out. On the matlab software ,the simulation platform testing the scheme is setup. Simulation result proves the feasibility of the scheme. After that a (2,1,8) convolutional code with generating polynomial (561,753) is designed based on FPGA technology in Verilog HDL language on the platform of Quatrus2. Result of comparison with other designs proves the advantages of the design.
1247
WANG Xiumin et al. / Physics Procedia 24 (2012) 1243 – 1247 Author name / Physics Procedia 00 (2011) 000–000
Acknowledgment
The authors gratefully acknowledge the financial support from the Foundation of Science and Technology Planning Project 2009 by the General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China (2009QK027). Reference [1]Liu Guofang, Cheng Naiping. An Improved Viterbi Decoding Algorithm. Journal of Telemetry, Tracking, and Command, 2006, 27(1):30-32. [2]An Yong , Mu Rong2zeng , Cao Xiaolin , Yan Yuepeng. The RTL Implementation of a Punctured Convolutional Coding and Decoding. Micro Electronics & Computer, 2008,25(8):106-109. [3]E Wei,Su Guangchuan. Optimization and Realization of High Speed Viterbi Decoder. Application of Electronics Technology, 2003,(4): 50-51, 60.. [4]Liu Xiaoying ,Wang Yi ,Wang Xinan. A High Speed Viterbi Circuit Implementation for WLAN System. Computer Technology and Development, 2008, 18(1): 11-13, 51. [5]Chu Gang, Wang Wenbo, Chang Yongyu, Li Zonghao, System and Principle of Mobile Communications. Beijing: Press of Beijing Posts and Telecommunications University,2005, 119-120. [6]Cao Xuehong, Zhang Zongcheng. Information Theory and Encoding. Bejing, Press of Tsinghua University, 2004:58. [7]FANG
jinming.Soft
Decision
Viterbi
and
Sequential
Decoding
on
FPGA.Bulletin
of
Science
and
Technology.2003,19(4):344-347. [8]Li Zongbo , Zhang Puheng , Zhang Botao , Hu Wenmin , Liu Hengz hu. A Kind of Improved Viterbi Decoder. Journal of Beijing Jiaotong University, 2008, 32(6): 69-72. [9]Zhang Jian, Liu Xiaolin, Kuang Jingming, Wang Hua. FPGA Implementation of a High - Speed Viterbi Decoder. telecommunication technology., 2006,(3):37-41. [10]Zhang Changfang, Lei Jing. Design and Implementation of SurvivorMemory Unit in High Speed Viterbi Decoder. Electronic engineer, 2005: 31(3): 11-13. [11]Kang Guixia ,Lin Hui ,Wang Ting ,Zhang Ping. The Design and Implementation of a General2purpo se and High Speed Viterbi Decoder in the 3G Mobile Communication Systems. .
ACTA ELECTRONICA SINICA, 2000, 28(11A): 152-154.
Physics Procedia
Physics Procedia 00 (2011) Physics Procedia 24000–000 (2012) 1243 – 1247 www.elsevier.com/locate/procedia
2012 International Conference on Applied Physics and Industrial Engineering
Design of Viterbi Decoder Based on FPGA WANG Xiumin，ZHANG Yang, CHEN Haowei College of Information Engineering China Jiliang University Hangzhou,China
Abstract The minimum bit width of the path metrics at the premise of not affecting the performance are calculated out, in order to reduce the storage resources cost in the design of convolutional code decoders. A simple method is proposed to judge the state nodes which the decoder can reach at each clock cycle during the setup process. Simulation platform to verify the proposed scheme has been set up with the matlab software , after that a decoder of (2,1,8) convolutional code with generating polynomial (561,753) is designed. Result of comparison with other designs shows that the scheme proposed greatly improves the throughput of the decoder at the cost of fewer resources.
© 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of ICAPIE Organization © 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [name organizer] Committee. Keywords: FPGA, convolutional code, viterbi, Verilog HDL
1. Introduction Convolutional code is a commonly used forward error-correction code in deep space communication system and wireless communication system[1-4]. It is also adopted in the wireless digital cellular communication standard of IS - 95、CDMA[3]. The turbo code which is applied in the third generation wireless communication system is also derived from convolutional code[5-6]. There are two algorithms to implement the decoder of convolutional code i.e. Viterbi algorithm and sequence decoding algorithm[7]. Decoders based on sequence decoding algorithm has simpler structure, but their output delay time is uncertain, so they are only applied in non-real time area. Viterbi algorithm is the most likelihood decoding algorithm for the convolutional code. Its principle is to find out a path of the most similarity with the received code sequence by searching all the possible paths in the trellis graph. It is an effective algorithm for the realization of decoders of convolutional code whose constraint length is no larger than 10. According to the methods used to measure the similarity, decoders of convolutional code
1875-3892 © 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of ICAPIE Organization Committee. doi:10.1016/j.phpro.2012.02.186
1244
WANG Xiumin et al. / Physics Procedia 24 (2012) 1243 – 1247 Author name / Physics Procedia 00 (2011) 000–000
can also be divided into two types: hard decision decoders which measure the similarity by hamming distance and soft decision decoders which measure by Euclidean distance[7-8] . 2. Key problems in designing viterbi decoder and solutions 2.1 Working procedural of the viterbi decoder[6] z z z
Calculate the branch metric BM of each state node. i.e. the similarity of the output code word of the state node which transfers to the current state and the code word received at current time. In the case of binary hard decision , BM is the hamming distance between the two code words. Calculate the similarity of the most likelihood path of each state node i.e. path metric PM . Decoding output and update of the surviving path of each state node.
2.2 Key problems in designing viterbi decoder and solutions 1) Realization of the startup process. (2,1,8) convoluitional code decoder has 256 state nodes. When dealing with the ith code word (i is an integer larger than 0 but smaller than 9) input during the startup process.. only 2i state nodes can be reached [8] For these 2i state nodes , there is only one node can reach each of them. The state node transition diagram is as shown in Fig.1 The key problem is how to decide which state node can be reached and therefore should be dealt with . It is found out that if and only if the lowest (8-i) bits of the binary form of the state value of one node are all 0s , then it can be reached after dealing of the ith code word. According to this point , a simple method is designed in this paper for the judgment. Set a register variant sd0 whose initial value is assigned 0x7f, i.e. its MSB is set 0 and all the other bits are set 1. sd0 is right shifted by 1 bit after dealing of each input code word. When deciding whether the jth state node (j=1,2,…255) should be dealt. the only thing should be don is to calculate the bitwise and result of (j-1) and sd0. if it is 0, then the state node should be dealt , otherwise turn to deal with the next (j+1) th state node directly. 2) Overflow of the path metric[4, 10] .Since the path metric of each state node is increasing all the time and they are of different sizes , as the decoding process continues , the path metric with the largest value will overflow first . when this happens, errors will occur in the decoding result. So how to solve this problem is the second key problem. After analyzing the trellis graph of decoding process, the author find out that when adopting hard decision method ,the difference between the maximum and minimum value of the 256 path metrics is input 0
state i
state（2*i） input 1
state (i+ 128)
Figure 1 State node transition diagram of the (2,1,8)convolutional code decoder
no larger than 15. If the width of variants used to store the path metrics are 5 bits ,then at the time the largest path metric reaches 31 and will overflow ,the minimum path metric is no little than 16, By subtracting 16 from all the 256 path metrics. the path metric of any state node will no longer overflow. We can judge whether a path metric is no smaller than 16 simply by the value of its most significant bit (MSB). 3) Storage of the surviving path of each state node. There are two medias can be used to store the surviving path and path metric of each state node when implementing convolutional code decoders with
WANG Xiumin et al. / Physics Procedia 24 (2012) 1243 – 1247 Author name / Physics Procedia 00 (2011) 000–000
FPGA: RAM and registers. Correspondingly there are two decoding output strategies : trackback method and direst output method[9,11]. When adopting the first method ,the circuit synthesized will has a simpler interconnection and lower working power, cost less ship area. The shortcoming of it is that every time it output a bit of decoding result , a length of decoding depth which is usually five to ten times constraint length of the convolutional code should be trackbacked , so its decoding speed is slower. When using the second method, the decoding result can be output directly as soon as the decoding depth is reached. So the decoding speed is much faster. and it is suitable for high speed application. its shortcoming is that it costs larger chip area and consumes higher power . to achieve a high speed , the second method is selected in the design. 3. Verification of tbe scheme According to the strategies described above, A simulation model is setup on the matlab 7.0.1 software platform, and then the performance of the decoder under Gaussian white noise channel is tested. The whole test system is divided into five modules: source code generating module ,encoding module ,modulating ,noise-adding, demodulating and decision module ,decoding output module ,and bit error rate calculation module The working procedural of the test system is as shown in Fig.2. The source code generating module generate random sequence with almost equal number of 0s and 1s .The encoding module encode the random sequence of data into frames. The modulating ,noiseadding, demodulating and decision module simulate the whole process the encoded convolutional code going through before decoding by the decoder at the receiver end, which includes modulating, transmission in the Gaussian white noise channel ,demodulation at receiver end. The decoding module decode the data sequence generated after decision into a sequence composed of 0s and 1s . The bit error rate(BER) calculation module calculates the bit error rate of the decoder under specified Gaussian white noise channel. Considering that the BER will gets smaller and smaller as the SNR increases , a total number of 1000 frames of data is
Figure 2 Working procedural of the test system
used to test the performance of (2,1,8) convolutional code under each type of Gaussian white noise channel with a specified SNR. Therefore the total number of data tested under each SNR is 100*1000=100000. The performance of the decoder under the channel with SNR 0 db. 0.5 db，1 db， 1.5 db，2 db，2.5 db，3db is tested respectively. The curve output is as shown in Fig.3 , from which we can see clearly that as the value of SNR increases, the corresponding value of BER decreases. When the SNR reaches 2.3db ,the value of BER is about 10-4 which is agrees with the theoretical value. Therefore the solutions proposed in this paper is correct. 4. FPGA Implementation and Hardware Simulation On the integrated development platform Quartus2, the code of both encoder and decoder are written, and then complied and synthesized. When the input information bits are 100000000, the encoder outputs the codeword bits 313321013 after one clock cycle’s delay. The input of the decoder is then obtained by inverting the first 5 successive bits of this codeword. The simulation result is shown in Fig 4.
1245
1246
WANG Xiumin et al. / Physics Procedia 24 (2012) 1243 – 1247 Author name / Physics Procedia 00 (2011) 000–000
According to the principle in error-correcting encoding . When the minimum distance between any two codeword in a Linear block code is dmin, then the number of error bits the code can correct is no more than [(dmin-1)/2]. Since the equivalent minimum distance of (561,753) convolutional code is 12, it should be able to correct any 5 successive bits errors. From the waveform above , it can be seen that after a delay of 47 clock cycles, the decoder correct all the errors ,So the design of the decoder is correct. 5. Performance of the decoder When selecting EP1S20F484C5 as the target device, the synthesis report shows that the decoder consumes 14226 logic elements and can working at the highest working frequency of 102MHz. In contrast , when using RAM to store the path metrics and selecting APEX EP20K200 as the target device ,the design proposed in[10] consumes totally 2200 logic elements and 16 block RAMs, the working frequency is only 40MHz and the corresponding decoding rate is 588 kb/s.
Figure 3 Performance of the designed (2,1,8) convoluitional code decoder
Figure 4 hardware simulation result of the designed (2,1,8) convoluitional code decode
At the cost of only a few hardware, the design proposed in this paper obtains a high improvement in performance. 6. Conclusion An effective method for the implementation of the setup process of viterbi decoders is proposed. The minimum data width to store the path metrics of each state node is calculated out. On the matlab software ,the simulation platform testing the scheme is setup. Simulation result proves the feasibility of the scheme. After that a (2,1,8) convolutional code with generating polynomial (561,753) is designed based on FPGA technology in Verilog HDL language on the platform of Quatrus2. Result of comparison with other designs proves the advantages of the design.
1247
WANG Xiumin et al. / Physics Procedia 24 (2012) 1243 – 1247 Author name / Physics Procedia 00 (2011) 000–000
Acknowledgment
The authors gratefully acknowledge the financial support from the Foundation of Science and Technology Planning Project 2009 by the General Administration of Quality Supervision, Inspection and Quarantine of the People's Republic of China (2009QK027). Reference [1]Liu Guofang, Cheng Naiping. An Improved Viterbi Decoding Algorithm. Journal of Telemetry, Tracking, and Command, 2006, 27(1):30-32. [2]An Yong , Mu Rong2zeng , Cao Xiaolin , Yan Yuepeng. The RTL Implementation of a Punctured Convolutional Coding and Decoding. Micro Electronics & Computer, 2008,25(8):106-109. [3]E Wei,Su Guangchuan. Optimization and Realization of High Speed Viterbi Decoder. Application of Electronics Technology, 2003,(4): 50-51, 60.. [4]Liu Xiaoying ,Wang Yi ,Wang Xinan. A High Speed Viterbi Circuit Implementation for WLAN System. Computer Technology and Development, 2008, 18(1): 11-13, 51. [5]Chu Gang, Wang Wenbo, Chang Yongyu, Li Zonghao, System and Principle of Mobile Communications. Beijing: Press of Beijing Posts and Telecommunications University,2005, 119-120. [6]Cao Xuehong, Zhang Zongcheng. Information Theory and Encoding. Bejing, Press of Tsinghua University, 2004:58. [7]FANG
jinming.Soft
Decision
Viterbi
and
Sequential
Decoding
on
FPGA.Bulletin
of
Science
and
Technology.2003,19(4):344-347. [8]Li Zongbo , Zhang Puheng , Zhang Botao , Hu Wenmin , Liu Hengz hu. A Kind of Improved Viterbi Decoder. Journal of Beijing Jiaotong University, 2008, 32(6): 69-72. [9]Zhang Jian, Liu Xiaolin, Kuang Jingming, Wang Hua. FPGA Implementation of a High - Speed Viterbi Decoder. telecommunication technology., 2006,(3):37-41. [10]Zhang Changfang, Lei Jing. Design and Implementation of SurvivorMemory Unit in High Speed Viterbi Decoder. Electronic engineer, 2005: 31(3): 11-13. [11]Kang Guixia ,Lin Hui ,Wang Ting ,Zhang Ping. The Design and Implementation of a General2purpo se and High Speed Viterbi Decoder in the 3G Mobile Communication Systems. .
ACTA ELECTRONICA SINICA, 2000, 28(11A): 152-154.