- Email: [email protected]
ID methodology
Journal Pre-proof Design Technique for Regulated Cascode Transimpedance Amplifier Using Gm/ID Methodology
Motaz M. Elbadry, Mostafa Y. Makkey, Mohamed Abdelgawad, Mohamed Atef PII:
S0026-2692(19)30609-3
DOI:
https://doi.org/10.1016/j.mejo.2019.104676
Reference:
MEJ 104676
To appear in:
Microelectronics Journal
Received Date:
21 July 2019
Accepted Date:
03 December 2019
Please cite this article as: Motaz M. Elbadry, Mostafa Y. Makkey, Mohamed Abdelgawad, Mohamed Atef, Design Technique for Regulated Cascode Transimpedance Amplifier Using Gm/ID Methodology, Microelectronics Journal (2019), https://doi.org/10.1016/j.mejo.2019.104676
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain. © 2019 Published by Elsevier.
Journal Pre-proof
Design Technique for Regulated Cascode Transimpedance Amplifier Using Gm/ID Methodology Motaz M. Elbadry, Mostafa Y. Makkey, and Mohamed Abdelgawad, Mohamed Atef, Senior, IEEE
Abstract—This paper presents an approach using gm/ID methodology for the design of the regulated cascode circuit (RGC) transimpedance amplifier (TIA) for optical receivers. The framework uses lookup tables produced using the gm/ID methodology to define the sizing of the transistors needed to reach the required specifications. The framework has the advantage of setting limits on the design space using intuitive equations derived from the circuit analyses. This gives insight into the effect of changing the value of different circuit parameters on the resulting design while decreasing the time to reach the desired design. The framework gives the flexibility to minimize the DC power consumption or the total input referred noise. The framework is implemented in a 130 nm CMOS process with a 1.5 V supply voltage producing two different designs. Both designs met the required specifications while optimizing power consumption or noise and were validated using simulations. The results obtained are discussed and compared against other designs from the state-of-the-art.
Index Terms— Transimpedance Amplifier, Optical Receivers, Regulated Cascode, gm/ID methodology.
I. INTRODUCTION The design of transimpedance amplifiers (TIA) as a preamplifier for optical receivers proposes many challenges because of the trade-offs introduced between noise, bandwidth, gain, and power dissipation [1]. Interfacing the large photodiode capacitance is the main concern having the worst effect on bandwidth and noise performance of the circuit. Therefore, it is critical to develop topologies that can relax the input parasitic effects [2]. From the different topologies, the regulated cascode (RGC) circuit is considered for having the advantage of using local feedback to reduce the input resistance seen by the large photodiode capacitance [3]. The RGC topology is one of the widely used and commonly known in the literature, it has been introduced as a front-end amplifier for optical receivers in [2], [4] and [5] due to its numerous merits of wide bandwidth, high gain, and low noise contribution. It was shown to have superior noise performance to other topologies in [6]. Additionally, it was implemented in various technologies including BiCMOS in[7]– [9]. Methods of inductive peaking were used with the topology to further increase its bandwidth [8]–[11] while also being designed in a differential configuration in [5], [9] and low power operation in [3], [7]. Our work uses the gm/Id methodology for designing the RGC circuit. The gm/ID methodology has the advantage of using the generated lookup tables for determining the accurate sizing of transistors to achieve the required specifications. These tables are generated by extracting the different performance parameters of the This paper was submitted on for review on XXXX. Motaz M. Elbadry, Mostafa Y. Makkey, Mohamed Abdelgawad and Mohamed Atef are with the Electrical Engineering Department, Assiut University, Assiut, Egypt. ([email protected], [email protected], [email protected], [email protected]).
transistor (i.e. transit frequency (fT), intrinsic gain (gm/gds), current density (ID/W), and the intrinsic capacitances (Cgs, Cgd) ) as a function of the inversion level (gm/ID). The tables have the advantage of avoiding multiple iterations on simulation programs to find the optimum point for the required design. The gm/ID methodology has been used numerous times in the literature to optimize the noise performance of the analog circuits [12]–[17], minimize power consumption [7], [18]–[20], and to design different TIA topologies for optical receivers [3], [7], [21], [22]. The presented framework uses the lookup tables for the used technology along with closed-form DC signal analysis, noise analysis, and small-signal analysis equations generated either by hand calculations or a computer-aided design program [23]. The resulting equations are used to set the limits on the design space searched for the optimum design. A MATLAB [24] function is written using this framework takes the design specification as inputs (i.e. gain, bandwidth, power dissipation, output voltage swing, photodiode capacitance, output capacitance, and input referred noise) and outputs the circuit parameters achieving these specifications. The output design from the function can favor the optimum design in terms of power dissipation or the input referred noise. The approach is utilized in designing the RGC circuit having the same specifications as [7]. The circuits are implemented in a 130 nm CMOS process with 1.5V supply. The gm/ID methodology and procedure for generating the lookup tables are reviewed in Section II. Section III presents the RGC topology and the equation derived from its analyses used in our framework. Our proposed framework and optimization algorithm along with the method used for defining our design space and optimization technique for the dissipated power and noise performance of the circuit are discussed in Section IV. Section V shows the produced designs from using our work and the results obtained from the simulations and discusses the accuracy of the presented framework. also, the final designs are compared with other works of different topologies in the literature employing the same technology. Finally, we present our main conclusion in Section VI. II. GM/ID METHODOLOGY Sizing transistors in small channel MOSFET has become one of the main design problems in recent years due to the inaccuracy of the square-law model to describe the parameters of the transistors. Hence, this has often led the designers to rely upon multiple iterations to reach the optimum design. Consequently, increasing the difficulty of the design and as a result, the designers lose the intuitive understanding of the effect of different circuit parameters on the final specifications. The limitations associated with the square-law model are mainly due to its inability to account for second-order effects (i.e. channel length modulation and drain induced barrier lowering). These second-order effects become more important as the transistor length decreases reaching the nanoscale size. Therefore, the use of a different methodology becomes necessary. The gm/ID methodology depends on generated lookup tables describing different parameters (i.e. transit frequency, fT, intrinsic
Journal Pre-proof gain, gm/gds, current density, ID/W, and the intrinsic capacitances of the transistor) as a function of the inversion level described by the transconductance efficiency (i.e. gm/ID). In contrast with closed-form equations of the square-law model, the charts are generated from the spice model of the technology provided by the silicon foundry which closely captures the second-order effects. Since the main issue is not the analysis equations that describe the circuit, but the model used to link between the sizing of the transistors and its parameters represented in the circuit.
the transistor has higher transconductance (gm) and higher intrinsic (channel) resistance leading to higher gain. At the same time investigating Fig. 4 this leads to lower current density (ID/W) which requires wider transistor to obtain a certain drain current (ID) value leading to higher capacitance and lower speed.
Fig. 3. Transit frequency (fT) and intrinsic gain (gm/gds) as a function of gm/ID at different inversion levels.
Fig. 1. The test bench used to generate the lookup tables by DC sweeping VDS, VGS, and MOSFET length L for gm/Id methodology.
The lookup tables are produced once by sweeping the intrinsic gain cell in Fig. 1 along three dimensions (i.e. VDS, VGS, and L) and tabulating all the device parameters. We can include the device width (W) as a fourth dimension but this can be neglected since the parameters scale linearly with it. The gm/ID values as a function of overdrive voltage (Vov) typically range between 3 to 30 S/A as illustrated by Fig. 2. The higher gm/ID values represent weak inversion, the midrange values represent moderate inversion typically around 12 to 20 S/A, and the lower values represent strong inversion.
Fig. 2. The transconductance efficiency (gm/ID) as a function of overdrive voltage (Vov) at different levels of inversion at VDS=0.6 V and W=1 m.
Investigating the charts present in Fig. 3 we can see the tradeoff presented by the value of gm/ID and the resulting transit frequency (fT) and intrinsic gain (gm/gds) of the transistors. The last generated chart is the current density (ID/W) as a function of gm/ID at different inversion levels shown in Fig. 4. Fig. 2, Fig. 3 and Fig. 4 indicate that biasing the transistors at weak inversion exhibit low power consumption, higher gain, and voltage swing but at lower speed and large size. The opposite occurs when biased at strong inversion the transistor has higher speed, smaller size, decreased voltage swing, and lower gain. This can be understood by the fact that at higher gm/ID values corresponding to weak inversion,
Fig. 4. The current density (ID/W) as a function of gm/ID at different inversion levels
III. MODELING OF REGULATED CASCODE CIRCUIT The RGC topology is a well-known circuit as the first stage of the optical receiver where the photocurrent detected by the photodiode is amplified and converted to a voltage signal at the output. The low input impedance of the RGC topology due to the local feedback gives it many advantages over other topologies in terms of higher bandwidth achieved at lower power [2]. It can be seen from the circuit diagram of the RGC in Fig. 5 that the topology has two transistors M1 and MB. Transistor M1 acts as the main amplifier. The photocurrent signal at the source is amplified to a voltage signal at the drain. MB is used to provide negative feedback to reduce the input impedance and improve the bandwidth. A) DC Analysis: By investigating the DC analysis of the RGC circuit shown in Fig. 5, it is evident that the power dissipation is equal to the power supply voltage multiplied by the drain currents of transistors M1 and MB.
Pdiss VDD ( I D1 I DB )
(1)
Also, the drain to source voltage of MB is equal to the gate to source voltage of both transistors.
VDSB VGS 1 VGSB
(2)
Journal Pre-proof C XZ Cgs1 CgdB
(6)
Where Cgs1 is the parasitic capacitance from the gate to the source of transistor M1, and CgdB is the parasitic capacitance from the gate to the drain of transistor MB.
C XY Cdb1
(7)
Where Cdb1 is the parasitic capacitance from the drain to the bulk of transistor M1.
CYZ C gd 1
(8)
Where Cgd1 is the parasitic capacitance between the gate and the drain of transistor M1. The transfer function of the RGC circuit is obtained by the help of the symbolic analysis on the computer-aided design software SapWin [23]. The transfer function has two zeros and three poles in which two are complex conjugate poles and one simple pole. The two zeros are represented by:
N ( s ) as 2 bs c Fig. 5. The RGC circuit schematic diagram.
and z1,2
b b 2 4ac 2a
(9)
Where N(s) is the representation of the zeros in the Laplace domain while a, b, and c are coefficients of the second-order polynomial. The coefficients of the polynomial can be approximated by:
a C XZ C XY CYZ C XZ CYZ C XY CZ C XY RB , b C XY CYZ ( g m1 g mB ) g m1CZ RB ,
(10)
and c g m1 1 g mB RB Fig. 6. The RGC small-signal model.
B) AC analysis: The RGC small-signal model in Fig. 6 contains five parasitic capacitances CX, CY, CZ, CXZ, and CYZ between different nodes as explained in [3]. These capacitances are as follows:
C X CPD C gsB
(4)
Where CL is the capacitance of the load at the output of the circuit.
CZ CdbB
z1,2
c a
(3)
Where CPD is the capacitance of the photodiode and CgsB is the parasitic capacitance between the gate and source of transistor MB.
CY CL
Examining the values of the coefficients it is deduced that the two zeros are complex conjugate and by using the fact that b2<<4ac then the magnitude of the zeros can be approximated by:
(5)
Where CdbB is the parasitic capacitance from the drain to the bulk of transistor MB.
z1,2
g m1 1 g mB RB
(11)
C XZ C XY CYZ C XZ CYZ C XY CZ C XY RB
Comparing the value presented by (11) with the transit frequency given by fT = gm/Cgg; where Cgg is the total gate capacitance of the transistor; we deduce that this value is higher than the transit frequency. Thus, it is shown that the values of the zeros occur at a much higher frequency than the poles so that they can be neglected, and the transfer function can be approximated by:
A( s )
A0 s
s2
s (1 )(1 2 ) p1 0 0Q
(12)
Journal Pre-proof IV. THE PROPOSED DESIGN FRAMEWORK The two poles of the transfer function are:
p1 p1 p2,3
0 2Q
(1 1 4Q 2 )
(13) (14)
The simple pole is dependent on the time constant at the input and output of the circuit at nodes X and Y [3], [6]. these time constants can be written as:
τ X C X RX and τY CY RY
(15)
Where RX and RY are the resistances seen respectively at the input and output:
RX R S
1 g m1 (1 g mB RB )
(16)
and
RY R1
(17)
The midband gain A0 in (12) is equal to:
A0 R1
g m1 RS (1 g mB RB ) g m1 RS (1 g mB RB ) 1
(18)
The purpose of our framework is to use the lookup tables generated by the gm/ID methodology to determine the proper sizing of the transistors achieving the required specifications of the final design. However, the difficulty arises from the fact that our design space needs to be limited in order to decrease the processing time and efforts needed to find the appropriate circuit parameters. The equations obtained from the different types of circuit analyses presented in the previous section III can be manipulated to achieve these specifications. Finally, an algorithm can be implemented using a proper programming tool; which is MATLAB in our case; utilizing this framework to search the reduced design space for valid solutions. Keeping in mind the fact that more than one solution could be found for the given specifications, certain criteria are applied to reach an optimum design with respect to two different parameters either the DC power dissipation of the circuit or its noise performance. First, we need to define the constraints that are applied to our design space limiting the amount of search needed to pinpoint the required design. Intuitively, these constraints are set on the different sweeping parameters defining our design space. The merit of using the gm/ID lookup tables is that we only need to choose the value of gm/ID for both transistors in the circuit and by picking the right value of drain current (ID) for each transistor we can check whether this design meets the specification. This is a result of the fact that all circuits’ parameters are related to the gm/ID value and its sweeping parameters. Accordingly, the constraints are needed to only define two different variables which are: the transconductance efficiency (gm/ID) and the drain current (ID) of the two transistors. (A) The Framework Equations: Inspecting the DC analysis of the RGC circuit, the minimum value for the drain current of transistor M1 is directly related to the required output voltage swing:
I D1,min
if gm1RS(1+gmBRB) >> 1 the midband gain can be approximated by:
A0 R1
(19)
C) Noise Analysis: Examining the noise analysis of the RGC topology, it is noted that the noise generated by the transistor MB is dominant and has the highest contribution to the total input referred noise of the circuit [6]. The input referred noise current spectral density of the circuit due to MB can be given by:
I n ,in 2
RS CPD 12 4 KT g mB B 2 g mB RS
(20)
Where K is the Boltzmann’s constant, T is the absolute temperature, and ϒ is the noise factor of the transistor. After integrating this equation, we can get the total root mean squared (rms) input referred noise current given by:
I n,in,rms 4 KT
b 4 2 Bn3CPD 2 4 Bn 2CPD Bn 2 g mB 3 2 RS RS
Where BN is the equivalent noise bandwidth.
(21).
output voltage swing 2 R1
(22)
Also, the maximum limit for the drain currents of the transistors is set by the power consumption of the circuit
I D1,max I DB ,max
PDC VDD
(23)
Where PDC is the total DC power consumption and VDD is the DC supply voltage. Finally, to find the lower limit for the drain current of transistor MB, we use (21) and multiplying both sides by IDB
I DB ,min
4 KT I n,in,rms 2
B 4 2 Bn3CPD 2 4 Bn2CPD Bn 2 3 2 RS RS gm I D B
(24)
Before deriving the equations defining the limits on the (gm/ID) value of the transistors. It is useful to note that transistors M1 can be viewed as a common gate amplifier, while transistor MB as a common source amplifier thus:
AV 1 g m1 R1 and AVB g mB RB
(25)
Journal Pre-proof Where AV1 and AVB are the voltage gains of transistors M1 and MB respectively. We can use (25) and the fact that the gain-bandwidth product of an amplifier is equal to its transit frequency to obtain the upper limit for (gm/ID)1
fT I D1,min R1 BW gm I D 1,max
VGSB I D1
(30)
VDD VGS 1 VGSB I DB
(31)
RS RB
(26)
W
ID ID W
(32)
Where W is the width of the transistor and (ID/W) is the current density of the transistor.
Where BW is the overall bandwidth of the circuit. Equation (15) states that increasing the amount of feedback gmBRB presented by transistor MB, the input impedance will be reduced and the bandwidth will increase. But a large increase in the amount of feedback (gmBRB) will cause unwanted peaking in the frequency response. gmBRB must be lower than a certain threshold F to avoid that frequency overshot [2], [3], thus it is possible to derive a lower limit for (gm/ID)B:
g g mB RB F fT F BW m I D B ,min
(27)
From (18) it is shown that the gain of the circuit can be approximated by the value of the resistor R1 under the condition that gm1RS(1+gmBRB)>>1, use 10 as a rule of thumb, this condition can be used to derive the lower limit of the (gm/ID)1 value. This is done by multiplying and dividing the left-hand side by ID1 and noting that ID1RS = VGSB and the limitation on the value of gmBRB not exceeding F,
g g m1 RS ( g mB RB 1) 10 ( F 1) m ( I D1 RS ) 10 I D 1 g 10 m I D 1,min ( F 1)VGSB
(28)
Using (25), we can assume that the transit frequency of transistor MB must be equal to its gain times the bandwidth. Then multiplying and dividing by the IDB while using the fact that the voltage drop on the resistor RB is equal to (VDD – VGS1 - VGSB), we can provide an upper limit on the (gm/ID)B value.
g fT g mB RB BW fT m ( I DB RB ) BW I D B g fT m I D B ,max (VDD VGS 1 VGSB ) BW
(29)
As mentioned before, all other circuit parameters (resistor values and width of the transistors) are related to the gm/ID value of the transistor and by selecting the appropriate value for the drain currents and hence the transconductance, it is possible to determine the remaining parameters accordingly. So, these equations are presented as follows:
Fig. 7. A flowchart explaining our algorithm
(B) The Framework Algorithm: Using the equations presented in section IV, we can implement an algorithm to find the proper solution. A MATLAB function was written with the required specifications as an input and returns the corresponding circuit parameters achieving them as an output. The
Journal Pre-proof proposed algorithm is shown as a flowchart in Fig. 7 and can be explained by the following steps: 1)
Set the value of the transimpedance gain to R1, as stated in (19), and define the limits of the drain currents of transistors M1 and MB (22), (23), and (24) 2) Set maximum and minimum values of (gm/ID) for both transistors using (26) to (29). Define the design space by values which meet the condition presented by (2). 3) Search the design space by sweeping different values of ID1 and IDB at each pair of (gm/ID) of both transistors. (a) If the optimization criteria are to minimize the power dissipation then sweep the drain currents from minimum to maximum values. (b) If the criteria were to minimize the total input referred noise then sweep IDB descending from maximum to minimum. 4) Calculate the remaining circuit parameters for each iteration using equations (30) to (32) and evaluate the circuit performances (bandwidth, gain, and noise) to verify whether it is viable. 5) It is noted that the voltage swing and power dissipation do not need to be checked at each iteration since they were considered in defining the limits of the drain currents. 6) Once a solution that meets the specifications is found the corresponding parameters to this solution are returned as an output. V.
Specification
First Design (Minimum Power)
Second Design (Minimum Noise)
Gain (dBΩ)
59.885
59.889
Bandwidth (GHz)
6.9
6.958
DC Power (µW)
872.965
997.235
Integrated Noise (nArms)
806.258
771.304
Input Referred noise (pA/√Hz)
7.925
7.55
Fig. 8. Simulated Frequency Response of the first design minimizing the power.
SIMULATION RESULTS AND COMPARISONS
The proposed framework is implemented in MATLAB and the resulting designs were verified by CADENCE simulations. The RGC topology was implemented on a 130 nm CMOS technology. The targeted circuit specifications were similar to those presented in [7]. The gain was set to 60 dBΩ, the desired bandwidth was 7 GHz, the total DC power dissipation was set to less than 1 mW, the allowable output voltage swing was set to 0.6 VP-P, the photodiode capacitance was 200 fF and the load capacitance was 20 fF, and the targeted overall input integrated noise to be less than 1.5 µVrms or 14.639 pA/√Hz. Two designs presented using the proposed methodology each of them met the required specifications while one was optimized to reduce the power dissipation and the other minimizes the integrated input referred noise current. The resulting calculated circuit parameters using MATLAB are presented in Table I. Simulations results and achieved circuit specifications verified by CADENCE Spectre simulations of both designs are present in Table II. The simulated frequency responses are shown in Fig. 8 and Fig. 9, Monte-Carlo simulations of the gain, bandwidth, power consumption and noise of the minimum power design are shown in Fig. 10. The simulated total harmonic distortion (THD) vs. input current is presented in Fig. 11 and the circuit step response for a 10 µA input in Fig. 12. The simulated eye diagram with a 10 µA 10 Gb/s 215-1 PRBS is shown in Fig. 13. TABLE I CALCULATED PARAMETERS OF THE RGC TOPOLOGY USING MATLAB First Design (Power Second Design (Noise) Dissipation) Parameter M1 MB M1 MB gm (mS) 3.194 4.386 3.356 5.4202 ID (µA) 291.99 289.987 306.666 358.158 gm/ID (V-1) 10.9396 15.1234 10.9436 15.1338 W (µm) 7.08 15.77 7.435 19.52 L (nm) 130 130 130 130 R1 (kΩ) 1 1 RB (kΩ) 1.77 1.432 RS (kΩ) 1.534 1.46 TABLE II SPECIFICATIONS OF THE RESULTING DESIGNS
Fig. 9. Simulated Frequency Response of the second design minimizing the input referred noise.
Fig. 10. Monte-Carlo simulation of the minimum power design
Fig. 11. Simulated input current Vs. THD%.
Journal Pre-proof
Fig. 12. Step response of minimum power design for a 10 µA step input.
Fig. 13. Eye diagram with a 10 µA 10 Gb/s 215-1 PRBS.
TABLE III PERFORMANCE COMPARISON WITH OTHER WORKS Input Supply Power referred CPD voltage Architecture (mW) noise (fF) (V) (pA/√Hz) RGC W/ 2.94 510 300 1.05 active feedback Shunt 51.8 feedback w/ 45.7 50 1.5 (sim.) inductive peaking Transformer 28.2 21.3 220 2.5 based RGC Inverter w/ transformer3 16 250 1.2 based feedback
Ref.
Year
Gain (dBΩ)
Bandwidth (GHz)
[25]*
2018
54
9.39
[26]*
2009
50
29
[8]*
2012
59
26
[27]*
2018
42
24
[7]
2017
60
7.28
1
12.2
200
1.5
RGC
1
2019
59.885
6.9
0.873
7.925
200
1.5
RGC
2
2019
59.889
6.958
0.997
7.55
200
1.5
RGC
This work
Technology
fT (GHz)
FoM
32 nm CMOS
-
0.94
130 nm CMOS
85
0.194
250 nm SiGe CMOS
137
8.487
65 nm CMOS
-
15.737
-
119.344
85
196.841
85
182.525
130 nm SiGe BiCMOS 130 nm CMOS 130 nm CMOS
* Results were obtained experimentally.
It is clear from the simulation’s results that both of our designs achieved the specifications used as an input for the proposed algorithm. Investigating Table II, we conclude that the first design achieved a boost in the power performance of 16.56% while the second design presented a better noise performance of 20.31%. It is worth mentioning that the highest relative error in bandwidth is 1.8% and 1.315% for the gain. Moreover, looking at Fig. 10 showing the MonteCarlo simulations of the minimum power design the circuit achieved a standard deviation of 24.9 µW (2.85%) in power consumption, 143.15 MHz (2.08%) in bandwidth, 838.98 mΩ (0.09%) in gain, and 16.25 nArms (1.92%) in the integrated input referred noise. From Fig. 11 the same design achieved a THD < 0.1% for input sinusoidal photocurrents up to 52 µAp-p and less than 1% for input photocurrents below 280 µAp-p. Examining the step response in Fig. 12 a rise time of 52.45 ps, a settling time of 0.15 ns for 1% range of the final value and 0.23 ns for 5%, and percentage overshoot of 12.76% were realized for a 10 µA step input. The resulting eye-opening achieved by the design in Fig. 13 is 93.34 mV vertically and 96.923 ps horizontally. Table III illustrates the performance comparison between the results obtained from our final designs and the works presented in the literature. It is found that our design has an improved performance in power and noise which is expected as they were the main optimized specifications of our work. A figure of merit (FoM) is defined to provide an understandable comparison between the proposed designs and other works.
FoM
BW (GHz ) Gain() CPD ( pF ) PDC (mW ) I n ,in ,ref ( pA / Hz )
(33)
Where FoM is the figure of merit, Iin,n,ref is the input referred noise. Investigating Table III, we can see that our work achieved the highest FoM, this result can be understood in the scope of two reasons. The first reason is related to the usage of the RGC circuit and its ability to compensate for the undesirable effects presented by the large photodiode capacitance, as a result, it can achieve wide bandwidth, low power consumption, and noise performance while obtaining high gain. The second reason is related to our framework utilizing the gm/ID methodology which obtains accurate results for the circuit parameters leading to the required specifications thus utilized in our framework along with equations derived from circuit analysis calculations for limiting the design space and setting the criteria for reaching the optimum design. The framework’s restrictions allow reaching a design meeting all the specifications required as these restrictions govern all the output specifications of the design which may be challenging to achieve without iterations otherwise. Additionally, another remark that can be noted regarding the higher FoM reached by our designs especially in contrast with [7] is the fact that our framework takes the noise performance as one of the concerning specifications this can be
Journal Pre-proof observed as our designs achieved the lowest input referred noise value. Moreover, our methodology utilizes criteria in locating the optimum design rather than calculating all the viable solutions in [7] and then locating the optimum one among them which in general leads to less time and computational power for our algorithm to find the optimum solution. VI.
CONCLUSION
This work presents a systematic framework for designing a RGC transimpedance amplifier for optical receivers. The proposed framework uses the gm/ID methodology for avoiding the inaccuracy of closed-form equations driven from the conventional square-law method. Our methodology depends on using equations to define the design space and the criteria used to reach the optimum design. The calculations are derived from the basic circuit analysis which can be generalized to analyze other topologies. The algorithm utilizing this framework was implemented in MATLAB, two designs were obtained using a 130 nm CMOS technology using a supply voltage of 1.5 V and with a photodiode capacitance of 200 fF. Each of the two designs had a different performance parameter (DC power consumption and input referred noise) as its optimizations criteria. Both designs achieved the required specifications of 7 GHz bandwidth and 60 dBΩ with a relative error of less than 2% while achieving a power consumption of less than 1 mW and input referred noise of less than 8 pA/√Hz. The obtained results were verified by simulations and are shown to be superior to other works according to our figure of merit. This justifies the handy analysis needed to be done to derive the restriction on the design space and optimization criteria of our methodology. Since, they enable us to provide a final design which optimizes more than one specification while meeting all other specifications provided as input to the algorithm in contrast with other works which may only optimize one specification. This proves the presented framework to be successful and can be implemented to design RGC amplifiers on other CMOS technologies. Finally, our design space and the generic restrictions are mainly derived from equations and constraints like the power dissipation and the GBW which can be extended to other topologies along with basic circuit analysis which is fundamental to understanding any topology. REFERENCES [1]B. Razavi, Design of integrated circuits for optical communications, 2nd ed., John Wiley & Sons, 2012. [2]S. M. Park and H.-J. Yoo, “1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 112–121, 2004. [3]C. Talarico, G. D’Amato, G. Avitabile, G. Piccinni, and G. Coviello, “A Systematic Design Approach for Nanoscale Inductor-less Regulated Cascode Stages,” Proceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains, Piscataway, NJ, USA, 2017, pp. 21:1– 21:5. [4]Sung Min Park and C. Toumazou, “A Packaged Low-noise High-speed Regulated Cascode Transimpedance Amplifier Using a 0.6 µm N-well CMOS Technology,” Proceedings of the 26th European Solid-State Circuits Conference, 2000, pp. 431–434. [5]J. Lee, S.-J. Song, S. M. Park, C.-M. Nam, Y.-S. Kwon, and H.-J. Yoo, “A multichip on oxide of 1 Gb/s 80 dB Fully-differential CMOS Transimpedance Amplifier for Optical Interconnect Applications,” 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No. 02CH37315), 2002, vol. 1, pp. 80–447. [6]L. B. Oliveira, C. M. Leitão, and M. M. Silva, “Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 9, pp. 1841–1848, 2012. [7]G. Piccinni, G. Avitabile, G. Coviello, and C. Talarico, “A Novel Design Optimization Framework for Regulated Cascode Transimpedance Amplifiers,”, 2017 European Conference on Circuit Theory and Design (ECCTD), 2017, pp. 1–4.
[8]C. Li and S. Palermo, “A Low-power 26-GHz Transformer-based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier,” IEEE Journal of SolidState Circuits, vol. 48, no. 5, pp. 1264–1275, 2013. [9]S. B. Amid, C. Plett, and P. Schvan, “Fully differential, 40 Gb/s Regulated Cascode Transimpedance Amplifier in 0.13 μm SiGe BiCMOS Technology,” 2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010, pp. 33–36. [10] C. Kromer, G. Sialm, T. Morf, M. Schmatz, F. Ellinger, D. Erni, and H. Jackel, “A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 6, pp. 885– 894, 2004. [11] Y.-H. Kim, E.-S. Jung, and S.-S. Lee, “Bandwidth Enhancement Technique for CMOS RGC Transimpedance Amplifier,” Electronics Letters, vol. 50, no. 12, pp. 882–884, 2014. [12] J. Ou and P. M. Ferreira, “A gm/ID-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier,” IEEE Trans. Circuits Syst. II, vol. 61, no. 10, pp. 783–787, Oct. 2014. [13] J. Ou, P. M. Ferreira, and J.-C. Lee, “Experimental Demonstration of Gm/Id Based Noise Analysis,” Circuits and Systems, vol. 5, no. 04, p. 69, 2014. [14] J. Ou, “Gm/ID Based Noise Analysis for CMOS Analog Circuits,” 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea (South), 2011, pp. 1–4. [15] M. Manghisoni, L. Ratti, V. Re, V. Speziali, and G. Traversi, “Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Frontend Electronics,” 2006 IEEE Nuclear Science Symposium Conference Record, San Diego, CA, USA, 2006, pp. 214–218. [16] M. Akbari, M. Shokouhifar, O. Hashemipour, A. Jalali, and A. Hassanzadeh, “Systematic Design of Analog Integrated Circuits Using Ant Colony Algorithm Based on Noise Optimization,” Analog Integrated Circuits and Signal Processing, vol. 86, no. 2, pp. 327–339, 2016. [17] M. Akbari and O. Hashemipour, “Design and Analysis of Folded Cascode OTAs Using Gm/Id Methodology Based on Flicker Noise Reduction,” Analog Integrated Circuits and Signal Processing, vol. 83, no. 3, pp. 343–352, Jun. 2015. [18] A. Shameli and P. Heydari, “A Novel Power Optimization Technique for Ultra-low Power RFICs,” Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED ’06, Tegernsee, Bavaria, Germany, 2006, p. 274. [19] A. Shameli and P. Heydari, “A Novel Ultra-Low Power (ULP) Low Noise Amplifier using Differential Inductor Feedback,” 2006 Proceedings of the 32nd European Solid-State Circuits Conference, Montreux, 2006, pp. 352– 355. [20] A. Girardi and S. Bampi, “Power Constrained Design Optimization of Analog Circuits Based on Physical gm/ID Characteristics,” Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design - SBCCI ’06, Ouro Preto, MG, Brazil, 2006, p. 89. [21] S. Goswami, J. Silver, T. Copani, W. Chen, H. Barnaby, B. Vermeire, and S. Kiaei, “A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects,” 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009. [22] N. B. Kamarudin and J. Karim, “Design and simulation single stage CMOS TIA for 1.4 GHz, -27 dB MEMS SAW Resonator,” in 2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), Batu Ferringhi, Penang, Malaysia, 2017, pp. 163–166. [23] SapWin, site: “http://cirlab.det.unifi.it/SapWin4”. [24] MATLAB, site: “https://www.mathworks.com/products/matlab”. [25] J. A. Hora, D. L. Piandong, P. E. G. Empas, O. J. L. Gerasta, X. Zhu, and E. Dutkiewicz, “A CMOS Implemented Transimpedance Amplifier Design for Optical Communications,” 2018 IEEE 10th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM), 2018, pp. 1–6. [26] J. Kim and J. F. Buckwalter, “Bandwidth Enhancement with Low Groupdelay Variation for a 40-Gb/s Transimpedance Amplifier,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 1964–1972, 2010. [27] Q. Pan, Y. Wang, and C. P. Yue, “A 42-dBΩ 25-Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2019.
Journal Pre-proof
Conflict of Interest and Authorship Conformation Form Please check the following as appropriate:
All authors have participated in (a) conception and design, or analysis and interpretation of the data; (b) drafting the article or revising it critically for important intellectual content; and (c) approval of the final version.
This manuscript has not been submitted to, nor is under review at, another journal or other publishing venue.
The authors have no affiliation with any organization with a direct or indirect financial interest in the subject matter discussed in the manuscript
o The following authors have affiliations with organizations with direct or indirect financial interest in the subject matter discussed in the manuscript: Author’s name
Affiliation
Motaz M. Elbadry, Mostafa Y. Makkey, Mohamed Abdelgawad, Mohamed Atef PII:
S0026-2692(19)30609-3
DOI:
https://doi.org/10.1016/j.mejo.2019.104676
Reference:
MEJ 104676
To appear in:
Microelectronics Journal
Received Date:
21 July 2019
Accepted Date:
03 December 2019
Please cite this article as: Motaz M. Elbadry, Mostafa Y. Makkey, Mohamed Abdelgawad, Mohamed Atef, Design Technique for Regulated Cascode Transimpedance Amplifier Using Gm/ID Methodology, Microelectronics Journal (2019), https://doi.org/10.1016/j.mejo.2019.104676
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain. © 2019 Published by Elsevier.
Journal Pre-proof
Design Technique for Regulated Cascode Transimpedance Amplifier Using Gm/ID Methodology Motaz M. Elbadry, Mostafa Y. Makkey, and Mohamed Abdelgawad, Mohamed Atef, Senior, IEEE
Abstract—This paper presents an approach using gm/ID methodology for the design of the regulated cascode circuit (RGC) transimpedance amplifier (TIA) for optical receivers. The framework uses lookup tables produced using the gm/ID methodology to define the sizing of the transistors needed to reach the required specifications. The framework has the advantage of setting limits on the design space using intuitive equations derived from the circuit analyses. This gives insight into the effect of changing the value of different circuit parameters on the resulting design while decreasing the time to reach the desired design. The framework gives the flexibility to minimize the DC power consumption or the total input referred noise. The framework is implemented in a 130 nm CMOS process with a 1.5 V supply voltage producing two different designs. Both designs met the required specifications while optimizing power consumption or noise and were validated using simulations. The results obtained are discussed and compared against other designs from the state-of-the-art.
Index Terms— Transimpedance Amplifier, Optical Receivers, Regulated Cascode, gm/ID methodology.
I. INTRODUCTION The design of transimpedance amplifiers (TIA) as a preamplifier for optical receivers proposes many challenges because of the trade-offs introduced between noise, bandwidth, gain, and power dissipation [1]. Interfacing the large photodiode capacitance is the main concern having the worst effect on bandwidth and noise performance of the circuit. Therefore, it is critical to develop topologies that can relax the input parasitic effects [2]. From the different topologies, the regulated cascode (RGC) circuit is considered for having the advantage of using local feedback to reduce the input resistance seen by the large photodiode capacitance [3]. The RGC topology is one of the widely used and commonly known in the literature, it has been introduced as a front-end amplifier for optical receivers in [2], [4] and [5] due to its numerous merits of wide bandwidth, high gain, and low noise contribution. It was shown to have superior noise performance to other topologies in [6]. Additionally, it was implemented in various technologies including BiCMOS in[7]– [9]. Methods of inductive peaking were used with the topology to further increase its bandwidth [8]–[11] while also being designed in a differential configuration in [5], [9] and low power operation in [3], [7]. Our work uses the gm/Id methodology for designing the RGC circuit. The gm/ID methodology has the advantage of using the generated lookup tables for determining the accurate sizing of transistors to achieve the required specifications. These tables are generated by extracting the different performance parameters of the This paper was submitted on for review on XXXX. Motaz M. Elbadry, Mostafa Y. Makkey, Mohamed Abdelgawad and Mohamed Atef are with the Electrical Engineering Department, Assiut University, Assiut, Egypt. ([email protected], [email protected], [email protected], [email protected]).
transistor (i.e. transit frequency (fT), intrinsic gain (gm/gds), current density (ID/W), and the intrinsic capacitances (Cgs, Cgd) ) as a function of the inversion level (gm/ID). The tables have the advantage of avoiding multiple iterations on simulation programs to find the optimum point for the required design. The gm/ID methodology has been used numerous times in the literature to optimize the noise performance of the analog circuits [12]–[17], minimize power consumption [7], [18]–[20], and to design different TIA topologies for optical receivers [3], [7], [21], [22]. The presented framework uses the lookup tables for the used technology along with closed-form DC signal analysis, noise analysis, and small-signal analysis equations generated either by hand calculations or a computer-aided design program [23]. The resulting equations are used to set the limits on the design space searched for the optimum design. A MATLAB [24] function is written using this framework takes the design specification as inputs (i.e. gain, bandwidth, power dissipation, output voltage swing, photodiode capacitance, output capacitance, and input referred noise) and outputs the circuit parameters achieving these specifications. The output design from the function can favor the optimum design in terms of power dissipation or the input referred noise. The approach is utilized in designing the RGC circuit having the same specifications as [7]. The circuits are implemented in a 130 nm CMOS process with 1.5V supply. The gm/ID methodology and procedure for generating the lookup tables are reviewed in Section II. Section III presents the RGC topology and the equation derived from its analyses used in our framework. Our proposed framework and optimization algorithm along with the method used for defining our design space and optimization technique for the dissipated power and noise performance of the circuit are discussed in Section IV. Section V shows the produced designs from using our work and the results obtained from the simulations and discusses the accuracy of the presented framework. also, the final designs are compared with other works of different topologies in the literature employing the same technology. Finally, we present our main conclusion in Section VI. II. GM/ID METHODOLOGY Sizing transistors in small channel MOSFET has become one of the main design problems in recent years due to the inaccuracy of the square-law model to describe the parameters of the transistors. Hence, this has often led the designers to rely upon multiple iterations to reach the optimum design. Consequently, increasing the difficulty of the design and as a result, the designers lose the intuitive understanding of the effect of different circuit parameters on the final specifications. The limitations associated with the square-law model are mainly due to its inability to account for second-order effects (i.e. channel length modulation and drain induced barrier lowering). These second-order effects become more important as the transistor length decreases reaching the nanoscale size. Therefore, the use of a different methodology becomes necessary. The gm/ID methodology depends on generated lookup tables describing different parameters (i.e. transit frequency, fT, intrinsic
Journal Pre-proof gain, gm/gds, current density, ID/W, and the intrinsic capacitances of the transistor) as a function of the inversion level described by the transconductance efficiency (i.e. gm/ID). In contrast with closed-form equations of the square-law model, the charts are generated from the spice model of the technology provided by the silicon foundry which closely captures the second-order effects. Since the main issue is not the analysis equations that describe the circuit, but the model used to link between the sizing of the transistors and its parameters represented in the circuit.
the transistor has higher transconductance (gm) and higher intrinsic (channel) resistance leading to higher gain. At the same time investigating Fig. 4 this leads to lower current density (ID/W) which requires wider transistor to obtain a certain drain current (ID) value leading to higher capacitance and lower speed.
Fig. 3. Transit frequency (fT) and intrinsic gain (gm/gds) as a function of gm/ID at different inversion levels.
Fig. 1. The test bench used to generate the lookup tables by DC sweeping VDS, VGS, and MOSFET length L for gm/Id methodology.
The lookup tables are produced once by sweeping the intrinsic gain cell in Fig. 1 along three dimensions (i.e. VDS, VGS, and L) and tabulating all the device parameters. We can include the device width (W) as a fourth dimension but this can be neglected since the parameters scale linearly with it. The gm/ID values as a function of overdrive voltage (Vov) typically range between 3 to 30 S/A as illustrated by Fig. 2. The higher gm/ID values represent weak inversion, the midrange values represent moderate inversion typically around 12 to 20 S/A, and the lower values represent strong inversion.
Fig. 2. The transconductance efficiency (gm/ID) as a function of overdrive voltage (Vov) at different levels of inversion at VDS=0.6 V and W=1 m.
Investigating the charts present in Fig. 3 we can see the tradeoff presented by the value of gm/ID and the resulting transit frequency (fT) and intrinsic gain (gm/gds) of the transistors. The last generated chart is the current density (ID/W) as a function of gm/ID at different inversion levels shown in Fig. 4. Fig. 2, Fig. 3 and Fig. 4 indicate that biasing the transistors at weak inversion exhibit low power consumption, higher gain, and voltage swing but at lower speed and large size. The opposite occurs when biased at strong inversion the transistor has higher speed, smaller size, decreased voltage swing, and lower gain. This can be understood by the fact that at higher gm/ID values corresponding to weak inversion,
Fig. 4. The current density (ID/W) as a function of gm/ID at different inversion levels
III. MODELING OF REGULATED CASCODE CIRCUIT The RGC topology is a well-known circuit as the first stage of the optical receiver where the photocurrent detected by the photodiode is amplified and converted to a voltage signal at the output. The low input impedance of the RGC topology due to the local feedback gives it many advantages over other topologies in terms of higher bandwidth achieved at lower power [2]. It can be seen from the circuit diagram of the RGC in Fig. 5 that the topology has two transistors M1 and MB. Transistor M1 acts as the main amplifier. The photocurrent signal at the source is amplified to a voltage signal at the drain. MB is used to provide negative feedback to reduce the input impedance and improve the bandwidth. A) DC Analysis: By investigating the DC analysis of the RGC circuit shown in Fig. 5, it is evident that the power dissipation is equal to the power supply voltage multiplied by the drain currents of transistors M1 and MB.
Pdiss VDD ( I D1 I DB )
(1)
Also, the drain to source voltage of MB is equal to the gate to source voltage of both transistors.
VDSB VGS 1 VGSB
(2)
Journal Pre-proof C XZ Cgs1 CgdB
(6)
Where Cgs1 is the parasitic capacitance from the gate to the source of transistor M1, and CgdB is the parasitic capacitance from the gate to the drain of transistor MB.
C XY Cdb1
(7)
Where Cdb1 is the parasitic capacitance from the drain to the bulk of transistor M1.
CYZ C gd 1
(8)
Where Cgd1 is the parasitic capacitance between the gate and the drain of transistor M1. The transfer function of the RGC circuit is obtained by the help of the symbolic analysis on the computer-aided design software SapWin [23]. The transfer function has two zeros and three poles in which two are complex conjugate poles and one simple pole. The two zeros are represented by:
N ( s ) as 2 bs c Fig. 5. The RGC circuit schematic diagram.
and z1,2
b b 2 4ac 2a
(9)
Where N(s) is the representation of the zeros in the Laplace domain while a, b, and c are coefficients of the second-order polynomial. The coefficients of the polynomial can be approximated by:
a C XZ C XY CYZ C XZ CYZ C XY CZ C XY RB , b C XY CYZ ( g m1 g mB ) g m1CZ RB ,
(10)
and c g m1 1 g mB RB Fig. 6. The RGC small-signal model.
B) AC analysis: The RGC small-signal model in Fig. 6 contains five parasitic capacitances CX, CY, CZ, CXZ, and CYZ between different nodes as explained in [3]. These capacitances are as follows:
C X CPD C gsB
(4)
Where CL is the capacitance of the load at the output of the circuit.
CZ CdbB
z1,2
c a
(3)
Where CPD is the capacitance of the photodiode and CgsB is the parasitic capacitance between the gate and source of transistor MB.
CY CL
Examining the values of the coefficients it is deduced that the two zeros are complex conjugate and by using the fact that b2<<4ac then the magnitude of the zeros can be approximated by:
(5)
Where CdbB is the parasitic capacitance from the drain to the bulk of transistor MB.
z1,2
g m1 1 g mB RB
(11)
C XZ C XY CYZ C XZ CYZ C XY CZ C XY RB
Comparing the value presented by (11) with the transit frequency given by fT = gm/Cgg; where Cgg is the total gate capacitance of the transistor; we deduce that this value is higher than the transit frequency. Thus, it is shown that the values of the zeros occur at a much higher frequency than the poles so that they can be neglected, and the transfer function can be approximated by:
A( s )
A0 s
s2
s (1 )(1 2 ) p1 0 0Q
(12)
Journal Pre-proof IV. THE PROPOSED DESIGN FRAMEWORK The two poles of the transfer function are:
p1 p1 p2,3
0 2Q
(1 1 4Q 2 )
(13) (14)
The simple pole is dependent on the time constant at the input and output of the circuit at nodes X and Y [3], [6]. these time constants can be written as:
τ X C X RX and τY CY RY
(15)
Where RX and RY are the resistances seen respectively at the input and output:
RX R S
1 g m1 (1 g mB RB )
(16)
and
RY R1
(17)
The midband gain A0 in (12) is equal to:
A0 R1
g m1 RS (1 g mB RB ) g m1 RS (1 g mB RB ) 1
(18)
The purpose of our framework is to use the lookup tables generated by the gm/ID methodology to determine the proper sizing of the transistors achieving the required specifications of the final design. However, the difficulty arises from the fact that our design space needs to be limited in order to decrease the processing time and efforts needed to find the appropriate circuit parameters. The equations obtained from the different types of circuit analyses presented in the previous section III can be manipulated to achieve these specifications. Finally, an algorithm can be implemented using a proper programming tool; which is MATLAB in our case; utilizing this framework to search the reduced design space for valid solutions. Keeping in mind the fact that more than one solution could be found for the given specifications, certain criteria are applied to reach an optimum design with respect to two different parameters either the DC power dissipation of the circuit or its noise performance. First, we need to define the constraints that are applied to our design space limiting the amount of search needed to pinpoint the required design. Intuitively, these constraints are set on the different sweeping parameters defining our design space. The merit of using the gm/ID lookup tables is that we only need to choose the value of gm/ID for both transistors in the circuit and by picking the right value of drain current (ID) for each transistor we can check whether this design meets the specification. This is a result of the fact that all circuits’ parameters are related to the gm/ID value and its sweeping parameters. Accordingly, the constraints are needed to only define two different variables which are: the transconductance efficiency (gm/ID) and the drain current (ID) of the two transistors. (A) The Framework Equations: Inspecting the DC analysis of the RGC circuit, the minimum value for the drain current of transistor M1 is directly related to the required output voltage swing:
I D1,min
if gm1RS(1+gmBRB) >> 1 the midband gain can be approximated by:
A0 R1
(19)
C) Noise Analysis: Examining the noise analysis of the RGC topology, it is noted that the noise generated by the transistor MB is dominant and has the highest contribution to the total input referred noise of the circuit [6]. The input referred noise current spectral density of the circuit due to MB can be given by:
I n ,in 2
RS CPD 12 4 KT g mB B 2 g mB RS
(20)
Where K is the Boltzmann’s constant, T is the absolute temperature, and ϒ is the noise factor of the transistor. After integrating this equation, we can get the total root mean squared (rms) input referred noise current given by:
I n,in,rms 4 KT
b 4 2 Bn3CPD 2 4 Bn 2CPD Bn 2 g mB 3 2 RS RS
Where BN is the equivalent noise bandwidth.
(21).
output voltage swing 2 R1
(22)
Also, the maximum limit for the drain currents of the transistors is set by the power consumption of the circuit
I D1,max I DB ,max
PDC VDD
(23)
Where PDC is the total DC power consumption and VDD is the DC supply voltage. Finally, to find the lower limit for the drain current of transistor MB, we use (21) and multiplying both sides by IDB
I DB ,min
4 KT I n,in,rms 2
B 4 2 Bn3CPD 2 4 Bn2CPD Bn 2 3 2 RS RS gm I D B
(24)
Before deriving the equations defining the limits on the (gm/ID) value of the transistors. It is useful to note that transistors M1 can be viewed as a common gate amplifier, while transistor MB as a common source amplifier thus:
AV 1 g m1 R1 and AVB g mB RB
(25)
Journal Pre-proof Where AV1 and AVB are the voltage gains of transistors M1 and MB respectively. We can use (25) and the fact that the gain-bandwidth product of an amplifier is equal to its transit frequency to obtain the upper limit for (gm/ID)1
fT I D1,min R1 BW gm I D 1,max
VGSB I D1
(30)
VDD VGS 1 VGSB I DB
(31)
RS RB
(26)
W
ID ID W
(32)
Where W is the width of the transistor and (ID/W) is the current density of the transistor.
Where BW is the overall bandwidth of the circuit. Equation (15) states that increasing the amount of feedback gmBRB presented by transistor MB, the input impedance will be reduced and the bandwidth will increase. But a large increase in the amount of feedback (gmBRB) will cause unwanted peaking in the frequency response. gmBRB must be lower than a certain threshold F to avoid that frequency overshot [2], [3], thus it is possible to derive a lower limit for (gm/ID)B:
g g mB RB F fT F BW m I D B ,min
(27)
From (18) it is shown that the gain of the circuit can be approximated by the value of the resistor R1 under the condition that gm1RS(1+gmBRB)>>1, use 10 as a rule of thumb, this condition can be used to derive the lower limit of the (gm/ID)1 value. This is done by multiplying and dividing the left-hand side by ID1 and noting that ID1RS = VGSB and the limitation on the value of gmBRB not exceeding F,
g g m1 RS ( g mB RB 1) 10 ( F 1) m ( I D1 RS ) 10 I D 1 g 10 m I D 1,min ( F 1)VGSB
(28)
Using (25), we can assume that the transit frequency of transistor MB must be equal to its gain times the bandwidth. Then multiplying and dividing by the IDB while using the fact that the voltage drop on the resistor RB is equal to (VDD – VGS1 - VGSB), we can provide an upper limit on the (gm/ID)B value.
g fT g mB RB BW fT m ( I DB RB ) BW I D B g fT m I D B ,max (VDD VGS 1 VGSB ) BW
(29)
As mentioned before, all other circuit parameters (resistor values and width of the transistors) are related to the gm/ID value of the transistor and by selecting the appropriate value for the drain currents and hence the transconductance, it is possible to determine the remaining parameters accordingly. So, these equations are presented as follows:
Fig. 7. A flowchart explaining our algorithm
(B) The Framework Algorithm: Using the equations presented in section IV, we can implement an algorithm to find the proper solution. A MATLAB function was written with the required specifications as an input and returns the corresponding circuit parameters achieving them as an output. The
Journal Pre-proof proposed algorithm is shown as a flowchart in Fig. 7 and can be explained by the following steps: 1)
Set the value of the transimpedance gain to R1, as stated in (19), and define the limits of the drain currents of transistors M1 and MB (22), (23), and (24) 2) Set maximum and minimum values of (gm/ID) for both transistors using (26) to (29). Define the design space by values which meet the condition presented by (2). 3) Search the design space by sweeping different values of ID1 and IDB at each pair of (gm/ID) of both transistors. (a) If the optimization criteria are to minimize the power dissipation then sweep the drain currents from minimum to maximum values. (b) If the criteria were to minimize the total input referred noise then sweep IDB descending from maximum to minimum. 4) Calculate the remaining circuit parameters for each iteration using equations (30) to (32) and evaluate the circuit performances (bandwidth, gain, and noise) to verify whether it is viable. 5) It is noted that the voltage swing and power dissipation do not need to be checked at each iteration since they were considered in defining the limits of the drain currents. 6) Once a solution that meets the specifications is found the corresponding parameters to this solution are returned as an output. V.
Specification
First Design (Minimum Power)
Second Design (Minimum Noise)
Gain (dBΩ)
59.885
59.889
Bandwidth (GHz)
6.9
6.958
DC Power (µW)
872.965
997.235
Integrated Noise (nArms)
806.258
771.304
Input Referred noise (pA/√Hz)
7.925
7.55
Fig. 8. Simulated Frequency Response of the first design minimizing the power.
SIMULATION RESULTS AND COMPARISONS
The proposed framework is implemented in MATLAB and the resulting designs were verified by CADENCE simulations. The RGC topology was implemented on a 130 nm CMOS technology. The targeted circuit specifications were similar to those presented in [7]. The gain was set to 60 dBΩ, the desired bandwidth was 7 GHz, the total DC power dissipation was set to less than 1 mW, the allowable output voltage swing was set to 0.6 VP-P, the photodiode capacitance was 200 fF and the load capacitance was 20 fF, and the targeted overall input integrated noise to be less than 1.5 µVrms or 14.639 pA/√Hz. Two designs presented using the proposed methodology each of them met the required specifications while one was optimized to reduce the power dissipation and the other minimizes the integrated input referred noise current. The resulting calculated circuit parameters using MATLAB are presented in Table I. Simulations results and achieved circuit specifications verified by CADENCE Spectre simulations of both designs are present in Table II. The simulated frequency responses are shown in Fig. 8 and Fig. 9, Monte-Carlo simulations of the gain, bandwidth, power consumption and noise of the minimum power design are shown in Fig. 10. The simulated total harmonic distortion (THD) vs. input current is presented in Fig. 11 and the circuit step response for a 10 µA input in Fig. 12. The simulated eye diagram with a 10 µA 10 Gb/s 215-1 PRBS is shown in Fig. 13. TABLE I CALCULATED PARAMETERS OF THE RGC TOPOLOGY USING MATLAB First Design (Power Second Design (Noise) Dissipation) Parameter M1 MB M1 MB gm (mS) 3.194 4.386 3.356 5.4202 ID (µA) 291.99 289.987 306.666 358.158 gm/ID (V-1) 10.9396 15.1234 10.9436 15.1338 W (µm) 7.08 15.77 7.435 19.52 L (nm) 130 130 130 130 R1 (kΩ) 1 1 RB (kΩ) 1.77 1.432 RS (kΩ) 1.534 1.46 TABLE II SPECIFICATIONS OF THE RESULTING DESIGNS
Fig. 9. Simulated Frequency Response of the second design minimizing the input referred noise.
Fig. 10. Monte-Carlo simulation of the minimum power design
Fig. 11. Simulated input current Vs. THD%.
Journal Pre-proof
Fig. 12. Step response of minimum power design for a 10 µA step input.
Fig. 13. Eye diagram with a 10 µA 10 Gb/s 215-1 PRBS.
TABLE III PERFORMANCE COMPARISON WITH OTHER WORKS Input Supply Power referred CPD voltage Architecture (mW) noise (fF) (V) (pA/√Hz) RGC W/ 2.94 510 300 1.05 active feedback Shunt 51.8 feedback w/ 45.7 50 1.5 (sim.) inductive peaking Transformer 28.2 21.3 220 2.5 based RGC Inverter w/ transformer3 16 250 1.2 based feedback
Ref.
Year
Gain (dBΩ)
Bandwidth (GHz)
[25]*
2018
54
9.39
[26]*
2009
50
29
[8]*
2012
59
26
[27]*
2018
42
24
[7]
2017
60
7.28
1
12.2
200
1.5
RGC
1
2019
59.885
6.9
0.873
7.925
200
1.5
RGC
2
2019
59.889
6.958
0.997
7.55
200
1.5
RGC
This work
Technology
fT (GHz)
FoM
32 nm CMOS
-
0.94
130 nm CMOS
85
0.194
250 nm SiGe CMOS
137
8.487
65 nm CMOS
-
15.737
-
119.344
85
196.841
85
182.525
130 nm SiGe BiCMOS 130 nm CMOS 130 nm CMOS
* Results were obtained experimentally.
It is clear from the simulation’s results that both of our designs achieved the specifications used as an input for the proposed algorithm. Investigating Table II, we conclude that the first design achieved a boost in the power performance of 16.56% while the second design presented a better noise performance of 20.31%. It is worth mentioning that the highest relative error in bandwidth is 1.8% and 1.315% for the gain. Moreover, looking at Fig. 10 showing the MonteCarlo simulations of the minimum power design the circuit achieved a standard deviation of 24.9 µW (2.85%) in power consumption, 143.15 MHz (2.08%) in bandwidth, 838.98 mΩ (0.09%) in gain, and 16.25 nArms (1.92%) in the integrated input referred noise. From Fig. 11 the same design achieved a THD < 0.1% for input sinusoidal photocurrents up to 52 µAp-p and less than 1% for input photocurrents below 280 µAp-p. Examining the step response in Fig. 12 a rise time of 52.45 ps, a settling time of 0.15 ns for 1% range of the final value and 0.23 ns for 5%, and percentage overshoot of 12.76% were realized for a 10 µA step input. The resulting eye-opening achieved by the design in Fig. 13 is 93.34 mV vertically and 96.923 ps horizontally. Table III illustrates the performance comparison between the results obtained from our final designs and the works presented in the literature. It is found that our design has an improved performance in power and noise which is expected as they were the main optimized specifications of our work. A figure of merit (FoM) is defined to provide an understandable comparison between the proposed designs and other works.
FoM
BW (GHz ) Gain() CPD ( pF ) PDC (mW ) I n ,in ,ref ( pA / Hz )
(33)
Where FoM is the figure of merit, Iin,n,ref is the input referred noise. Investigating Table III, we can see that our work achieved the highest FoM, this result can be understood in the scope of two reasons. The first reason is related to the usage of the RGC circuit and its ability to compensate for the undesirable effects presented by the large photodiode capacitance, as a result, it can achieve wide bandwidth, low power consumption, and noise performance while obtaining high gain. The second reason is related to our framework utilizing the gm/ID methodology which obtains accurate results for the circuit parameters leading to the required specifications thus utilized in our framework along with equations derived from circuit analysis calculations for limiting the design space and setting the criteria for reaching the optimum design. The framework’s restrictions allow reaching a design meeting all the specifications required as these restrictions govern all the output specifications of the design which may be challenging to achieve without iterations otherwise. Additionally, another remark that can be noted regarding the higher FoM reached by our designs especially in contrast with [7] is the fact that our framework takes the noise performance as one of the concerning specifications this can be
Journal Pre-proof observed as our designs achieved the lowest input referred noise value. Moreover, our methodology utilizes criteria in locating the optimum design rather than calculating all the viable solutions in [7] and then locating the optimum one among them which in general leads to less time and computational power for our algorithm to find the optimum solution. VI.
CONCLUSION
This work presents a systematic framework for designing a RGC transimpedance amplifier for optical receivers. The proposed framework uses the gm/ID methodology for avoiding the inaccuracy of closed-form equations driven from the conventional square-law method. Our methodology depends on using equations to define the design space and the criteria used to reach the optimum design. The calculations are derived from the basic circuit analysis which can be generalized to analyze other topologies. The algorithm utilizing this framework was implemented in MATLAB, two designs were obtained using a 130 nm CMOS technology using a supply voltage of 1.5 V and with a photodiode capacitance of 200 fF. Each of the two designs had a different performance parameter (DC power consumption and input referred noise) as its optimizations criteria. Both designs achieved the required specifications of 7 GHz bandwidth and 60 dBΩ with a relative error of less than 2% while achieving a power consumption of less than 1 mW and input referred noise of less than 8 pA/√Hz. The obtained results were verified by simulations and are shown to be superior to other works according to our figure of merit. This justifies the handy analysis needed to be done to derive the restriction on the design space and optimization criteria of our methodology. Since, they enable us to provide a final design which optimizes more than one specification while meeting all other specifications provided as input to the algorithm in contrast with other works which may only optimize one specification. This proves the presented framework to be successful and can be implemented to design RGC amplifiers on other CMOS technologies. Finally, our design space and the generic restrictions are mainly derived from equations and constraints like the power dissipation and the GBW which can be extended to other topologies along with basic circuit analysis which is fundamental to understanding any topology. REFERENCES [1]B. Razavi, Design of integrated circuits for optical communications, 2nd ed., John Wiley & Sons, 2012. [2]S. M. Park and H.-J. Yoo, “1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 112–121, 2004. [3]C. Talarico, G. D’Amato, G. Avitabile, G. Piccinni, and G. Coviello, “A Systematic Design Approach for Nanoscale Inductor-less Regulated Cascode Stages,” Proceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains, Piscataway, NJ, USA, 2017, pp. 21:1– 21:5. [4]Sung Min Park and C. Toumazou, “A Packaged Low-noise High-speed Regulated Cascode Transimpedance Amplifier Using a 0.6 µm N-well CMOS Technology,” Proceedings of the 26th European Solid-State Circuits Conference, 2000, pp. 431–434. [5]J. Lee, S.-J. Song, S. M. Park, C.-M. Nam, Y.-S. Kwon, and H.-J. Yoo, “A multichip on oxide of 1 Gb/s 80 dB Fully-differential CMOS Transimpedance Amplifier for Optical Interconnect Applications,” 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No. 02CH37315), 2002, vol. 1, pp. 80–447. [6]L. B. Oliveira, C. M. Leitão, and M. M. Silva, “Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 9, pp. 1841–1848, 2012. [7]G. Piccinni, G. Avitabile, G. Coviello, and C. Talarico, “A Novel Design Optimization Framework for Regulated Cascode Transimpedance Amplifiers,”, 2017 European Conference on Circuit Theory and Design (ECCTD), 2017, pp. 1–4.
[8]C. Li and S. Palermo, “A Low-power 26-GHz Transformer-based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier,” IEEE Journal of SolidState Circuits, vol. 48, no. 5, pp. 1264–1275, 2013. [9]S. B. Amid, C. Plett, and P. Schvan, “Fully differential, 40 Gb/s Regulated Cascode Transimpedance Amplifier in 0.13 μm SiGe BiCMOS Technology,” 2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010, pp. 33–36. [10] C. Kromer, G. Sialm, T. Morf, M. Schmatz, F. Ellinger, D. Erni, and H. Jackel, “A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 6, pp. 885– 894, 2004. [11] Y.-H. Kim, E.-S. Jung, and S.-S. Lee, “Bandwidth Enhancement Technique for CMOS RGC Transimpedance Amplifier,” Electronics Letters, vol. 50, no. 12, pp. 882–884, 2014. [12] J. Ou and P. M. Ferreira, “A gm/ID-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier,” IEEE Trans. Circuits Syst. II, vol. 61, no. 10, pp. 783–787, Oct. 2014. [13] J. Ou, P. M. Ferreira, and J.-C. Lee, “Experimental Demonstration of Gm/Id Based Noise Analysis,” Circuits and Systems, vol. 5, no. 04, p. 69, 2014. [14] J. Ou, “Gm/ID Based Noise Analysis for CMOS Analog Circuits,” 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea (South), 2011, pp. 1–4. [15] M. Manghisoni, L. Ratti, V. Re, V. Speziali, and G. Traversi, “Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Frontend Electronics,” 2006 IEEE Nuclear Science Symposium Conference Record, San Diego, CA, USA, 2006, pp. 214–218. [16] M. Akbari, M. Shokouhifar, O. Hashemipour, A. Jalali, and A. Hassanzadeh, “Systematic Design of Analog Integrated Circuits Using Ant Colony Algorithm Based on Noise Optimization,” Analog Integrated Circuits and Signal Processing, vol. 86, no. 2, pp. 327–339, 2016. [17] M. Akbari and O. Hashemipour, “Design and Analysis of Folded Cascode OTAs Using Gm/Id Methodology Based on Flicker Noise Reduction,” Analog Integrated Circuits and Signal Processing, vol. 83, no. 3, pp. 343–352, Jun. 2015. [18] A. Shameli and P. Heydari, “A Novel Power Optimization Technique for Ultra-low Power RFICs,” Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED ’06, Tegernsee, Bavaria, Germany, 2006, p. 274. [19] A. Shameli and P. Heydari, “A Novel Ultra-Low Power (ULP) Low Noise Amplifier using Differential Inductor Feedback,” 2006 Proceedings of the 32nd European Solid-State Circuits Conference, Montreux, 2006, pp. 352– 355. [20] A. Girardi and S. Bampi, “Power Constrained Design Optimization of Analog Circuits Based on Physical gm/ID Characteristics,” Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design - SBCCI ’06, Ouro Preto, MG, Brazil, 2006, p. 89. [21] S. Goswami, J. Silver, T. Copani, W. Chen, H. Barnaby, B. Vermeire, and S. Kiaei, “A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects,” 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009. [22] N. B. Kamarudin and J. Karim, “Design and simulation single stage CMOS TIA for 1.4 GHz, -27 dB MEMS SAW Resonator,” in 2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), Batu Ferringhi, Penang, Malaysia, 2017, pp. 163–166. [23] SapWin, site: “http://cirlab.det.unifi.it/SapWin4”. [24] MATLAB, site: “https://www.mathworks.com/products/matlab”. [25] J. A. Hora, D. L. Piandong, P. E. G. Empas, O. J. L. Gerasta, X. Zhu, and E. Dutkiewicz, “A CMOS Implemented Transimpedance Amplifier Design for Optical Communications,” 2018 IEEE 10th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM), 2018, pp. 1–6. [26] J. Kim and J. F. Buckwalter, “Bandwidth Enhancement with Low Groupdelay Variation for a 40-Gb/s Transimpedance Amplifier,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 1964–1972, 2010. [27] Q. Pan, Y. Wang, and C. P. Yue, “A 42-dBΩ 25-Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2019.
Journal Pre-proof
Conflict of Interest and Authorship Conformation Form Please check the following as appropriate:
All authors have participated in (a) conception and design, or analysis and interpretation of the data; (b) drafting the article or revising it critically for important intellectual content; and (c) approval of the final version.
This manuscript has not been submitted to, nor is under review at, another journal or other publishing venue.
The authors have no affiliation with any organization with a direct or indirect financial interest in the subject matter discussed in the manuscript
o The following authors have affiliations with organizations with direct or indirect financial interest in the subject matter discussed in the manuscript: Author’s name
Affiliation