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Development of a detector-compatible JFET technology on high-resistivity silicon
Nuclear Instruments and Methods in Physics Research A 409 (1998) 346—350
Development of a detector-compatible JFET technology on high-resistivity silicon G.F. Dalla Betta!,",*, M. Boscardin", G.U. Pignatel!, G. Verzellesi!, L. Bosisio#, L. Ferrario", M. Zen", G. Soncini!," ! Dipartimento di Ingegneria dei Materiali, Universita% di Trento, I-38050 Mesiano (TN), Italy " IRST, Divisione Microsensori ed Integrazione di Sistema, I-38050 Povo (TN), Italy # Dipartimento di Fisica and INFN-Sezione di Trieste, Via A. Valerio 2, I-34127, Trieste, Italy
Abstract We report on the development of a radiation-detector compatible JFET technology on high-resistivity silicon for monolithic integration of detectors and front-end electronics. A dedicated test-chip has been designed and fabricated for process and device characterization. Results from the electrical characterization of a first fabrication run show that good values of detector leakage current (+1 nA/cm2) can be obtained in spite of the relatively high thermal budget characterizing the process. As far as the JFET performance is concerned, a problem of insufficient device isolation at high substrate voltages has been evidenced. A second run is currently being carried on with the aim of optimizing the JFET structure. ( 1998 Elsevier Science B.V. All rights reserved.
1. Introduction Thanks to their low-noise figures and high radiation hardness, Junction Field Effect Transistors (JFETs) are widely used as active components in the front-end electronics of silicon radiation detectors [1]. Monolithic integration of the preamplification stage on the detector chip can give further advantages in terms of performance enhancement as well as system assembly simplification [2]. A key requirement, however, is that the additional process steps necessary for the JFET fabrication do not degrade significantly the detector leakage current. This task can be accomplished either by min* Correspondence address: Dipartimento di Ingegneria dei Materiali, Universita` di Trento, I-38050 Mesiano (TN), Italy.
imizing the number of high-temperature thermal cycles [3], or, alternatively, by making use of extrinsic-gettering techniques [4,5]. This work is devoted to the definition of a JFET technology on high-resistivity silicon for the fabrication of fully depleted, PIN radiation detectors with on-chip, JFET-based preamplifiers. The JFET structure and doping profile has been defined and optimized by means of 2D numerical process/device simulations [6]. In this paper, we report on the electrical characterization of a dedicated test chip containing JFETs, PIN diodes, and other test structures (including Van der Pauw resistors, gated diodes, as well as MOS capacitors and transistors), which has been designed and fabricated to allow for the characterization of the proposed JFET technology.
0168-9002/98/$19.00 ( 1998 Elsevier Science B.V. All rights reserved PII S 0 1 6 8 - 9 0 0 2 ( 9 7 ) 0 1 2 9 6 - 5
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G.F. Dalla Betta et al./Nucl. Instr. and Meth. in Phys. Res. A 409 (1998) 346—350
2. Fabrication technology The technological approach adopted features (i) triple ion implantation and thermal diffusion for the JFET realization, (ii) backside phosphorusdoped polysilicon gettering to preserve the high carrier generation lifetime required for optimal detector operation. The fabrication process can be outlined as follows: f starting material: 500 lm thick, S1 1 1T oriented, n-type, 5 k) cm FZ silicon wafers; f P-doped poly-Si backside deposition; f screen oxide growth (20 nm); f n-channel implant (P, 7.0]1012 cm~2, 220 keV); f p-well (bottom gate) implant (B, 1.0]1012 cm~2, 250 keV); f diffusion (975°C, 150 min); f gate/well-contact implant (B, 2.0]1014 cm~2, 30 keV); f source/drain implant (P, 1.0]1015 cm~2, 90 keV); f LTO deposition (900 nm) annealing (850°C, N ); 2 f contacts opening, metallization and sintering. Some modifications to the main fabrication process have been implemented as process splits. These include: (i) two alternative values for the JFET channel implantation dose, namely 6.0]1012 and 8.0]1012 cm~2; (ii) a simpler backside contact using a P implant (5.0]1015 cm~2, 120 keV) as an alternative to the P-doped polysilicon layer; (iii) a modified JFET fabrication strategy which makes use of lower channel and well implant energies (attainable by single-charged ion implantation) but necessitates a longer JFET drive-in (170 min in dry O followed by 200 min in N ). 2 2 3. Results 3.1. Test structures Fig. 1 shows the leakage current versus reverse voltage curves in p`(JFET gate)—n~!n` diodes obtained with three different fabrication processes, while average and standard deviation values (referring to ten samples on the same wafer) of the leakage-current density at a reverse voltage of 10 V
(corresponding to about 120 lm depletion width) are reported in Table 1. As can be seen, leakagecurrent densities in the order of 1 nA/cm2 are obtained in the two cases where P-doped polysilicon gettering is adopted. Noticeably, the process with longer drive-in (more than 6 h at 975°C) exhibits diode leakage-current densities which are only slightly increased with respect to those characterizing the main process, whereas much higher values are instead measured in devices treated with the backside P implant. By correlating the reverse I(») diode characteristic with the C(») curve from the same device, it is possible to calculate the generation lifetime, q , whose values are ' also reported in Table 1 for the different fabrication processes.
Fig. 1. Current versus reverse voltage in 3.0 mm2 area, p`(gate)— n~—n` diodes for the main fabrication process and two different process splits.
Table 1 Diode leakage-current density at » "10 V (corresponding to 3%7 about 120 lm depletion width) and corresponding bulk generation lifetimes Process
SJ T L (nA/cm2)
p[J ] L (nA/cm2)
Sq T ' (ms)
p[q ] ' (ms)
Poly gett., main Poly gett., long diff. Backside P-implant
0.82 1.13 132.4
0.13 0.25 13.4
40 31 0.2
15 19 0.08
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G.F. Dalla Betta et al./Nucl. Instr. and Meth. in Phys. Res. A 409 (1998) 346—350 Table 2 Surface generation velocity Process
Ss T 0 (cm/s)
p[s ] 0 (cm/s)
Poly gett., main Poly gett., long diff. Backside P-implant
4.75 4.70 2.80
0.34 0.73 0.30
Fig. 2. Diode current versus gate voltage for different bulk voltages (diode contact grounded) in a gated-diode (main fabrication process).
The surface contribution to leakage current has been evaluated by measuring the reverse current in a gated diode [7]. Fig. 2 shows the diode current as a function of the gate voltage for different bulk voltages measured in a gated diode belonging to a wafer treated with the P-doped polysilicon gettering (main). Once the surface leakage current is known from measurements like that shown in Fig. 2, the surface generation velocity, s , can easily 0 be calculated [7].In Table 2, the average and standard-deviation values of s are summarized for the 0 different process splits. As can be seen, s values 0 ranging from 2.5 to 5 cm/s are measured, which are quite typical for S1 1 1T substrates. 3.2. JFETs Two groups of JFETs are present on the test chip, featuring different layouts and dimensions. Devices belonging to the first group have the gate and well-contact p` implanted regions connected together (triode configuration). On the contrary, the gate and the p-well of devices belonging to the second group have separated contacts, so that they can be biased independently (tetrode configuration). Fig. 3 shows the transfer characteristics of a 200/6 JFET in the triode configuration for the three different channel doses adopted, whereas in
Fig. 3. I versus » characteristics of a 200/6 JFET (triode $ '4 configuration) for three different channel implantation doses.
Fig. 4 the output characteristics of a device with the lowest channel dose are reported for different » values. Despite such figures that demonstrate '4 the JFET is functional, some discrepancies are observed with respect to the intended, simulated performance [6]. As can be seen from Fig. 3, the pinch-off voltage ranges from about !2 V to about !5 V, depending on the channel dose. Correspondingly, the drain saturation current, I , $44 varies from 1.5 mA to about 5 mA. Both D» D and p I values are higher than expected from device $44 simulation [6], indicating that the actual channel conductance is higher than the simulated one. This is also confirmed by channel sheet resistance measurements (not shown). From Fig. 4, then, one notices that the saturating behaviour in the pinch-off region is not very good, so that the JFET output resistance turns out to be much lower than predicted by device simulations
G.F. Dalla Betta et al./Nucl. Instr. and Meth. in Phys. Res. A 409 (1998) 346—350
Fig. 4. I versus » characteristics at different » voltages for $ $4 '4 a 200/6 JFET (triode configuration) obtained with the lowest channel dose.
[6]. Such a result suggests that the confinement provided by the p-well to the electrons flowing in the channel is not as effective as expected. An even more serious consequence of this is that the JFET cannot substain the high bulk voltages needed to fully deplete the silicon substrate. This is clearly evidenced by Fig. 5, showing the drain, source, and bulk currents as a function of the bulk voltage, » (at a given value of » and » ). As can be seen, "4 '4 $4 the drain and source currents depart from each other for » '10 V, indicating that at such bulk "4 voltages the p-well region is completely depleted and the drain and source n` regions are punchedthrough to the n-type substrate. All the observed deviations from the desired behaviour can be explained if the actual p-well doping is assumed to be significantly lower than the simulated one, resulting in effective channel thickness enlargement and poor device isolation. As a matter of fact, spreading resistance measurements confirmed the above explanation. From a technological point of view, there are some critical steps that can be responsible for such a deviation from the simulated doping profile: (i) the p-well implant, which is performed at high energy in a region that is already damaged by the previous phosphorus implantation; (ii) the p-well and the n-channel drivein, that is carried out after the two implantation steps, possibly resulting in an anomalous diffusion
349
Fig. 5. Drain, source, and bulk currents as a function of bulk voltage in a 200/12 JFET (tetrode configuration).
process due to the interaction of the two species diffusing simultaneously. In these conditions, reliable process simulation predictions require the process simulator to be calibrated to the specific fabrication technology. Of course, this could not be done for our devices, that were fabricated for the first time.
4. Conclusions A specially designed test-chip has been manufactured for process/device characterization of a detector-compatible JFET technology. A P-doped polysilicon backside gettering layer allows the additional high-temperature steps required for the JFET implementation to be carried out without significant degradation of diode leakage current. JFET electrical and technological characterization has pointed out that the actual p-well (bottom gate) doping is significantly lower than predicted by simulations, resulting in insufficient device isolation. To solve this problem, a fabrication recycle is currently being carried on, in which the p-well implant dose has suitably been increased.
References [1] V. Radeka, S. Rescia, P.F. Manfredi, V. Re, V. Speziali, Nucl. Instr. and Meth. A 326 (1993) 77.
III. FRONT-END ELECTRONICS
350
G.F. Dalla Betta et al./Nucl. Instr. and Meth. in Phys. Res. A 409 (1998) 346—350
[2] V. Radeka, P. Rehak, S. Rescia, E. Gatti, A. Longoni, M. Sampietro, G. Bertuccio, P. Holl, L. Struder, J. Kemmer, IEEE Electron Dev. Lett. EDL-10(2) (1989) 91. [3] P. Rehak, S. Rescia, V. Radeka, E. Gatti, A. Longoni, M. Sampietro, G. Bertuccio, P. Holl, L. Struder, J. Kemmer, U. Prechtel, T. Zieman, Nucl. Instr. and Meth. A 288 (1990) 168. [4] S. Holland, H. Spieler, IEEE Trans. Nucl. Sci. TNS-37(2) (1990) 463.
[5] W. Snoeys, J.D. Plummer, S. Parker, C. Kenney, IEEE Trans. Electron Devices TED-41(6) (1994) 903. [6] G.F. Dalla Betta, G. Verzellesi, G.U. Pignatel, S. Amon, M. Boscardin, G. Soncini, Nucl. Instr. and Meth. A 365 (1995) 473. [7] G. Vanstraelen, K. De Backker, I. Debuscchere, C. Claeys, G. Declerck, Nucl. Instr. Meth. A 288 (1990) 48.
Development of a detector-compatible JFET technology on high-resistivity silicon G.F. Dalla Betta!,",*, M. Boscardin", G.U. Pignatel!, G. Verzellesi!, L. Bosisio#, L. Ferrario", M. Zen", G. Soncini!," ! Dipartimento di Ingegneria dei Materiali, Universita% di Trento, I-38050 Mesiano (TN), Italy " IRST, Divisione Microsensori ed Integrazione di Sistema, I-38050 Povo (TN), Italy # Dipartimento di Fisica and INFN-Sezione di Trieste, Via A. Valerio 2, I-34127, Trieste, Italy
Abstract We report on the development of a radiation-detector compatible JFET technology on high-resistivity silicon for monolithic integration of detectors and front-end electronics. A dedicated test-chip has been designed and fabricated for process and device characterization. Results from the electrical characterization of a first fabrication run show that good values of detector leakage current (+1 nA/cm2) can be obtained in spite of the relatively high thermal budget characterizing the process. As far as the JFET performance is concerned, a problem of insufficient device isolation at high substrate voltages has been evidenced. A second run is currently being carried on with the aim of optimizing the JFET structure. ( 1998 Elsevier Science B.V. All rights reserved.
1. Introduction Thanks to their low-noise figures and high radiation hardness, Junction Field Effect Transistors (JFETs) are widely used as active components in the front-end electronics of silicon radiation detectors [1]. Monolithic integration of the preamplification stage on the detector chip can give further advantages in terms of performance enhancement as well as system assembly simplification [2]. A key requirement, however, is that the additional process steps necessary for the JFET fabrication do not degrade significantly the detector leakage current. This task can be accomplished either by min* Correspondence address: Dipartimento di Ingegneria dei Materiali, Universita` di Trento, I-38050 Mesiano (TN), Italy.
imizing the number of high-temperature thermal cycles [3], or, alternatively, by making use of extrinsic-gettering techniques [4,5]. This work is devoted to the definition of a JFET technology on high-resistivity silicon for the fabrication of fully depleted, PIN radiation detectors with on-chip, JFET-based preamplifiers. The JFET structure and doping profile has been defined and optimized by means of 2D numerical process/device simulations [6]. In this paper, we report on the electrical characterization of a dedicated test chip containing JFETs, PIN diodes, and other test structures (including Van der Pauw resistors, gated diodes, as well as MOS capacitors and transistors), which has been designed and fabricated to allow for the characterization of the proposed JFET technology.
0168-9002/98/$19.00 ( 1998 Elsevier Science B.V. All rights reserved PII S 0 1 6 8 - 9 0 0 2 ( 9 7 ) 0 1 2 9 6 - 5
347
G.F. Dalla Betta et al./Nucl. Instr. and Meth. in Phys. Res. A 409 (1998) 346—350
2. Fabrication technology The technological approach adopted features (i) triple ion implantation and thermal diffusion for the JFET realization, (ii) backside phosphorusdoped polysilicon gettering to preserve the high carrier generation lifetime required for optimal detector operation. The fabrication process can be outlined as follows: f starting material: 500 lm thick, S1 1 1T oriented, n-type, 5 k) cm FZ silicon wafers; f P-doped poly-Si backside deposition; f screen oxide growth (20 nm); f n-channel implant (P, 7.0]1012 cm~2, 220 keV); f p-well (bottom gate) implant (B, 1.0]1012 cm~2, 250 keV); f diffusion (975°C, 150 min); f gate/well-contact implant (B, 2.0]1014 cm~2, 30 keV); f source/drain implant (P, 1.0]1015 cm~2, 90 keV); f LTO deposition (900 nm) annealing (850°C, N ); 2 f contacts opening, metallization and sintering. Some modifications to the main fabrication process have been implemented as process splits. These include: (i) two alternative values for the JFET channel implantation dose, namely 6.0]1012 and 8.0]1012 cm~2; (ii) a simpler backside contact using a P implant (5.0]1015 cm~2, 120 keV) as an alternative to the P-doped polysilicon layer; (iii) a modified JFET fabrication strategy which makes use of lower channel and well implant energies (attainable by single-charged ion implantation) but necessitates a longer JFET drive-in (170 min in dry O followed by 200 min in N ). 2 2 3. Results 3.1. Test structures Fig. 1 shows the leakage current versus reverse voltage curves in p`(JFET gate)—n~!n` diodes obtained with three different fabrication processes, while average and standard deviation values (referring to ten samples on the same wafer) of the leakage-current density at a reverse voltage of 10 V
(corresponding to about 120 lm depletion width) are reported in Table 1. As can be seen, leakagecurrent densities in the order of 1 nA/cm2 are obtained in the two cases where P-doped polysilicon gettering is adopted. Noticeably, the process with longer drive-in (more than 6 h at 975°C) exhibits diode leakage-current densities which are only slightly increased with respect to those characterizing the main process, whereas much higher values are instead measured in devices treated with the backside P implant. By correlating the reverse I(») diode characteristic with the C(») curve from the same device, it is possible to calculate the generation lifetime, q , whose values are ' also reported in Table 1 for the different fabrication processes.
Fig. 1. Current versus reverse voltage in 3.0 mm2 area, p`(gate)— n~—n` diodes for the main fabrication process and two different process splits.
Table 1 Diode leakage-current density at » "10 V (corresponding to 3%7 about 120 lm depletion width) and corresponding bulk generation lifetimes Process
SJ T L (nA/cm2)
p[J ] L (nA/cm2)
Sq T ' (ms)
p[q ] ' (ms)
Poly gett., main Poly gett., long diff. Backside P-implant
0.82 1.13 132.4
0.13 0.25 13.4
40 31 0.2
15 19 0.08
III. FRONT-END ELECTRONICS
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G.F. Dalla Betta et al./Nucl. Instr. and Meth. in Phys. Res. A 409 (1998) 346—350 Table 2 Surface generation velocity Process
Ss T 0 (cm/s)
p[s ] 0 (cm/s)
Poly gett., main Poly gett., long diff. Backside P-implant
4.75 4.70 2.80
0.34 0.73 0.30
Fig. 2. Diode current versus gate voltage for different bulk voltages (diode contact grounded) in a gated-diode (main fabrication process).
The surface contribution to leakage current has been evaluated by measuring the reverse current in a gated diode [7]. Fig. 2 shows the diode current as a function of the gate voltage for different bulk voltages measured in a gated diode belonging to a wafer treated with the P-doped polysilicon gettering (main). Once the surface leakage current is known from measurements like that shown in Fig. 2, the surface generation velocity, s , can easily 0 be calculated [7].In Table 2, the average and standard-deviation values of s are summarized for the 0 different process splits. As can be seen, s values 0 ranging from 2.5 to 5 cm/s are measured, which are quite typical for S1 1 1T substrates. 3.2. JFETs Two groups of JFETs are present on the test chip, featuring different layouts and dimensions. Devices belonging to the first group have the gate and well-contact p` implanted regions connected together (triode configuration). On the contrary, the gate and the p-well of devices belonging to the second group have separated contacts, so that they can be biased independently (tetrode configuration). Fig. 3 shows the transfer characteristics of a 200/6 JFET in the triode configuration for the three different channel doses adopted, whereas in
Fig. 3. I versus » characteristics of a 200/6 JFET (triode $ '4 configuration) for three different channel implantation doses.
Fig. 4 the output characteristics of a device with the lowest channel dose are reported for different » values. Despite such figures that demonstrate '4 the JFET is functional, some discrepancies are observed with respect to the intended, simulated performance [6]. As can be seen from Fig. 3, the pinch-off voltage ranges from about !2 V to about !5 V, depending on the channel dose. Correspondingly, the drain saturation current, I , $44 varies from 1.5 mA to about 5 mA. Both D» D and p I values are higher than expected from device $44 simulation [6], indicating that the actual channel conductance is higher than the simulated one. This is also confirmed by channel sheet resistance measurements (not shown). From Fig. 4, then, one notices that the saturating behaviour in the pinch-off region is not very good, so that the JFET output resistance turns out to be much lower than predicted by device simulations
G.F. Dalla Betta et al./Nucl. Instr. and Meth. in Phys. Res. A 409 (1998) 346—350
Fig. 4. I versus » characteristics at different » voltages for $ $4 '4 a 200/6 JFET (triode configuration) obtained with the lowest channel dose.
[6]. Such a result suggests that the confinement provided by the p-well to the electrons flowing in the channel is not as effective as expected. An even more serious consequence of this is that the JFET cannot substain the high bulk voltages needed to fully deplete the silicon substrate. This is clearly evidenced by Fig. 5, showing the drain, source, and bulk currents as a function of the bulk voltage, » (at a given value of » and » ). As can be seen, "4 '4 $4 the drain and source currents depart from each other for » '10 V, indicating that at such bulk "4 voltages the p-well region is completely depleted and the drain and source n` regions are punchedthrough to the n-type substrate. All the observed deviations from the desired behaviour can be explained if the actual p-well doping is assumed to be significantly lower than the simulated one, resulting in effective channel thickness enlargement and poor device isolation. As a matter of fact, spreading resistance measurements confirmed the above explanation. From a technological point of view, there are some critical steps that can be responsible for such a deviation from the simulated doping profile: (i) the p-well implant, which is performed at high energy in a region that is already damaged by the previous phosphorus implantation; (ii) the p-well and the n-channel drivein, that is carried out after the two implantation steps, possibly resulting in an anomalous diffusion
349
Fig. 5. Drain, source, and bulk currents as a function of bulk voltage in a 200/12 JFET (tetrode configuration).
process due to the interaction of the two species diffusing simultaneously. In these conditions, reliable process simulation predictions require the process simulator to be calibrated to the specific fabrication technology. Of course, this could not be done for our devices, that were fabricated for the first time.
4. Conclusions A specially designed test-chip has been manufactured for process/device characterization of a detector-compatible JFET technology. A P-doped polysilicon backside gettering layer allows the additional high-temperature steps required for the JFET implementation to be carried out without significant degradation of diode leakage current. JFET electrical and technological characterization has pointed out that the actual p-well (bottom gate) doping is significantly lower than predicted by simulations, resulting in insufficient device isolation. To solve this problem, a fabrication recycle is currently being carried on, in which the p-well implant dose has suitably been increased.
References [1] V. Radeka, S. Rescia, P.F. Manfredi, V. Re, V. Speziali, Nucl. Instr. and Meth. A 326 (1993) 77.
III. FRONT-END ELECTRONICS
350
G.F. Dalla Betta et al./Nucl. Instr. and Meth. in Phys. Res. A 409 (1998) 346—350
[2] V. Radeka, P. Rehak, S. Rescia, E. Gatti, A. Longoni, M. Sampietro, G. Bertuccio, P. Holl, L. Struder, J. Kemmer, IEEE Electron Dev. Lett. EDL-10(2) (1989) 91. [3] P. Rehak, S. Rescia, V. Radeka, E. Gatti, A. Longoni, M. Sampietro, G. Bertuccio, P. Holl, L. Struder, J. Kemmer, U. Prechtel, T. Zieman, Nucl. Instr. and Meth. A 288 (1990) 168. [4] S. Holland, H. Spieler, IEEE Trans. Nucl. Sci. TNS-37(2) (1990) 463.
[5] W. Snoeys, J.D. Plummer, S. Parker, C. Kenney, IEEE Trans. Electron Devices TED-41(6) (1994) 903. [6] G.F. Dalla Betta, G. Verzellesi, G.U. Pignatel, S. Amon, M. Boscardin, G. Soncini, Nucl. Instr. and Meth. A 365 (1995) 473. [7] G. Vanstraelen, K. De Backker, I. Debuscchere, C. Claeys, G. Declerck, Nucl. Instr. Meth. A 288 (1990) 48.