- Email: [email protected]
Development of a two-dimensional ASIC for hard X-ray spectroscopy and imaging with a CdTe pixel detector
ARTICLE IN PRESS
Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262 www.elsevier.com/locate/nima
Development of a two-dimensional ASIC for hard X-ray spectroscopy and imaging with a CdTe pixel detector Tatsuro Hirutaa,b,, K. Tamuraa,b, H. Ikedaa, K. Nakazawaa, T. Takasimaa, T. Takahashia,b a
Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510, Japan b Department of Physics, The University of Tokyo, Bunkyo, Tokyo 113-0033, Japan Available online 13 June 2006
Abstract We are developing a two-dimensional analog ASIC for the readout of pixel sensors based on silicon (Si) or cadmium telluride (CdTe) for spectroscopic imaging observations in the X-ray and gamma-ray regions. The aim for the ASIC is to obtain a low-noise performance better than 100 electrons (rms) with self-triggering capabilities. As the first step of prototyping, we have fabricated several ASICs. We obtained an energy resolution of 5.4 keV (FWHM) for 81 keV gamma-rays from 133Ba with a one-dimensional ASIC connected to a CdTe diode and also verified a readout architecture via a two-dimensional ASIC with 144 pixel channels. Based on the results obtained and experience gained through prototype ASICs, we are developing a 4096-channel two-dimensional analog ASIC. r 2006 Elsevier B.V. All rights reserved. Keywords: Two-dimensional ASIC; X-ray; Gamma-ray; CdTe
1. Introduction Two-dimensional analog ASIC is advantageous for the next generation of hard X-ray and gamma-ray detectors. We are particularly developing these detectors utilizing Si and CdTe as detector materials for astrophysics [1–3]. One of them is the hard X-ray spectroscopy and imaging detector that consists of a supermirror hard X-ray telescope and a CdTe pixel detector [4,5]. This detector requires a spatial resolution of 200 mm and the total detector size of 2 3 cm2 with several thousand pixels. It is not practical to readout the signals of all the pixels by pulling out the signal wires. The two-dimensional analog ASIC can be connected to the pixel detector by a studbump technique [3] and has an analog circuit in each pixel to readout the signal from the corresponding pixel of the detector. This capability enables us to readout several thousand pixels. The goal of the ASIC is to obtain a low Corresponding author. Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510, Japan. Tel.: +81 42 759 8136; fax: +81 42 759 8546. E-mail address: [email protected] (T. Hiruta).
0168-9002/$ - see front matter r 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2006.05.007
noise performance better than 100 electrons (rms) with selftriggering capability, a timing resolution of a few tens of ms to improve the background reduction via anti-coincidence and low power consumption smaller than 250 mW=pixel. We are developing the required ASICs in collaboration with several research institutes. Although several ASICs with sufficient energy resolution have recently been developed [6–8], none of them necessarily satisfies all our requirements in full (e.g. spectroscopy function, timing resolution or power consumption). In this paper, we will report on the development of the two-dimensional analog ASIC, called H02. Fig. 1 shows a schematic diagram of our ASIC development strategy. The first objective of our project is to construct a set of verified circuit block designs to be used for the signal processing of radiation detectors. These blocks include signal amplification, shaping, and triggering. Special care is being taken to establish a standard design for low-noise analog circuits. The second objective of our project is to develop a fast and effective two-dimensional ASIC readout system and interconnecting technology with a detector. The details of these prototype ASICs are reviewed by Tamura et al. [9].
ARTICLE IN PRESS T. Hiruta et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262
ROHM 0.35 µm 32ch K01
TSMC 64ch
0.35 µm
K02
Analog output Test pulse
1-dim VLSI chips
Peak Hold CSA
Input
PZC
ROHM 0.35 µm 144ch 260µm pitch H02
H01
2003
259
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2005
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Fig. 2. Analog circuit diagram of the 12 12-pixel two-dimensional ASIC, H01. Consisting of a CSA, differentiation–integration circuit with PZC, 2-stage gain amplifiers, peak-hold circuit and comparator.
year 12x12-channel Analog block
Fig. 1. Schematic diagram of ASIC development strategy.
Peak-hold output
2. Performance of the prototype chips
(P/H)
2.1. Two-dimensional ASIC, H01 As a first step to develop a two-dimensional ASIC, we designed a two-dimensional 12 12 pixel analog ASIC, H01. The pixel size was 260 260 mm2 and the chip size was 4:9 4:9 mm2 . The ASIC was fabricated using the 0:35mm CMOS process of ROHM. The VLSI Design and Education Center at the University of Tokyo (VDEC) hosted the production program. Fig. 2 shows a schematic of the linear amplification stage of H01. Each channel of the ASIC consisted of a charge sensitive preamplifier (CSA), differentiation–integration circuit with a pole-zero-cancellation circuit (PZC), twostage gain amplifiers, peak-hold circuit, comparator, analog multiplexer circuit and digital-control circuits. Fig. 3 shows readout block diagram of H01. When a trigger signal is generated, the logic inside the ASIC automatically searches for the 3 3 channels surrounding the hit-channel and serially outputs the analog pulse height data from the peak-hold circuits. The output is fed into an analog-to-digital converter (ADC) located outside the chip. In this way we can handle a vast number of channels in pixel imaging detectors. A 12 12 pixel CdTe diode detector was connected to this ASIC using our gold studbump technology. The size of the detector was 3:3 3:3 mm2 with a thickness of 0.3 mm. We succeeded in obtaining signals from radioactive sources. This prototype chip had two problems of analog circuit. The first was that the DC level of the peak-hold output varied over a large range among the channels. Therefore, it was difficult to determine a common threshold level to operate multiple channels. The second problem was that the noise level was greater than 1000 electrons (rms). In order to solve these problems, we re-designed this analog part into a one-dimensional 64-channel analog ASIC, K02. 2.2. Improvement of the analog circuits A one-dimensional analog ASIC, K02, was fabricated using a 0:35mm CMOS process of TSMC. The input pitch of each channel was 120 mm and the chip size was 10 5 mm2 . The analog circuit diagram is shown in Fig. 4.
hit-channel
Digital readout block (P/H) 9-channels selection circuit
144 channels
(P/H) 12x12-channels Analog block
Mux 9
to ADC outside the chip
Digital readout block
Fig. 3. H01 readout block diagram. A sparse readout scheme is implemented to only readout triggered channels together with the surroundings channels.
P
0.2 pF
Test pulse
Peak Hold
Diff cir PZC
CSA
Charge input MON_B1
MON_B2
Analog output Trigger
V threshold
Fig. 4. K02 analog circuit diagram.
The DC level variation of H01 was identified as the fluctuation of parameters among FETs in the manufacturing process, which were larger than expected. To overcome this problem, a simple AC-coupled integrator circuit was introduced. In addition, a gain amplifier was added right after the CSA to reduce the noise generated in the PZC circuit (Fig. 4). As a result of these measures, the measured DC level variation decreased to less than 10% of the dynamic range. In addition, we confirmed that the noise level of the monitor channel decreased to 317 electrons (rms) at 0 pF of input capacitance and 2:1 ms of peaking time. The output signals of preamplifier and PZC circuit as observed on the monitoring outputs are shown in Fig. 5.
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T. Hiruta et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262
We assembled this chip with a CdTe diode detector to obtain the gamma-ray spectra. The size of the detector was 2 2 mm2 with a thickness of 0.5 mm, surrounded by a guard-ring with a width of 1 mm. The energy resolution was 4.6 keV (FWHM) or 435 electron (RMS) for 59.5 keV with an operating temperature of 20 C and a bias voltage of 400 V [9]. The obtained energy resolution for K02 did not attain our goal of 100 electron (rms) due to sensitivity of the CSA to the DC power rail ripple. 3. Designing of a new generation two-dimensional ASIC, H02 3.1. Overview of the H02 chip sec Fig. 5. K02 experimental monitor outputs. The test pulse equivalent to a positive charge of 1300 electrons is injected. These waveforms are inverted on the test board. MON_B1 is analog output of the CSA. MON_B2 is an output of the PZC circuit after the gain amplifier.
Based on the results and know-how gained through the development and testing of prototype ASICs, we started development of the new two-dimensional analog ASIC, called H02. The ASIC was fabricated using a 0:25mm CMOS process of TSMC with options such as five-metal, double-poly, deep N-well and medium VT. The step-bystep verification of the chip performance is scheduled for later this year. The pixel size of this ASIC is 200 200 mm2 with a chip size of 16 16 mm2 , which accommodates the 4096 channels of the amplifier array. This chip consists of four 8 8 mm2 sub-chips that are rotated and assembled to conform with the 4096-channel chips. Fig. 6 shows a layout of the circuit for a pixel. Each sub-chip can be operated independently in order to achieve a higher readout speed. The power rails employed are 1:25 V and the designed power consumption is 150 mW per channel. 3.2. Analog processing chain Fig. 7 shows a schematic of the analog processing chain for each pixel. The ASIC consists of a CSA, shaping amplifier, peak-hold circuit, analog multiplexer circuit and digital-control circuit. The preamplifier is configured as a p-MOS-input foldedcascade amplifier with a gain-boost for the cascade transistor. The gain-boost suppresses a reduction of the output amplitude due to an increase in the input capacitance. The feedback capacitor of the CSA can be selected from among 0.01 and 0.02 pF with a control signal
Fig. 6. Layout of the circuit for a pixel.
RST2
LOWG
RST2
SLOW
TPENB Peak Hold
TP
CSA
AIN
AOUT
HLD TRK MON1
MON2
FAST
HIT RST1
ADJ DAC
Fig. 7. H02 analog circuit diagram.
D[0 : 2]
ARTICLE IN PRESS T. Hiruta et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262
Voltage [mV]
LOWG. With this option, a dynamic range of 10–200 and 5–100 keV can be supported. The DC restoration circuit is implemented with a switch circuit, which provides a stepwise output signal, and then needs no pole-zero cancellation circuit in the following amplification stage. The output of the CSA is fed into a three-stage amplification stage. The first stage is a RC integrator, whose time constant is 1 ms. The resistor is implemented with a transconductor circuit by applying an appropriate bias current. Since the feedback element is a capacitor, a switch circuit operated by RST2 is employed for a DC restoration. The second stage is an inverting amplifier to adjust the signal polarity, whose gain is set as slightly larger than unity. The third stage is split into two parts, one is a slow filter, and the other is a fast filter. The slow filter is configured as a RC-CR filter, whose time constant is 1 ms. The overall peaking time of the slow filter (SLOW) is 2 ms to be fed into a peak-hold circuit. The fast filter channel (FAST) provides a steep signal whose peaking time is 1 ms or less, which is fed into a comparator circuit to be employed for a trigger use. The peak-hold circuit consists of a peak-detect circuit and a hold circuit. The peak-detect circuit employs a p-MOS diode as a rectification device. The peak-detect mode is enabled by TRK ¼ L, and disabled by TRK ¼ H. The output of the peak-detect circuit can be quickly saved by the hold circuit whose hold capacitor is set as 1 pF. The hold signal, HLD, is supplied by an external control circuit in response to a trigger output, TRG. The output of the peak-hold circuit, is fed into a multiplexor circuit to be sequentially processed by an external A-to-D converter. Fig. 8 shows the simulated waveforms of the monitor outputs from the simulations. The comparator circuit consists of a discriminator, a Dflip/flop with an enable function, and a trim DAC. At the output of the discriminator, a Schmidt-trigger inverter is
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employed. The D-flip/flop is enabled only for HLD ¼ L, and is reset by TRK ¼ H. The trim DAC is a three-bit current DAC controlled by a three bit code D[0:2] provided by a control register. The output of the trim-DAC is summed with an externally supplied global threshold (ADJ) to be fed into a reference terminal of the discriminator. 3.3. Design improvements for noise reduction In order to keep up with the low-noise characteristics, special care was taken for the reinforcement of the powersupply ripple rejection. We inserted a CR-filter, which consists of a MOS-capacitor and off-transistor, in the CSA to stabilize the voltage between VL and VSS (Fig. 9). The bias circuit for the CSA was also stabilized using capacitors between the bias-voltage and power-supply lines. Fig. 10 shows the sensitivity results of the analog output to the VSS ripple. We adopted a deep N-well process to decrease interference between analog and digital circuits by isolating the analog circuits from the digital circuits. We also separated the analog circuit from the digital circuit on a layout basis (e.g. power supplies). Eventually the electronic noise was confirmed to be suppressed down to 100 electrons (rms) or less at 1:4 ms of peaking time with a CdTe pixel detector which capacitance is smaller than 1 pF as the simulation basis (Fig. 11). 3.4. Readout sequence By moving RST1, RST2, TRK, and HLD from H to L, the readout system waits for an assertion of TRG. Once detecting TRG ¼ H, HLD is asserted, and then RST1 and RST2 are moved from L to H. The TRG is inhibited during the analog readout. The readout sequence proceeds two steps. Fig. 12 shows the principle behind the readout
Time [s] Fig. 8. H02 simulation output waveforms. From the top, the outputs of the CSA, 2nd gain-amplifier, slow shaper together with peak-hold circuit and fast shaper.
261
Fig. 9. Preamplifier of H02.
ARTICLE IN PRESS T. Hiruta et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262
Voltage Magnitude [dB]
262
without filter
with filter
Frequency [Hz] Fig. 10. Sensitivity of the slow output to VSS ripple.
system. A first step is the readout of the hit-pattern, the X–Y hit information of the hit-channel are projected into the shift registers located at the fringe of the amplifier array. A second step is the readout of the peak-hold output of triggered channel together with the surrounding channel. Based on the X–Y hit-pattern, pixel-select signals (XSEL, YSEL) and clock signals (XCK, YCK) on each axis are sent from an external control circuit. The pixelselect signal moves to the next block for each clock signal. The X–Y readout location can be specified by a logical multiplication of XSEL and YSEL. The readout time of this sequence is about 24 ms. 4. Conclusion
Noise (RMS) [electron]
We are developing a two-dimensional ASIC for hard Xray imagers and spectrometers. So far we have developed H01 and K02, and have developed H02 based on these chips. Electronic noise suppressed down to 100 electrons (rms) or less on a simulation basis was confirmed and entire pixel circuit can be placed in an area of 200 200 mm2 . We have readily obtained H02 to initiate evaluation procedures. Acknowledgments
Input Capacitance [pF] Fig. 11. H02 simulated electronic noise.
Some ASICs in this study were fabricated in the chip fabrication program of the VLSI Design and Education Center (VDEC) of the University of Tokyo in collaboration with Rohm Corporation and Toppan Printing Corporation. References
XSEL
YSEL
YCK Xi
CAPXY
CAPL
XCK Xj
XHIT AND XSEL
CAPT
CELL
XHIT YHIT AND YSEL
YHIT Trigger
Fig. 12. H02 readout block diagram.
[1] T. Takahashi, K. Nakazawa, T. Kamae, H. Tajima, Y. Fukazawa, M. Nomachi, M. Kokubun, SPIE 4851 (2003) 1228. [2] K. Nakazawa, T. Takahashi, S. Watanabe, G. Sato, M. Kouda, Y. Okada, T. Mitani, Y. Kobayashi, Y. Kuroda, M. Onishi, R. Ohno, H. Kitajima, Nucl. Instr. and Meth. A 512 (2003) 412. [3] K. Nakazawa, K. Oonuki, T. Tanaka, Y. Kobayashi, K. Tamura, T. Mitani, G. Sato, S. Watanabe, T. Takahashi, R. Ohno, A. Kitajima, Y. Kuroda, M. Onishi, IEEE Trans. Nucl. Sci. NS-51 (2004) 1881. [4] T. Takahashi, et al., Nucl. Instr. and Meth. A 541 (2005) 332. [5] T. Takahashi, et al., Proc. SPIE 5488 (2004) 549. [6] H. Tajima, T. Kamae, G. Madejski, E. do Couto e Silva, S. Uno, T. Nakamoto, Y. Fukazawa, T. Mitani, T. Tanaka, T. Takahashi, K. Nakazawa, Y. Okada, M. Nomachi, D. Marlow, IEEE Trans. Nucl. Sci. NS-51 (2004) 842. [7] M. Loecker, P. Fischer, S. Krimmel, H. Krueger, M. Lindner, K. Nakazawa, T. Takahashi, N. Wermes, IEEE Trans. Nucl. Sci. NS-51 (2004) 1717. [8] K. Oonuki, H. Inoue, K. Nakazawa, T. Mitani, T. Tanaka, T. Takahashi, H.C.M. Chen, W.R. Cook, F.A. Harrison, Proc. SPIE 5501 (2004) 218. [9] K. Tamura, T. Hiruta, H. Ikeda, H. Inoue, T. Kiyuna, Y. Kobayashi, K. Nakazawa, T. TakashimaT, T. Takahashi, IEEE Trans. Nucl. Sci. NS-52 (2005) 2023.
Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262 www.elsevier.com/locate/nima
Development of a two-dimensional ASIC for hard X-ray spectroscopy and imaging with a CdTe pixel detector Tatsuro Hirutaa,b,, K. Tamuraa,b, H. Ikedaa, K. Nakazawaa, T. Takasimaa, T. Takahashia,b a
Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510, Japan b Department of Physics, The University of Tokyo, Bunkyo, Tokyo 113-0033, Japan Available online 13 June 2006
Abstract We are developing a two-dimensional analog ASIC for the readout of pixel sensors based on silicon (Si) or cadmium telluride (CdTe) for spectroscopic imaging observations in the X-ray and gamma-ray regions. The aim for the ASIC is to obtain a low-noise performance better than 100 electrons (rms) with self-triggering capabilities. As the first step of prototyping, we have fabricated several ASICs. We obtained an energy resolution of 5.4 keV (FWHM) for 81 keV gamma-rays from 133Ba with a one-dimensional ASIC connected to a CdTe diode and also verified a readout architecture via a two-dimensional ASIC with 144 pixel channels. Based on the results obtained and experience gained through prototype ASICs, we are developing a 4096-channel two-dimensional analog ASIC. r 2006 Elsevier B.V. All rights reserved. Keywords: Two-dimensional ASIC; X-ray; Gamma-ray; CdTe
1. Introduction Two-dimensional analog ASIC is advantageous for the next generation of hard X-ray and gamma-ray detectors. We are particularly developing these detectors utilizing Si and CdTe as detector materials for astrophysics [1–3]. One of them is the hard X-ray spectroscopy and imaging detector that consists of a supermirror hard X-ray telescope and a CdTe pixel detector [4,5]. This detector requires a spatial resolution of 200 mm and the total detector size of 2 3 cm2 with several thousand pixels. It is not practical to readout the signals of all the pixels by pulling out the signal wires. The two-dimensional analog ASIC can be connected to the pixel detector by a studbump technique [3] and has an analog circuit in each pixel to readout the signal from the corresponding pixel of the detector. This capability enables us to readout several thousand pixels. The goal of the ASIC is to obtain a low Corresponding author. Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510, Japan. Tel.: +81 42 759 8136; fax: +81 42 759 8546. E-mail address: [email protected] (T. Hiruta).
0168-9002/$ - see front matter r 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2006.05.007
noise performance better than 100 electrons (rms) with selftriggering capability, a timing resolution of a few tens of ms to improve the background reduction via anti-coincidence and low power consumption smaller than 250 mW=pixel. We are developing the required ASICs in collaboration with several research institutes. Although several ASICs with sufficient energy resolution have recently been developed [6–8], none of them necessarily satisfies all our requirements in full (e.g. spectroscopy function, timing resolution or power consumption). In this paper, we will report on the development of the two-dimensional analog ASIC, called H02. Fig. 1 shows a schematic diagram of our ASIC development strategy. The first objective of our project is to construct a set of verified circuit block designs to be used for the signal processing of radiation detectors. These blocks include signal amplification, shaping, and triggering. Special care is being taken to establish a standard design for low-noise analog circuits. The second objective of our project is to develop a fast and effective two-dimensional ASIC readout system and interconnecting technology with a detector. The details of these prototype ASICs are reviewed by Tamura et al. [9].
ARTICLE IN PRESS T. Hiruta et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262
ROHM 0.35 µm 32ch K01
TSMC 64ch
0.35 µm
K02
Analog output Test pulse
1-dim VLSI chips
Peak Hold CSA
Input
PZC
ROHM 0.35 µm 144ch 260µm pitch H02
H01
2003
259
2004
2-dim VLSI chips
2005
V threshold
Trigger
Fig. 2. Analog circuit diagram of the 12 12-pixel two-dimensional ASIC, H01. Consisting of a CSA, differentiation–integration circuit with PZC, 2-stage gain amplifiers, peak-hold circuit and comparator.
year 12x12-channel Analog block
Fig. 1. Schematic diagram of ASIC development strategy.
Peak-hold output
2. Performance of the prototype chips
(P/H)
2.1. Two-dimensional ASIC, H01 As a first step to develop a two-dimensional ASIC, we designed a two-dimensional 12 12 pixel analog ASIC, H01. The pixel size was 260 260 mm2 and the chip size was 4:9 4:9 mm2 . The ASIC was fabricated using the 0:35mm CMOS process of ROHM. The VLSI Design and Education Center at the University of Tokyo (VDEC) hosted the production program. Fig. 2 shows a schematic of the linear amplification stage of H01. Each channel of the ASIC consisted of a charge sensitive preamplifier (CSA), differentiation–integration circuit with a pole-zero-cancellation circuit (PZC), twostage gain amplifiers, peak-hold circuit, comparator, analog multiplexer circuit and digital-control circuits. Fig. 3 shows readout block diagram of H01. When a trigger signal is generated, the logic inside the ASIC automatically searches for the 3 3 channels surrounding the hit-channel and serially outputs the analog pulse height data from the peak-hold circuits. The output is fed into an analog-to-digital converter (ADC) located outside the chip. In this way we can handle a vast number of channels in pixel imaging detectors. A 12 12 pixel CdTe diode detector was connected to this ASIC using our gold studbump technology. The size of the detector was 3:3 3:3 mm2 with a thickness of 0.3 mm. We succeeded in obtaining signals from radioactive sources. This prototype chip had two problems of analog circuit. The first was that the DC level of the peak-hold output varied over a large range among the channels. Therefore, it was difficult to determine a common threshold level to operate multiple channels. The second problem was that the noise level was greater than 1000 electrons (rms). In order to solve these problems, we re-designed this analog part into a one-dimensional 64-channel analog ASIC, K02. 2.2. Improvement of the analog circuits A one-dimensional analog ASIC, K02, was fabricated using a 0:35mm CMOS process of TSMC. The input pitch of each channel was 120 mm and the chip size was 10 5 mm2 . The analog circuit diagram is shown in Fig. 4.
hit-channel
Digital readout block (P/H) 9-channels selection circuit
144 channels
(P/H) 12x12-channels Analog block
Mux 9
to ADC outside the chip
Digital readout block
Fig. 3. H01 readout block diagram. A sparse readout scheme is implemented to only readout triggered channels together with the surroundings channels.
P
0.2 pF
Test pulse
Peak Hold
Diff cir PZC
CSA
Charge input MON_B1
MON_B2
Analog output Trigger
V threshold
Fig. 4. K02 analog circuit diagram.
The DC level variation of H01 was identified as the fluctuation of parameters among FETs in the manufacturing process, which were larger than expected. To overcome this problem, a simple AC-coupled integrator circuit was introduced. In addition, a gain amplifier was added right after the CSA to reduce the noise generated in the PZC circuit (Fig. 4). As a result of these measures, the measured DC level variation decreased to less than 10% of the dynamic range. In addition, we confirmed that the noise level of the monitor channel decreased to 317 electrons (rms) at 0 pF of input capacitance and 2:1 ms of peaking time. The output signals of preamplifier and PZC circuit as observed on the monitoring outputs are shown in Fig. 5.
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We assembled this chip with a CdTe diode detector to obtain the gamma-ray spectra. The size of the detector was 2 2 mm2 with a thickness of 0.5 mm, surrounded by a guard-ring with a width of 1 mm. The energy resolution was 4.6 keV (FWHM) or 435 electron (RMS) for 59.5 keV with an operating temperature of 20 C and a bias voltage of 400 V [9]. The obtained energy resolution for K02 did not attain our goal of 100 electron (rms) due to sensitivity of the CSA to the DC power rail ripple. 3. Designing of a new generation two-dimensional ASIC, H02 3.1. Overview of the H02 chip sec Fig. 5. K02 experimental monitor outputs. The test pulse equivalent to a positive charge of 1300 electrons is injected. These waveforms are inverted on the test board. MON_B1 is analog output of the CSA. MON_B2 is an output of the PZC circuit after the gain amplifier.
Based on the results and know-how gained through the development and testing of prototype ASICs, we started development of the new two-dimensional analog ASIC, called H02. The ASIC was fabricated using a 0:25mm CMOS process of TSMC with options such as five-metal, double-poly, deep N-well and medium VT. The step-bystep verification of the chip performance is scheduled for later this year. The pixel size of this ASIC is 200 200 mm2 with a chip size of 16 16 mm2 , which accommodates the 4096 channels of the amplifier array. This chip consists of four 8 8 mm2 sub-chips that are rotated and assembled to conform with the 4096-channel chips. Fig. 6 shows a layout of the circuit for a pixel. Each sub-chip can be operated independently in order to achieve a higher readout speed. The power rails employed are 1:25 V and the designed power consumption is 150 mW per channel. 3.2. Analog processing chain Fig. 7 shows a schematic of the analog processing chain for each pixel. The ASIC consists of a CSA, shaping amplifier, peak-hold circuit, analog multiplexer circuit and digital-control circuit. The preamplifier is configured as a p-MOS-input foldedcascade amplifier with a gain-boost for the cascade transistor. The gain-boost suppresses a reduction of the output amplitude due to an increase in the input capacitance. The feedback capacitor of the CSA can be selected from among 0.01 and 0.02 pF with a control signal
Fig. 6. Layout of the circuit for a pixel.
RST2
LOWG
RST2
SLOW
TPENB Peak Hold
TP
CSA
AIN
AOUT
HLD TRK MON1
MON2
FAST
HIT RST1
ADJ DAC
Fig. 7. H02 analog circuit diagram.
D[0 : 2]
ARTICLE IN PRESS T. Hiruta et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262
Voltage [mV]
LOWG. With this option, a dynamic range of 10–200 and 5–100 keV can be supported. The DC restoration circuit is implemented with a switch circuit, which provides a stepwise output signal, and then needs no pole-zero cancellation circuit in the following amplification stage. The output of the CSA is fed into a three-stage amplification stage. The first stage is a RC integrator, whose time constant is 1 ms. The resistor is implemented with a transconductor circuit by applying an appropriate bias current. Since the feedback element is a capacitor, a switch circuit operated by RST2 is employed for a DC restoration. The second stage is an inverting amplifier to adjust the signal polarity, whose gain is set as slightly larger than unity. The third stage is split into two parts, one is a slow filter, and the other is a fast filter. The slow filter is configured as a RC-CR filter, whose time constant is 1 ms. The overall peaking time of the slow filter (SLOW) is 2 ms to be fed into a peak-hold circuit. The fast filter channel (FAST) provides a steep signal whose peaking time is 1 ms or less, which is fed into a comparator circuit to be employed for a trigger use. The peak-hold circuit consists of a peak-detect circuit and a hold circuit. The peak-detect circuit employs a p-MOS diode as a rectification device. The peak-detect mode is enabled by TRK ¼ L, and disabled by TRK ¼ H. The output of the peak-detect circuit can be quickly saved by the hold circuit whose hold capacitor is set as 1 pF. The hold signal, HLD, is supplied by an external control circuit in response to a trigger output, TRG. The output of the peak-hold circuit, is fed into a multiplexor circuit to be sequentially processed by an external A-to-D converter. Fig. 8 shows the simulated waveforms of the monitor outputs from the simulations. The comparator circuit consists of a discriminator, a Dflip/flop with an enable function, and a trim DAC. At the output of the discriminator, a Schmidt-trigger inverter is
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employed. The D-flip/flop is enabled only for HLD ¼ L, and is reset by TRK ¼ H. The trim DAC is a three-bit current DAC controlled by a three bit code D[0:2] provided by a control register. The output of the trim-DAC is summed with an externally supplied global threshold (ADJ) to be fed into a reference terminal of the discriminator. 3.3. Design improvements for noise reduction In order to keep up with the low-noise characteristics, special care was taken for the reinforcement of the powersupply ripple rejection. We inserted a CR-filter, which consists of a MOS-capacitor and off-transistor, in the CSA to stabilize the voltage between VL and VSS (Fig. 9). The bias circuit for the CSA was also stabilized using capacitors between the bias-voltage and power-supply lines. Fig. 10 shows the sensitivity results of the analog output to the VSS ripple. We adopted a deep N-well process to decrease interference between analog and digital circuits by isolating the analog circuits from the digital circuits. We also separated the analog circuit from the digital circuit on a layout basis (e.g. power supplies). Eventually the electronic noise was confirmed to be suppressed down to 100 electrons (rms) or less at 1:4 ms of peaking time with a CdTe pixel detector which capacitance is smaller than 1 pF as the simulation basis (Fig. 11). 3.4. Readout sequence By moving RST1, RST2, TRK, and HLD from H to L, the readout system waits for an assertion of TRG. Once detecting TRG ¼ H, HLD is asserted, and then RST1 and RST2 are moved from L to H. The TRG is inhibited during the analog readout. The readout sequence proceeds two steps. Fig. 12 shows the principle behind the readout
Time [s] Fig. 8. H02 simulation output waveforms. From the top, the outputs of the CSA, 2nd gain-amplifier, slow shaper together with peak-hold circuit and fast shaper.
261
Fig. 9. Preamplifier of H02.
ARTICLE IN PRESS T. Hiruta et al. / Nuclear Instruments and Methods in Physics Research A 565 (2006) 258–262
Voltage Magnitude [dB]
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without filter
with filter
Frequency [Hz] Fig. 10. Sensitivity of the slow output to VSS ripple.
system. A first step is the readout of the hit-pattern, the X–Y hit information of the hit-channel are projected into the shift registers located at the fringe of the amplifier array. A second step is the readout of the peak-hold output of triggered channel together with the surrounding channel. Based on the X–Y hit-pattern, pixel-select signals (XSEL, YSEL) and clock signals (XCK, YCK) on each axis are sent from an external control circuit. The pixelselect signal moves to the next block for each clock signal. The X–Y readout location can be specified by a logical multiplication of XSEL and YSEL. The readout time of this sequence is about 24 ms. 4. Conclusion
Noise (RMS) [electron]
We are developing a two-dimensional ASIC for hard Xray imagers and spectrometers. So far we have developed H01 and K02, and have developed H02 based on these chips. Electronic noise suppressed down to 100 electrons (rms) or less on a simulation basis was confirmed and entire pixel circuit can be placed in an area of 200 200 mm2 . We have readily obtained H02 to initiate evaluation procedures. Acknowledgments
Input Capacitance [pF] Fig. 11. H02 simulated electronic noise.
Some ASICs in this study were fabricated in the chip fabrication program of the VLSI Design and Education Center (VDEC) of the University of Tokyo in collaboration with Rohm Corporation and Toppan Printing Corporation. References
XSEL
YSEL
YCK Xi
CAPXY
CAPL
XCK Xj
XHIT AND XSEL
CAPT
CELL
XHIT YHIT AND YSEL
YHIT Trigger
Fig. 12. H02 readout block diagram.
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