- Email: [email protected]
Development of conductive adhesive joining for surface-mounting electronics manufacturing
552
World abstracts on microelectronics and reliability
With a duplex MIC connector, this package conforms to an industry standard outline and pinout. The optical transceiver easily meets full FDDI specifications. The design integrates an LED, PIN, transmitter IC, receiver IC, and two capacitors in a single, overmolded package. The final assembly sequence was conceived using the latest Design For Simplicity (DFS) principles. This paper describes the design concept and prototype model performance results.
results from the work show that currently available surface-mounting machinery can be used for the conductive adhesive joining process. However, further work is needed to optimize the processing conditions. Transmission electron microscopy analysis of the adhesive joints after temperature cycling and humidity testing shows that oxide layer formation on metal surfaces can be one of the mechanisms which causes decrease in the electrical performance of the joint.
Physical models and algorithms for optoelectronic MCM layout. JIAO FAN, DAVID ZALETA, CHUNG-KUAN CHENG and SING H. LEE. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(1), 124 (March 1995). Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over "long" distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGH's) are extremely attractive optical components for use in free-space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGH's for general interconnection networks require the need for placement algorithms for large processing element (PE's) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGH's for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnect in parallel optoelectronic MCM systems are then identified from which we derive several logical modes for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks.
Carrier and socket technology for high pin count WFP packages. JOSEPH W. FOERSTEL. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, 18(1), 136 (March t995). The Carrier and Socket Technology for high pin count Quad Flat Pack (QFP) packages is a set of three components that can be used in various combinations, that allow for easier manipulation of fine pitch, (fine pitch defined as packages having a lead tip to lead tip spacing of 0.65 mm or less), QFP between various shipping, test, programming, and prototype environments. The three components are the small outline carrier, surface mountable Development Socket, and through hole mountable Programming Socket. The Carrier is designed to protect the leads of the QFP from deformation, while allowing the leads to make electrical connection with the contacts of the two different sockets. The Development Socket is surface mountable with a footprint that is identical to the naked QFP housed within the Carrier. The Programming Socket is a through hole mountable, clam-shell socket, which accepts the same Carrier as the Development Socket. The Carrier and Socket Technology was developed primarily to assist in the development and prototyping of re-configurable QFP devices. Specifically, those QFP devices that need to be placed in a different electrical environment to be re-configured, than the electrical environment the device will be in, once it has been configured to the users satisfaction. The key items of the technology are the QFP compatible footprint of the Development Socket, and the ability of the Carrier to work with both the Development Socket and the Programming Socket. The Carrier allows the user to easily maneuver and transport the QFP by hand between the programming environment, in this case the Programming Socket, and the actual working environment, in most cases a land pattern on a printed circuit, PC, board that the Development Socket can mount to. This cycle of transport between re-configuring of the QFP device, and the actual testing of a given configuration, can be repeated many times. The Carrier protects the fragile leads of the QFP device from physical deformation that can occur during these repeated cycles.
Development of conductive adhesive joining for surface-mounting electronics manufacturing. JOHAN LIU, LARS LJUNGKRONA and ZONGHE LAI, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(2), 313 (May 1995). This paper presents the results of a study of process development for conductive adhesives as solder replacement. The main objective of the work was to investigate the potentials for using conventional surface-mounting equipment for component assembly with conductive adhesives. Two processes have been studied: one which uses both anisotropically and isotropically conductive adhesives and one which uses isotropically conductive adhesives only. The
A four ASIC MCM-C, design for maaufaeturability and the next generation silicon. ED FULCHER and SADA PATIL. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 4 (February 1995). A ceramic MCM was
World abstracts on microelectronics and reliability
With a duplex MIC connector, this package conforms to an industry standard outline and pinout. The optical transceiver easily meets full FDDI specifications. The design integrates an LED, PIN, transmitter IC, receiver IC, and two capacitors in a single, overmolded package. The final assembly sequence was conceived using the latest Design For Simplicity (DFS) principles. This paper describes the design concept and prototype model performance results.
results from the work show that currently available surface-mounting machinery can be used for the conductive adhesive joining process. However, further work is needed to optimize the processing conditions. Transmission electron microscopy analysis of the adhesive joints after temperature cycling and humidity testing shows that oxide layer formation on metal surfaces can be one of the mechanisms which causes decrease in the electrical performance of the joint.
Physical models and algorithms for optoelectronic MCM layout. JIAO FAN, DAVID ZALETA, CHUNG-KUAN CHENG and SING H. LEE. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(1), 124 (March 1995). Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over "long" distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGH's) are extremely attractive optical components for use in free-space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGH's for general interconnection networks require the need for placement algorithms for large processing element (PE's) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGH's for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnect in parallel optoelectronic MCM systems are then identified from which we derive several logical modes for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks.
Carrier and socket technology for high pin count WFP packages. JOSEPH W. FOERSTEL. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, 18(1), 136 (March t995). The Carrier and Socket Technology for high pin count Quad Flat Pack (QFP) packages is a set of three components that can be used in various combinations, that allow for easier manipulation of fine pitch, (fine pitch defined as packages having a lead tip to lead tip spacing of 0.65 mm or less), QFP between various shipping, test, programming, and prototype environments. The three components are the small outline carrier, surface mountable Development Socket, and through hole mountable Programming Socket. The Carrier is designed to protect the leads of the QFP from deformation, while allowing the leads to make electrical connection with the contacts of the two different sockets. The Development Socket is surface mountable with a footprint that is identical to the naked QFP housed within the Carrier. The Programming Socket is a through hole mountable, clam-shell socket, which accepts the same Carrier as the Development Socket. The Carrier and Socket Technology was developed primarily to assist in the development and prototyping of re-configurable QFP devices. Specifically, those QFP devices that need to be placed in a different electrical environment to be re-configured, than the electrical environment the device will be in, once it has been configured to the users satisfaction. The key items of the technology are the QFP compatible footprint of the Development Socket, and the ability of the Carrier to work with both the Development Socket and the Programming Socket. The Carrier allows the user to easily maneuver and transport the QFP by hand between the programming environment, in this case the Programming Socket, and the actual working environment, in most cases a land pattern on a printed circuit, PC, board that the Development Socket can mount to. This cycle of transport between re-configuring of the QFP device, and the actual testing of a given configuration, can be repeated many times. The Carrier protects the fragile leads of the QFP device from physical deformation that can occur during these repeated cycles.
Development of conductive adhesive joining for surface-mounting electronics manufacturing. JOHAN LIU, LARS LJUNGKRONA and ZONGHE LAI, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(2), 313 (May 1995). This paper presents the results of a study of process development for conductive adhesives as solder replacement. The main objective of the work was to investigate the potentials for using conventional surface-mounting equipment for component assembly with conductive adhesives. Two processes have been studied: one which uses both anisotropically and isotropically conductive adhesives and one which uses isotropically conductive adhesives only. The
A four ASIC MCM-C, design for maaufaeturability and the next generation silicon. ED FULCHER and SADA PATIL. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 4 (February 1995). A ceramic MCM was