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Developments in monolithic FET-input amplifiers
Microelectronics and Reliability, Vol. 14, p. 375. Pergamon Press, 1975. Printed in Great Britain
D E V E L O P M E N T S IN M O N O L I T H I C
F E T - I N P U T AMPLIFIERS
D. FULLAGAR ABSTRACT
The first monolithic FET input amplifiers showed two disadvantages when compared against their discrete or hybrid counterparts: their input currents were about two orders of magnitude greater, and their offset voltages were in the 20-50 mV area. The first problem was overcome very rapidly by processing and device layout improvements; devices with input currents in the 1 to 2 pA range have been available for about 2 yr now. More recently, the problem of improving the FET match to reduce the input offset voltage specification has received an increasing degree of attention. Two techniques are proving successful--ion implantation and digitally trimming the offset voltage at wafer test using Avalanche Induced Migration. Ion implafftation has several advantages over conventional diffusion techniques. In the latter process, the transistor emitter and the FET top gate are diffused simultaneously. It is this step which determines the critical transistor base width and FET channel width. Optimising both is akin to the race between the tortoise and the hare; how far behind the tortoise do you start the hare, so that they both arrive at the finish line at the same time? Using ion implantation this problem does not arise, since ion implantation is a low temperature process. All the earlier diffusions remain fixed while the FET gate (for example) is being implanted. The ion implantation process also produces more uniform doping levels across the wafer. In practical terms, simply substituting the use of ion implantation for diffusion processing dramatically improves the FET offset voltage match. Prior to the use of ion implantation, only about 20 % of the devices had offset voltages of less than 10 mV. Using ion implantation, without in any way trying to optimise the masks for the new process, the number of devices with offset voltages of less than 10 mV increases to better than 40 %. The second technique to be discussed, digital offset trimming, is capable of providing a further order of magnitude improvement in input offset voltage specification. The concept of on-chip trimming is by no means new, but early attempts using lasers on film resistors at the wafer stage proved expensive, as well as being unsatisfactory. Accurately aligning the laser beam to the appropriate point on the die was difficult and the energy of the laser beam also generated very large photo currents. The use of digital trimming has overcome these problems.
03
IC
-
05
~lB 0
4C
4
Fig. 1 The technique is best explained with the help of Fig. 1. The offset voltage of the amplifier is first measured at wafer sort, with all the diodes D~ to D 6 unshorted. The diodes are then selectively and permanently shorted so as to reduce the offset voltage from an initial 24 mV (max.) to less than 1 mV. This is accomplished by weighting the resistors in binary form; i.e. R z affects the offset by 24 mV, R 2 by 12 mV, etc., with R 6 having a 0.75 mV affect. Thus the amplifiers are automatically offset nulled while still in wafer form; the rest of the assembly procedure is standard. At the present time, FET input amplifiers with offset voltages less than 2 mV are manufactured in volume using digital trimming. The advantages of a FET-input amplifier which requires no nulling trimpot are obvious. In military applications, the elimination of potentiometers is always desirable and for hybrid circuits the availability of ready-trimmed dice greatly increases the designer's flexibility. Table 1. Examples of FET amplifier using the technologies described above
375
Part Number
Max Vos (mV)
8007C-1 8007M-2 8007C-2 8007C-4 8007M-5 8007C-5
2 2 2 10 10 10
Technology Ion Implant/AIM* Trimmed Ion Implant/AIM Trimmed Ion Implant/AIM Trimmed Ion Implant Ion Implant Ion Implant
* Intersil's "Avalanche Induced Migration" process.
D E V E L O P M E N T S IN M O N O L I T H I C
F E T - I N P U T AMPLIFIERS
D. FULLAGAR ABSTRACT
The first monolithic FET input amplifiers showed two disadvantages when compared against their discrete or hybrid counterparts: their input currents were about two orders of magnitude greater, and their offset voltages were in the 20-50 mV area. The first problem was overcome very rapidly by processing and device layout improvements; devices with input currents in the 1 to 2 pA range have been available for about 2 yr now. More recently, the problem of improving the FET match to reduce the input offset voltage specification has received an increasing degree of attention. Two techniques are proving successful--ion implantation and digitally trimming the offset voltage at wafer test using Avalanche Induced Migration. Ion implafftation has several advantages over conventional diffusion techniques. In the latter process, the transistor emitter and the FET top gate are diffused simultaneously. It is this step which determines the critical transistor base width and FET channel width. Optimising both is akin to the race between the tortoise and the hare; how far behind the tortoise do you start the hare, so that they both arrive at the finish line at the same time? Using ion implantation this problem does not arise, since ion implantation is a low temperature process. All the earlier diffusions remain fixed while the FET gate (for example) is being implanted. The ion implantation process also produces more uniform doping levels across the wafer. In practical terms, simply substituting the use of ion implantation for diffusion processing dramatically improves the FET offset voltage match. Prior to the use of ion implantation, only about 20 % of the devices had offset voltages of less than 10 mV. Using ion implantation, without in any way trying to optimise the masks for the new process, the number of devices with offset voltages of less than 10 mV increases to better than 40 %. The second technique to be discussed, digital offset trimming, is capable of providing a further order of magnitude improvement in input offset voltage specification. The concept of on-chip trimming is by no means new, but early attempts using lasers on film resistors at the wafer stage proved expensive, as well as being unsatisfactory. Accurately aligning the laser beam to the appropriate point on the die was difficult and the energy of the laser beam also generated very large photo currents. The use of digital trimming has overcome these problems.
03
IC
-
05
~lB 0
4C
4
Fig. 1 The technique is best explained with the help of Fig. 1. The offset voltage of the amplifier is first measured at wafer sort, with all the diodes D~ to D 6 unshorted. The diodes are then selectively and permanently shorted so as to reduce the offset voltage from an initial 24 mV (max.) to less than 1 mV. This is accomplished by weighting the resistors in binary form; i.e. R z affects the offset by 24 mV, R 2 by 12 mV, etc., with R 6 having a 0.75 mV affect. Thus the amplifiers are automatically offset nulled while still in wafer form; the rest of the assembly procedure is standard. At the present time, FET input amplifiers with offset voltages less than 2 mV are manufactured in volume using digital trimming. The advantages of a FET-input amplifier which requires no nulling trimpot are obvious. In military applications, the elimination of potentiometers is always desirable and for hybrid circuits the availability of ready-trimmed dice greatly increases the designer's flexibility. Table 1. Examples of FET amplifier using the technologies described above
375
Part Number
Max Vos (mV)
8007C-1 8007M-2 8007C-2 8007C-4 8007M-5 8007C-5
2 2 2 10 10 10
Technology Ion Implant/AIM* Trimmed Ion Implant/AIM Trimmed Ion Implant/AIM Trimmed Ion Implant Ion Implant Ion Implant
* Intersil's "Avalanche Induced Migration" process.