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Diagnosis of interconnects using a structured walking-1 approach
the VLSI journal ELSEVIER
INTEGRATION, the VLSI Journal 19 (1995) 181 198
Diagnosis of interconnects using a structured walking-1 approach" T. Liu, F. Lombardi* Department of Computer Science, Texas A&M University, College Station, TX 77843, USA Received 12 August 1994; revised 4 May 1995
Abstract This paper presents a new approach for testing interconnects for boundary scan architectures. This approach relies on a structured walking-I test set in the sense that a structural analysis based on the layout of the interconnect, is carried out. The proposed structural test method differs from previous approaches as it explicitly avoids aliasing and confounding and is applicable to dense as well as sparse interconnect layouts. The proposed method is applicable to both one-step and two-step test generation and diagnosis of stuck-at as well as bridge faults. Two algorithms with an execution complexity of O(n2), where n is the number of nets in the interconnect, are given. New criteria for test vector compaction are proposed; a greedy condition is exploited to compact test vectors for one-step and two-step diagnosis. For a given interconnect, the two-step diagnosis algorithm requires a number of tests as a function of the number of faults present, while the one-step algorithm requires a fixed number of tests. Simulation results for benchmark and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches compared with previous approaches. It is also shown that the proposed algorithms can be used interchangeably depending on the requirements of the overall test process (such as off/on-line execution as well as reduction in number of vectors and test generation time).
Keywords: Interconnect testing; Diagnosis; Syndrome; Boundary scan
1. Introduction
The miniaturization of digital circuits and today's technologies (such as MCM and WSI) have made possible the manufacturing of high-density layouts and boards [1, 2]. Costs for manufacturing as well as tailoring a general architecture to particular applications for full customization have however increased. The high density and complexity of these systems require that testing and diagnosis must be efficiently implemented to diagnose the occurrence of faults due to either a short or open in nets which are closely adjacent as well as stuck-at faults. At the same time, due to the use of surface-mount technology (SMT) as well as MCMs, a traditional testing technique (such as a bed-of-nails approach) is not very efficient. The standardization by the IEEE of the Boundary This research was supported by grants from the Texas ATP and the Ministry of Education and Science of Japan. * Corresponding author. E-mail: [email protected]. Tel. (409) 845-5464. 0167-9260/95/$9.50 © 1995
Elsevier Science B.V. All rights reserved.
SSDI 0 1 6 7 - 9 2 6 0 ( 9 5 ) 0 0 0 1 0 - 0
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Scan Architecture has simplified testing of this type of systems (from applying and loading test vectors to collecting test outcomes) [3]. If all components on a board support the boundary-scan feature, short, open and stuck-at .faults of all nets in the interconnect can be tested by executing the E X T E S T instruction [4]. Only those components which are usually relatively simple combinational circuits and are considered easy to test, do not support on the board the boundary-scan standard. Diagnosis consists of both fault detection and location and is important because after testing it permits an efficient repair of boards, thus increasing the manufacturing throughput and decreasing costs [5-1. Considerable research has been pursued to fully diagnose interconnects as part of a boundary scan architecture; examples of this type of approaches can be found in [6-10]. The interconnect system is usually analyzed as a set of nets which can be affected by different types of faults, such as stuck-at, short and open [-6,9, 10-]. Diagnosis is usually accomplished by comparing the signatures received at the output pins with the ones provided at the inputs, i.e. no internal probing is permitted in the system. Examples of techniques which utilize probing, can be found in Ref. [ 11] as applicable to substrate testing. For interconnect testing, research has been pursued on shorts (bridge faults) as they are the most likely and more difficult faults to diagnose [1]. Bridging faults can be tested by using either a behavioral testing or a structural testing strategy. Several papers [9, 12] have discussed behavioral testing. In structural testing, the wiring layout of the given network must be specified. As automatic routing systems are often employed for checking layouts, the structure of the nets (such as their positions and connections) is known; therefore, the viability of structural testing of an interconnect is possible and realistic [13]. The objective of this paper is to propose a new approach for testing interconnects in a boundary scan architecture. This approach relies on a structured walking-1 test set in the sense that a structural analysis based on the layout of the interconnect, is carried out. Our structural test method differs from the approach of Ref. [10] as it explicitly avoids aliasing and confounding. The proposed method is applicable to both one-step and two-step diagnosis by considering the testing complexity (as measured by the number of tests and the test generation time) as well as the nature of the testing process itself (either on-line or off-line). Simulation results show that for relatively smaller interconnects, one-step diagnosis is more suitable than two-step diagnosis as the number of tests can be generated and reduced using the propo~..ed structured walking-1 method with relative ease. For large (and hence complex) interconnects, two-step diagnosis is superior due to its flexibility in handling the fault detection and location processes separately. Table 1 summarizes the characteristics of previous and proposed approaches. New criteria for test vector compaction are ,dso proposed; simulation results for benchmark layouts and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches. This paper is organized as follows. Section 2 introduces a brief review of previous methods. Section 3 deals with preliminaries as well as notation. The basic criteria for the proposed method are described in Section 4. Section 5 presents the proposed approach to one-step diagnosis, while Section 6 deals with two-step diagnosis. The process of fault location is analyzed in Section 7. A detailed example and the applicability and execution of the proposed approaches are given in Section 8. Section 9 presents simulation results and a comparative analysis with previous approaches for benchmark layouts as well as random interconnects. In Section 10, conclusions and final remarks are provided.
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Table 1 Approach
Aliasing/confounding
Diagnosis
Comments
Kautz 1-9] Wagner [12] Self-diagnosis [6] Walking- 1 [7] Goel [3]
Yes/Yes No/Yes No/Yes No/No No/No
No Partial Partial Yes Yes
McBean and Moore [10] C-Test [8]
Yes/Yes No/No
Partial Yes
Max-independence [8]
No/No
Yes
Proposed approaches
No/No
Yes
Short sequence Simple test generation Simple diagnosis Very long sequence Sequence length depends on number of faults Long sequence Sequence length depends on number of faults Very difficult ordering; limited practicality Very short sequence Sequence length depends on number of faults
2. Review In this section, a brief review of behavioral and structural testing approaches to interconnects will be presented. The faults in interconnects can be tested by using either a behavioral testing or a structural testing strategy. Several papers [6, 13, 8] have discussed behavioral testing. In structural testing, the wiring layout of the given network must be specified. Structural testing is possible through the knowledge of the layout [14]. In behavioral testing, it is commonly postulated that every net on the board can be shorted to any other net. The Counting Sequence Algorithm of [9] can be used to detect all short faults with a test length (usually referred to as the length of the sequential test vectors (ST V)) of [-log2 n 7, where n is the number of nets in the interconnect. If the test vectors must be applied through a boundary scan chain, the test time will be n [-logzn]. If both the STVs consisting of all 0 and all 1 are included, then a modified counting sequence [3] is obtained. These test vectors permit to diagnose stuck-at faults too. The sequential response vector (SR V) of a net to a STV is then used to detect and/or diagnosis shorts between nets. If the SRV of a net differs from its STV, then this vector is referred to as a fault syndrome. It has been shown in Ref. [8] that the counting sequence cannot diagnose all short faults. If a syndrome in the presence of a fault is the same as the fault-free response of a net, then it is impossible to determine whether or not this net is also a part of the short. The response in this case is referred to as an aliasing syndrome. Similarly, a short between a pair of nets may produce the same syndrome as between another net pair; it is impossible to determine whether or not there is a short between which pair of nets. The response is called a confounding syndrome. Ref. [12] has added test vectors with complement values to the counting sequence such that it is possible to diagnose shorts with unique syndromes (i.e. no aliasing syndromes occur). However, confounding may still occur. Using this approach the test length is 2Flog2(n + 1)7, if vectors with all 0 and all 1 are allowed. The walking-1 test set proposed by Ref. [7] can avoid the aliasing and confounding problems, i.e. it can be used to diagnose all shorts in the nets. The drawback of this method however is that large
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test sets generated as a sequence of length n is required. This is especially severe if a boundary-scan method is employed, in which a sequence of length n requires n 2 testing time. The Max-Independence Algorithm of Ref. [8] generalizes the walking-1 method by defining a diagonally independent matrix; it has been proved in Ref. [13] that this type of test vector will not generate aliasing or confounding syndromes. The walking-1 test set satisfies the independence requirement. Also, if every faulty net has an erroneous output response sequence, then every faulty net can be identified by checking its output response sequence only. A testing process with this property is called self-diagnosing. This method proposed in Ref. [-6] generates all test sequences of length p with p/2 '0' bits, i.e. the STV is a p/2 out of p code. For the approach of Ref. [8], a two-step diagnosis process is applicable: in the first step, a test set for detection only is generated. Provided there is no fault detected by the first step, the second step is not required for diagnosis. The first step consists of a Counting sequence; if faults are detected by analyzing the responses, it is then possible to identify a set of test vectors which have produced the faulty responses. In the second step, the procedure applies a walking-one test to diagnose the faults in nets which are involved in confounding and aliasing syndromes. This approach is commonly referred to as C-test [8]. Ref. [-10] has considered the restricted, yet realistic scenario in which two nets can be shorted only if they terminate at adjacent pins or their tracks are adjacent within a predetermined tolerance. This is referred to as the adjacency fault model. A net connection graph is proposed as basic data structure in the diagnosis process. The diagnosis of the nets is shown to be equivalent to the coloring problem and a solution based on coloring is proposed. Since it is well known that the coloring problem is an NP-complete problem, some heuristic criteria are used in Ref. [-10] to shorten the length of the STVs. This solution consists of generating primary test vectors as corresponding to the original nets and then generating further tests by triangularization. However, the pin adjacency approach requires a larger than expected number of vectors due to the large number of adjacencies between nets created by a layout such as in 2-channel routing. This approach has the drawback of generating a large number of vectors if each net has a large number of possible primary sequential nets in the net connection graph as well as confounding and aliasing (this will be proved in Section 6).
3. Preliminaries This section will first introduce the basic definitions and notation.
1. Adjacency graph: This graph is given by
Gad = (V, E), where each vertex in the set V identifies
a net (i.e. I V I = n) and an edge eij e E if a short may exist between ni and n~ as they are adjacent in the layout of the interconnect (given by the graph G). 2. Sequential test vector (STV): The binary string, as test data applied to a specific net of the interconnect in the diagnosis process. 3. Parallel test vector (PTV): The test data applied to all nets in parallel in a round of the diagnosis process. PTV~ denotes the PTV for net n~ whose only 1-entry is at position i (all other entries are 0).
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As fault model, a strictly physical characterization consisting of short faults, is used. Shorts are tested by loading to adjacent nets test vectors whose values are logically opposite [4]. If the bridge fault is of the AND (OR) type, then the outcomes from the affected nets should all be 0 (1). Stuck-at faults in a net are commonly tested by loading vectors with both logic values and are easy to diagnose. The traditional short fault model assumes that it is possible for any net to be shorted to any other net in the interconnect. This model is based on extending the adjacency fault model and adding a further restriction. This restriction is as follows: since most short faults are caused by excessive metal between the nets or by failure to remove metal between tracks, then it is much unlikely that a fault will affect two non adjacent nets without affecting the nets in between. Therefore, the short model assumption that each net can be shorted to any other net (even if the two nets are not adjacent on a plane) is very improbable in a practical context [1]. Hence, in the paper the following are assumed.
1. Adjacency assumption: Any short fault may happen between two nets only if these two nets are physically adjacent in the plane. 2. Continuous assumption: Given two non-adjacent nets n~, nj and a subset of nets (denoted by B) between n~ and n~ on a plane, if n~ and nj are shorted, then all nets in B between them are also shorted together. Hereafter, the following assumptions are valid in the analysis. 1. The adjacency and continuous assumptions are applicable to faults in the nets. The OR short is assumed for simplicity. Note that even though stuck-at faults are not dealt explicitly in this paper, the proposed approaches fully diagnoses them. 2. Probing is only allowed at the input and output pins of each net. 3. A fault must be located at relative ease such that repair or rework can take place [2, 5-], i.e. no aliasing or confounding must exist.
4. Basic outline of the proposed approach. The basic principles of the proposed approach are as follows: For test generation, as shorts can only occur between adjacent nets within the limitations of the assumed fault model, then the number of tests generated by the walking-1 approach can be reduced by exploiting the net adjacency relationships in the layout. As each n~ has a set of neighbors in the layout and PTVi can be obtained using the walking-1 approach of Ref. [7], then it is possible to establish if n~ is shorted to another net nj(j v~ i) by using only a subset of test vectors already generated from Ref. [7]. This is accomplished by looking at the observed output responses of the neighbors of ni without necessarily using PTV~ in the new test set, i.e. if this condition is valid, then PTV~ is said to be redundant. Consider, for example, the interconnect shown in Fig. 1; Table 2 shows the test vectors for the walking-1 approach of Ref. [7] using the adjacency graph of Fig. 2. Assume that PTV1 and PTVz are available. Using PTV1, we can establish if nl is shorted to n2 (denoted as n~,~n2), nl~--~n3 and nl~--~n4. Equivalently using PTVz, we can establish if n2~--~n3and
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n4
n2 1 n3 Fig. 1. Interconnect graph G. Table 2 Net (STV)
PTV1
PTV2
PTV 3
PTV4
nl (STV1) n2 (STV2) n 3 (STV3) n4 (STV4)
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
n4 nl n3
Fig. 2. Adjacency graph Gad.
nl~--.n 2. As all possible shorts are identified by PTVI and PTV2, then PTV3 and PTV4 are redundant. In this case, the length of the sequence (given by the length of the S T V ) is 2. For compaction, the test vectors generated using the adjacency relationship have numerous do
not care and 0 entries. Therefore, compaction can be employed to reduce their number, i.e. to reduce the length of the STV. This is only one aspect of compaction; a further novel aspect introduced in this paper, is given by the outcome in merging two PTVs, say PTVi and PTVj as basic step of compaction. Hence, entries of the compacted PTV are classified according to a four-value logic system (not three as in Ref. [15]): 0, 1, x (do not care) and y, where y means that the two PTVs have failed to merge, so the compacted PTV can be disregarded. The use of a fourth-logic value implies that for a failed merging step between the two test vectors, then there is no need (as in Ref. [15]) to complement the values of all entries in the vector PTV~ to account for the logic variables and then try to merge this complemented vector with the vector PTVI. Table 3 shows the new characteristics of the proposed compaction operation, where PTV k denotes the k th entry in PTV~ and PTVij is the PTV generated by compacting PTV~ with PTV~. Note that if the compacted vector has at least a y entry, then this PTV is not retained in the test set as compaction has failed.
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Table 3
PTV,
PTV
PTV,
0 0 0 1 1 1 x x
0 1 x 0 1 x 0 1
0 y 0 y 1 1 0 1
X
X
X
Therefore, the proposed approach initially utilizes the principles of the walking-1 test set together with the adjacency and continuous assumptions to construct a test set of smaller cardinality by taking into account the layout. This set is further reduced by compaction. Compaction is achieved through heuristic criteria, namely a greedy condition in the adjacency graph. As diagnosis can be thought as a covering process in which each adjacency in Gad (i.e. an edge) is uniquely covered by at least one test vector, then it is important to recognize the conditions by which shorts can occur and be diagnosed. Hereafter, the word "covering" will be used in the context of diagnosing a possible short fault, i.e. to establish the status (fault-free or faulty) of an edge in Gad. Interconnects can be tested using different approaches [3, 6-9, 15-1 which can also be distinguished according to the policy employed in the diagnosis process. Two types of diagnosis can be distinguished.
1. Adaptive diagnosis: Test vectors are generated on-line as a function of observed output responses and previous test vectors. This implies that the cardinality of the test set is a function of the scheduling of the tests as well as the location and nature of the faults in the interconnect. This may take several steps I-8]. The main advantage of this type of diagnosis is that the number of required tests can be smaller than in the static case; however, on-line computation is required and compaction may be difficult. Also, the dependency on the number of faults in the interconnect necessitates that detection and location must be handled separately. 2. Static diagnosis: Test vectors are generated and compacted a priori, i.e. off-line; this type of approach has the advantage that tests can be stored in dictionaries once they have been generated as the number of vectors is fixed for a given interconnect. The main disadvantage is that all tests must be applied for diagnosis, independently of the faults in the interconnect (as observed in the output response vectors). Also, test generation can be very time consuming if the overall number of test vector must be minimized. In the next sections, approaches for one-step and two-step diagnosis are proposed and analyzed. The one-step approach is purely static as testing is performed off-line; this may result in a potential long test generation time. However, as this process is executed once for a given interconnect, the feature of a fixed number of tests (irrespective of the number of faults present in the interconnect) may outweigh the overhead in test generation as an overall simplicity can be achieved in the diagnosis process. The proposed two-step approach represents a compromise between a static
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approach and a fully adaptive approach. Two-step diagnosis can significantly reduce testing time as detection and location are handled in a different manner as in an adaptive approach. Its disadvantage is that an interconnect must be tested twice if multiple faults exist and aliasing and/or confounding have occurred. For relatively small interconnects, simulation results will show that one-step diagnosis is better; for larger interconnects, the flexibility of a two-step diagnosis may offer a considerable advantage.
5. One-step diagnosis The first algorithm implements static diagnosis in a one-step process. One-step diagnosis is executed off-line and for a given interconnect, it requires a test set whose cardinality does not depend on the number of faults. This is achieved by finding vectors which do not yield aliasing and confounding in the presence of faults, thus test generation can be complex. In the proposed approach, the static condition is based on analyzing the adjacency graph as well as the relation between neighboring nets within a one-step process. In particular, the existence of disjoint components in Gad is exploited to generate independent tests prior to compaction. This property of Gad is used for generalizing the diagnosis to all types (either dense or sparse) of layout. This algorithm improves over the pin adjacency approach of Ref. [10] by diagnosing an interconnect without aliasing and confounding. However, prior to presenting the algorithm, it will be shown that the static algorithm of Ref. [10] yields aliasing and confounding. This will be shown through an example; consider the adjacency graph shown in Fig. 3. Table 4 shows the PTVs generated using the algorithm of Ref. [10] with initial assignment at n4. Note that in Table 4 the condition given in Ref. [10] that every net and the so-called primary and secondary nets must have different STVs, is met. Assume that n2 and na as well as n3 and n4 are shorted. Then, in this case it is not possible to establish if there is a short between nl and n2. This results in aliasing. The same example also yields confounding. 111
110
100
001
010
111
110
nl
n2
n3
n4
n5
n6
n7
Fig. 3. Adjacency graph. Table 4 Net (STV)
PTV1
PTV2
PTV3
nl (STV1) n2 (STV2) n3 (STV3) n, (STV,) n5 (STVs) /I6 (STV6) n7 (STVv)
1 1 1 0 0 1 1
1 1 0 0 1 1 1
1 0 0 1 0 1 0
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The first algorithm for diagnosis is given as follows.
Algorithm 1: One-step diagnosis Step 1: Generate from G the adjacency list and find (if any) the (disjoint) graph components of Gad. Step 2: For each connected graph component of Gad While the graph component has at least an edge (a) find the vertex (i.e. the net) with maximum degree; this is the current net; (b) generate a new vector as follows: initialize the vector with x as every entry; place a 1 to the entry corresponding to the current net; place a 0 for the entry of each net connected to the current net in the graph component; (c) delete all edges connected to the current net; endwhile end For Step 3: Compact the test vectors using the basic operation of Table 3. The computational complexity of Algorithm 1 can be calculated as follows: 1. Step 1 is O(n2). 2. Let Ni be the number of nets in the ith graph component. Then, substep (a) requires N 2 operations, substeps (b) and (c) require at most N 2 operations, respectively. Hence, Step 2 is O(SN~) = O(n2). 3. Step 3 is O(n). Hence, Algorithm 1 is O(n2). The following theorem establishes the absence of aliasing and confounding in the test set generated by Algorithm 1.
Theorem 1. There is no aliasing and confounding in the diagnosis using the test set generated by Algorithm 1.
Proof. The proof consists of two parts, by considering the test set before and after compaction. (A) Uncompacted test set: Consider the edge eij in Gad, i.e. the edge between nl and n~. This edge is covered by the PTV which has a 1 in the entry corresponding to n~ (or nj) and 0 for n~(ni); also, all other nets connected to ni (and nj) have their entries given as 0. This PTV is initially given by PTVi (PTV~). Its output response vector is such that the bit corresponding to n~(ni) will be 1 too if and only if n~ and nj are shorted among all nets currently connected to n~ (and nj). This implies that the edge e~j is covered uniquely by PTVi, hence no aliasing and confounding arises. (B) Compacted test set: The vector PTV~ (as defined before) may be merged with other vectors which are generated for other nets in different components of Gaa. Suppose PTV~ and another PTV (say PTV~) are merged to form the vector PTV~, where PTV~ is the PTV for net n~ (i.e. the entry corresponding to n~ is 1 in PTV~). As these nets are connected, then the entry in the output response vector of PTV~ for nj can be 1 due to an indirect short with either n~ or nj. In this case, there must
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be another net (denoted by n~) along the path from n, to nj such that its PTV (denoted as PTVp) has the entry corresponding to np equal to 1, while the entries corresponding to ni, nj and n, are all 0. Note however, that such a path is not connected while PTVi and PTV, are constructed independently of PTVo. Using PTVp, it is possible to find whether nj is shorted to n, (inclusive of all nets between them) as this path must exist. Moreover, it is already known if ni and nj are shorted (provided nj is shorted to n, too). If the entry corresponding to nj is not 1 from n, in PTVp and the entry corresponding to nj is 1 in PTV~,, then the entry corresponding to nj is 1 from a short with ni, i.e. the merging of PTV~ and PTV, as PTV~ does not result in aliasing and confounding. []
6. Two-step diagnosis The second approach proposed in this paper utilizes a different condition in the test generation process. The proposed algorithm for fault diagnosis is based on a two-step process, namely detection and location. Two-step diagnosis represents a compromise between a static approach and a fully adaptive approach. As diagnosis is performed on-line (as in the adaptive case), testing is dependent on the number of faults in the interconnect as well as to their confounding/aliasing characteristics, hence its flexibility and dependency on the fault pattern. In particular, this flexibility of a two-step diagnosis process makes it particularly suitable for large interconnects in which a static approach to test generation may be not very efficient if all possible fault cases must be considered. The proposed two-step approach can be described as follows. First, Algorithm 2 below detects the presence of faults as well as establishing if each individual net is either fault-free or faulty. In the second step, a modified version of Algorithm 1 is used. This algorithm (referred to as Algorithm 1A differs from Algorithm 1 in Step 1 as follows. Step 1: Delete all fault free edges from Gad and find (if any) the disjoint graph components of the new Gad" This condition is required due to the refinement nature of the two-step process to account for nets already diagnosed in the previous step. The algorithm for the first step in the two step diagnosis is as follows.
Algorithm 2: Detection Step 1: Generate from G the adjacency list. Step 2: For each net with degree greater than 0 generate a vector for the selected net as follows: (a) initialize the vector with x in every entry; (b) place a 1 to the entry corresponding to the selected net; (c) place a 0 to every entry for each net connected to the selected net; Step 3: Compact the test vectors using the basic operation of Table 3. The computational complexity of this algorithm is O(n2). The following theorem proves the correctness of Algorithm 2.
Theorem 2. All faulty nets can be detected by the test set 9enerated by Algorithm 2.
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Table 5 Net
PTVi
PTVj
tli
1
0
nj
0
1
Proof. The proof will follow the same process as for Theorem 1. (A) Uncompacted test set: By Step 2, any edge eij between nets ni and n~ in Ga~ is covered by the corresponding PTVs, PTVI and PTV~ whose entries are defined as in Table 5. If % is shorted, then by applying PTVI (PTVj) it is possible to establish if nj (ni) is faulty, i.e. if eli is shorted then the two nets are both faulty. (B) Compacted test set: As compaction does not change the values of 0 and 1, then the compacted vector still has the same characteristics of the two original vectors. Hence, the theorem is proved. []
7. Fault location An integral feature of diagnosis is the process of fault location. If the test set has undergone compaction, fault location may not be obvious such that in the worst case, an incorrect location can be found for a fault, thus resulting in a wasteful rework and repair [2]. While in the walking-1 approach only one entry in every PTV is 1, after compaction a compacted vector generated by either of the two proposed approaches, may have more than one 1 entries. This means that the output response vector must establish the location of the fault(s) by discriminating the 1 entries in the PTV as well as effects of shorts as possible through the adjacencies in the layout. This process is equivalent to finding a consistent labeling of the edges in Gad using the outcomes in the output response vectors for a given set of PTVs. The algorithm for fault location using a given set of PTVs is as follows.
Algorithm 3: Fault location Step 1: Label all edges in the graph Gad as faulty. Step 2: For each output response vector PTV' For each net ni with a 1 in PTV' For each neighboring net nj of ni with a 0 in PTV' label the edge eij (between ni and nj) as fault free; delete the edge eij from Gad Step 3: Report all edges left in the new Gad.
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The computational complexity of Algorithm 3 is calculated as follows with respect to each of its steps. 1. Step 1 is O (lED. 2. This step is O(number of fault free edges). 3. Step 3 is O(number of faulty edges). Hence the complexity of Algorithm 3 is O(IE[), i.e. O(n 2) . The correctness of the algorithm is given by the following theorem. Theorem 3. Algorithm 3 is correct, i.e. it correctly locates the faults in an interconnect. Proof. Let PTV' be the output response vector for a PTV. As in the proof of Theorem 1, let the edge eij be covered by PTVi such that the entry corresponding to ni (nj) is 1 (0). Three cases can be distinguished: 1. ei~ corresponds to a short, then in the output response vector the jth entry is 1, keep eij as faulty and no other test vector can diagnose this edge as fault free, since the ith andjth entries must be either both 1 or both 0. 2. eij is not shorted, the jth entry in PTV[ is 0. This edge is fault free. 3. eij is not shorted, but the jth entry of PTVf is 1. This edge will be still considered as faulty when PTVi' is analyzed. Using the proof of Theorem 1, there exists a PTV given by PTVa and a corresponding output response vector PTVa' in which the jth (ith) entry is 1 (0). Then, eii is fault free. The status of all edges is therefore correct, which proves the correctness of the algorithm.
[]
8. A detailed example Consider the interconnect shown in Fig. 4. Fig. 5 shows the Gad of the interconnect of Fig. 4. Table 6 shows the test set prior to compaction using Algorithm 1 in a one-step diagnosis process; compaction in Step 3 does not reduce the number of tests. nl 112 n3 - n4 n5
n6
rlrl
1
I .....
n7 Fig. 4. Interconnect graph.
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nl
(
n4
n5
n6 Fig. 5. Adjacency graph.
Table 6 STV1
STV2
STV3
STV,
STV5
STV6
STV7
0 0 0 x
0 1 x x
1 x x x
0 0 1 x
0 0 0 0
0 0 0 1
0 0 0 0
STV1
STV 2
STV 3
STV4
STV5
STV6
STV7
1
0
x
0
x
x
x
0 x 0 x x x
1 0 0 x 0 x
0 1 0 0 0 0
0 0 1 0 x x
x 0 0 1 0 x
0 0 x 0 1 0
x 0 x x 0 1
Table 7
The execution of the first two steps of Algorithm 2 results in a test set made of seven vectors as shown in Table 7. Compaction can reduce the cardinality of the test set to three, as shown in Table 8. Consider now a two-step diagnosis in which Algorithm 2 is first used (just for detection) followed by Algorithm 1A (for full diagnosis). In this case, assume that n2, n3, n5 and n6 are faulty. Then, the test vectors for the second step in the diagnosis process are given in Table 9. Consider next fault location. Assume that n2 and n 3 (n5 and n6) a r e shorted together. Using the tests for one-step diagnosis of Table 8, the output response vectors shown in Table 10 are obtained. These locate the shorts between n5 and n 6 and identify that n2 and na are faulty. Using the two-step diagnosis tests of Table 9, the output response vectors are given in Table 11.
194
T. Liu, F. Lombardi/INTEGRATION, the VLSI Journal 19 (1995) 181-198 Table 8 STV1
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T. Liu, F. Lombardi/INTEGRATION, the VLSI Journal 19 (1995) 181-198
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Prior to fault location, nl, n4 and n 7 are detected as fault free. The G~d is reduced to the graph of Fig. 6. Using Algorithm 3 and the test outcomes from the two-step diagnosis, the edges e26, e36 and e35 can be deleted from this graph. Hence, the shorts are n2(--~na and ns<--+n6.
9. Simulation results
The algorithms presented in the previous sections have been evaluated by simulation on three benchmarks as well as random interconnects. Table 12 shows a comparison between the previous Table 12 Benchmark
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approaches and the proposed algorithm (i.e. Algorithm 2) for detection only for three benchmark layouts. Note that [9, 10, 12] do not yield a full diagnosis as confounding and/or aliasing may exist. Note that the average number of tests required for random interconnects with 100, 200 and 500 nets using the proposed approach is 6, 6 and 8, respectively. Let f be the probability that two nets adjacent in the interconnect are faulty through a short. Fig. 7 shows the simulation results for diagnosis using a two-step process, i.e. the proposed approach (Algorithm 2 is first executed for detection followed by Algorithm 1A for full diagnosis) is compared with the C-test approach of Ref. [8] for the three benchmarks (note that the other adaptive algorithm of [-3] is already optimized by the C-test). Fig. 8 shows the simulation results for number of tests versus f in random interconnects for n = 100, 200 and 500. Figure 9 shows the anumber of tests for large random interconnects (n = 1000, 5000 and 10000) for only smaller values o f f The following quantitative conclusions can be drawn from the simulation results. 1. The reduction in number of tests is significant in both the one-step and two-step cases compared to other approaches with no aliasing and confounding, i.e. Ref. [7] only. In the two-step case, at least 300
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a 50% reduction in number of diagnostic tests compared to Ref. [81 is achieved for the simulated benchmarks. In the one-step case, Algorithm 2 achieves a 35% reduction compared to Ref. [6]. 2. In the two-step case, the proposed approach requires a smaller number of tests than the C-test approach of Ref. [8] irrespective o f f 3. The number of tests using the proposed two-step process still shows a direct dependency with f f o r diagnosis.
10. Conclusions This paper has presented a new approach for diagnosing shorts in interconnects. The proposed approach exploits new conditions in test generation and compaction. For test generation, two algorithms with an execution complexity of O(n 2) are proposed; the first algorithm is applicable to one-step diagnosis while the second algorithm is applicable to two-step diagnosis. These algorithms are based on an adjacency analysis of the layout such that the test outcomes yield full
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detection and location. Correctness of the proposed algorithms is proved prior and after test compaction such that aliasing and confounding are avoided. Simulation has shown that for two-step diagnosis, the number of tests required is a function (direct proportionality) of the number of shorts in the interconnect; however, simulation results show that their number is less than previous approaches I-6-8, 10]. A further significant feature of this paper is that the two proposed diagnosis algorithms (one-step and two-step) can be used interchangeably depending on the testing requirements: if off-line testing is required, the one-step strategy is superior as the number of tests to be stored is constant for a given interconnect. If the chosen figure of merit is testing time, then two-step diagnosis may offer considerable advantages over a one-step approach because it allows a flexible execution of the diagnosis process in which detection and location are dealt separately and therefore, a lower number of tests (provided the number of faults is not very large). The advantage of a two-step diagnosis is more pronounced for larger interconnects.
References I-1] [2] [3] [4]
H.B. Bakoglu, Circuits lnterconnections and Packa#ingfor VLSI (Addison-Wesley, Reading, MA, 1989). R.R. Tummala, Multic.hip packaging, a tutorial, Proc. IEEE 80 (12) (1992) 1924-1941. P. Goel and M.T. McMahon, Electronic chip-in-place test, Int. Test Conf. (1982) pp. 83-90. M. Melton and F. Breglez, Automatic pattern generation for diagnosis of wiring interconnect faults, Int. Test Conf. (1992) pp. 389-398. [5] J.K. Hagge and R.J. Wagner, High-yield assembly of multichip modules through known-good IC's and effective test strategies, Proc. IEEE 811 (12) (1992) 1965-1994. [6] W.-T. Cheng, J.L. Lewandowski and E. Wu, Diagnosis for wiring interconnects, Int. Test Conf. (1990) pp. 565-571. [7] A. Hassan, J. Rajski and V.K. Agrawal, Testing and diagnosis of interconnects using boundary-scan, Int. Test Conf. (1985) pp. 126-137. [8] N. Jarwala and C.W. Yau, A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects, Int. Test Conf. (1989) pp. 63-70. [9] W.H. Kautz, Testing for fault in wiring networks, IEEE Trans. Comput. C-23 (4) (1974) 358-363. [10] D. McBean and W.R. Moore, Testing interconnects: a pin adjacency approach, 1EEE European Test Conf. (1993) pp. 484-490. I-11] S.Z. Yao, N.C. Chou, CK. Cheng and T.C. Hu, A multi-probe approach for MCM substrate testing, IEEE Trans. CAD ICAS CAD13 (1) (1994) 110-121. [12] P.T. Wagner, Interconnect testing with boundary scan, Int. Test Conf. (1987) pp. 52-57. [13] C.W. Yau and N. Jarwala, A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects, Int. Test Conf. (1989) pp. 71-77. [14] J. Gailaiy, Y. Crouzet and M. Vergniault, Physical versus logic faults, impact on their testability, IEEE Trans. Comput. C-20 (6)(r980) 527-531. [15] J. Salinas, Y.N. Shen and F. Lombardi, Interconnect testing by line sweeping, Internal Report, Texas A&M University, Department of Computer Science, 1994. [16] M.R. Garey and. D.S. Johnson, Computer and Intractability, A Guide to the Theory of NP-Completeness (W.H. Freeman, San Fransisco, 1979). [17] F.P. Preparata and M.I. Shamos, Computational Geometry: An Introduction (Springer, New York, 1985).
INTEGRATION, the VLSI Journal 19 (1995) 181 198
Diagnosis of interconnects using a structured walking-1 approach" T. Liu, F. Lombardi* Department of Computer Science, Texas A&M University, College Station, TX 77843, USA Received 12 August 1994; revised 4 May 1995
Abstract This paper presents a new approach for testing interconnects for boundary scan architectures. This approach relies on a structured walking-I test set in the sense that a structural analysis based on the layout of the interconnect, is carried out. The proposed structural test method differs from previous approaches as it explicitly avoids aliasing and confounding and is applicable to dense as well as sparse interconnect layouts. The proposed method is applicable to both one-step and two-step test generation and diagnosis of stuck-at as well as bridge faults. Two algorithms with an execution complexity of O(n2), where n is the number of nets in the interconnect, are given. New criteria for test vector compaction are proposed; a greedy condition is exploited to compact test vectors for one-step and two-step diagnosis. For a given interconnect, the two-step diagnosis algorithm requires a number of tests as a function of the number of faults present, while the one-step algorithm requires a fixed number of tests. Simulation results for benchmark and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches compared with previous approaches. It is also shown that the proposed algorithms can be used interchangeably depending on the requirements of the overall test process (such as off/on-line execution as well as reduction in number of vectors and test generation time).
Keywords: Interconnect testing; Diagnosis; Syndrome; Boundary scan
1. Introduction
The miniaturization of digital circuits and today's technologies (such as MCM and WSI) have made possible the manufacturing of high-density layouts and boards [1, 2]. Costs for manufacturing as well as tailoring a general architecture to particular applications for full customization have however increased. The high density and complexity of these systems require that testing and diagnosis must be efficiently implemented to diagnose the occurrence of faults due to either a short or open in nets which are closely adjacent as well as stuck-at faults. At the same time, due to the use of surface-mount technology (SMT) as well as MCMs, a traditional testing technique (such as a bed-of-nails approach) is not very efficient. The standardization by the IEEE of the Boundary This research was supported by grants from the Texas ATP and the Ministry of Education and Science of Japan. * Corresponding author. E-mail: [email protected]. Tel. (409) 845-5464. 0167-9260/95/$9.50 © 1995
Elsevier Science B.V. All rights reserved.
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Scan Architecture has simplified testing of this type of systems (from applying and loading test vectors to collecting test outcomes) [3]. If all components on a board support the boundary-scan feature, short, open and stuck-at .faults of all nets in the interconnect can be tested by executing the E X T E S T instruction [4]. Only those components which are usually relatively simple combinational circuits and are considered easy to test, do not support on the board the boundary-scan standard. Diagnosis consists of both fault detection and location and is important because after testing it permits an efficient repair of boards, thus increasing the manufacturing throughput and decreasing costs [5-1. Considerable research has been pursued to fully diagnose interconnects as part of a boundary scan architecture; examples of this type of approaches can be found in [6-10]. The interconnect system is usually analyzed as a set of nets which can be affected by different types of faults, such as stuck-at, short and open [-6,9, 10-]. Diagnosis is usually accomplished by comparing the signatures received at the output pins with the ones provided at the inputs, i.e. no internal probing is permitted in the system. Examples of techniques which utilize probing, can be found in Ref. [ 11] as applicable to substrate testing. For interconnect testing, research has been pursued on shorts (bridge faults) as they are the most likely and more difficult faults to diagnose [1]. Bridging faults can be tested by using either a behavioral testing or a structural testing strategy. Several papers [9, 12] have discussed behavioral testing. In structural testing, the wiring layout of the given network must be specified. As automatic routing systems are often employed for checking layouts, the structure of the nets (such as their positions and connections) is known; therefore, the viability of structural testing of an interconnect is possible and realistic [13]. The objective of this paper is to propose a new approach for testing interconnects in a boundary scan architecture. This approach relies on a structured walking-1 test set in the sense that a structural analysis based on the layout of the interconnect, is carried out. Our structural test method differs from the approach of Ref. [10] as it explicitly avoids aliasing and confounding. The proposed method is applicable to both one-step and two-step diagnosis by considering the testing complexity (as measured by the number of tests and the test generation time) as well as the nature of the testing process itself (either on-line or off-line). Simulation results show that for relatively smaller interconnects, one-step diagnosis is more suitable than two-step diagnosis as the number of tests can be generated and reduced using the propo~..ed structured walking-1 method with relative ease. For large (and hence complex) interconnects, two-step diagnosis is superior due to its flexibility in handling the fault detection and location processes separately. Table 1 summarizes the characteristics of previous and proposed approaches. New criteria for test vector compaction are ,dso proposed; simulation results for benchmark layouts and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches. This paper is organized as follows. Section 2 introduces a brief review of previous methods. Section 3 deals with preliminaries as well as notation. The basic criteria for the proposed method are described in Section 4. Section 5 presents the proposed approach to one-step diagnosis, while Section 6 deals with two-step diagnosis. The process of fault location is analyzed in Section 7. A detailed example and the applicability and execution of the proposed approaches are given in Section 8. Section 9 presents simulation results and a comparative analysis with previous approaches for benchmark layouts as well as random interconnects. In Section 10, conclusions and final remarks are provided.
T. Liu, F. Lombardi/INTEGRATION, the VLS1Journal 19 (1995) 181-198
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Table 1 Approach
Aliasing/confounding
Diagnosis
Comments
Kautz 1-9] Wagner [12] Self-diagnosis [6] Walking- 1 [7] Goel [3]
Yes/Yes No/Yes No/Yes No/No No/No
No Partial Partial Yes Yes
McBean and Moore [10] C-Test [8]
Yes/Yes No/No
Partial Yes
Max-independence [8]
No/No
Yes
Proposed approaches
No/No
Yes
Short sequence Simple test generation Simple diagnosis Very long sequence Sequence length depends on number of faults Long sequence Sequence length depends on number of faults Very difficult ordering; limited practicality Very short sequence Sequence length depends on number of faults
2. Review In this section, a brief review of behavioral and structural testing approaches to interconnects will be presented. The faults in interconnects can be tested by using either a behavioral testing or a structural testing strategy. Several papers [6, 13, 8] have discussed behavioral testing. In structural testing, the wiring layout of the given network must be specified. Structural testing is possible through the knowledge of the layout [14]. In behavioral testing, it is commonly postulated that every net on the board can be shorted to any other net. The Counting Sequence Algorithm of [9] can be used to detect all short faults with a test length (usually referred to as the length of the sequential test vectors (ST V)) of [-log2 n 7, where n is the number of nets in the interconnect. If the test vectors must be applied through a boundary scan chain, the test time will be n [-logzn]. If both the STVs consisting of all 0 and all 1 are included, then a modified counting sequence [3] is obtained. These test vectors permit to diagnose stuck-at faults too. The sequential response vector (SR V) of a net to a STV is then used to detect and/or diagnosis shorts between nets. If the SRV of a net differs from its STV, then this vector is referred to as a fault syndrome. It has been shown in Ref. [8] that the counting sequence cannot diagnose all short faults. If a syndrome in the presence of a fault is the same as the fault-free response of a net, then it is impossible to determine whether or not this net is also a part of the short. The response in this case is referred to as an aliasing syndrome. Similarly, a short between a pair of nets may produce the same syndrome as between another net pair; it is impossible to determine whether or not there is a short between which pair of nets. The response is called a confounding syndrome. Ref. [12] has added test vectors with complement values to the counting sequence such that it is possible to diagnose shorts with unique syndromes (i.e. no aliasing syndromes occur). However, confounding may still occur. Using this approach the test length is 2Flog2(n + 1)7, if vectors with all 0 and all 1 are allowed. The walking-1 test set proposed by Ref. [7] can avoid the aliasing and confounding problems, i.e. it can be used to diagnose all shorts in the nets. The drawback of this method however is that large
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test sets generated as a sequence of length n is required. This is especially severe if a boundary-scan method is employed, in which a sequence of length n requires n 2 testing time. The Max-Independence Algorithm of Ref. [8] generalizes the walking-1 method by defining a diagonally independent matrix; it has been proved in Ref. [13] that this type of test vector will not generate aliasing or confounding syndromes. The walking-1 test set satisfies the independence requirement. Also, if every faulty net has an erroneous output response sequence, then every faulty net can be identified by checking its output response sequence only. A testing process with this property is called self-diagnosing. This method proposed in Ref. [-6] generates all test sequences of length p with p/2 '0' bits, i.e. the STV is a p/2 out of p code. For the approach of Ref. [8], a two-step diagnosis process is applicable: in the first step, a test set for detection only is generated. Provided there is no fault detected by the first step, the second step is not required for diagnosis. The first step consists of a Counting sequence; if faults are detected by analyzing the responses, it is then possible to identify a set of test vectors which have produced the faulty responses. In the second step, the procedure applies a walking-one test to diagnose the faults in nets which are involved in confounding and aliasing syndromes. This approach is commonly referred to as C-test [8]. Ref. [-10] has considered the restricted, yet realistic scenario in which two nets can be shorted only if they terminate at adjacent pins or their tracks are adjacent within a predetermined tolerance. This is referred to as the adjacency fault model. A net connection graph is proposed as basic data structure in the diagnosis process. The diagnosis of the nets is shown to be equivalent to the coloring problem and a solution based on coloring is proposed. Since it is well known that the coloring problem is an NP-complete problem, some heuristic criteria are used in Ref. [-10] to shorten the length of the STVs. This solution consists of generating primary test vectors as corresponding to the original nets and then generating further tests by triangularization. However, the pin adjacency approach requires a larger than expected number of vectors due to the large number of adjacencies between nets created by a layout such as in 2-channel routing. This approach has the drawback of generating a large number of vectors if each net has a large number of possible primary sequential nets in the net connection graph as well as confounding and aliasing (this will be proved in Section 6).
3. Preliminaries This section will first introduce the basic definitions and notation.
1. Adjacency graph: This graph is given by
Gad = (V, E), where each vertex in the set V identifies
a net (i.e. I V I = n) and an edge eij e E if a short may exist between ni and n~ as they are adjacent in the layout of the interconnect (given by the graph G). 2. Sequential test vector (STV): The binary string, as test data applied to a specific net of the interconnect in the diagnosis process. 3. Parallel test vector (PTV): The test data applied to all nets in parallel in a round of the diagnosis process. PTV~ denotes the PTV for net n~ whose only 1-entry is at position i (all other entries are 0).
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185
As fault model, a strictly physical characterization consisting of short faults, is used. Shorts are tested by loading to adjacent nets test vectors whose values are logically opposite [4]. If the bridge fault is of the AND (OR) type, then the outcomes from the affected nets should all be 0 (1). Stuck-at faults in a net are commonly tested by loading vectors with both logic values and are easy to diagnose. The traditional short fault model assumes that it is possible for any net to be shorted to any other net in the interconnect. This model is based on extending the adjacency fault model and adding a further restriction. This restriction is as follows: since most short faults are caused by excessive metal between the nets or by failure to remove metal between tracks, then it is much unlikely that a fault will affect two non adjacent nets without affecting the nets in between. Therefore, the short model assumption that each net can be shorted to any other net (even if the two nets are not adjacent on a plane) is very improbable in a practical context [1]. Hence, in the paper the following are assumed.
1. Adjacency assumption: Any short fault may happen between two nets only if these two nets are physically adjacent in the plane. 2. Continuous assumption: Given two non-adjacent nets n~, nj and a subset of nets (denoted by B) between n~ and n~ on a plane, if n~ and nj are shorted, then all nets in B between them are also shorted together. Hereafter, the following assumptions are valid in the analysis. 1. The adjacency and continuous assumptions are applicable to faults in the nets. The OR short is assumed for simplicity. Note that even though stuck-at faults are not dealt explicitly in this paper, the proposed approaches fully diagnoses them. 2. Probing is only allowed at the input and output pins of each net. 3. A fault must be located at relative ease such that repair or rework can take place [2, 5-], i.e. no aliasing or confounding must exist.
4. Basic outline of the proposed approach. The basic principles of the proposed approach are as follows: For test generation, as shorts can only occur between adjacent nets within the limitations of the assumed fault model, then the number of tests generated by the walking-1 approach can be reduced by exploiting the net adjacency relationships in the layout. As each n~ has a set of neighbors in the layout and PTVi can be obtained using the walking-1 approach of Ref. [7], then it is possible to establish if n~ is shorted to another net nj(j v~ i) by using only a subset of test vectors already generated from Ref. [7]. This is accomplished by looking at the observed output responses of the neighbors of ni without necessarily using PTV~ in the new test set, i.e. if this condition is valid, then PTV~ is said to be redundant. Consider, for example, the interconnect shown in Fig. 1; Table 2 shows the test vectors for the walking-1 approach of Ref. [7] using the adjacency graph of Fig. 2. Assume that PTV1 and PTVz are available. Using PTV1, we can establish if nl is shorted to n2 (denoted as n~,~n2), nl~--~n3 and nl~--~n4. Equivalently using PTVz, we can establish if n2~--~n3and
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n4
n2 1 n3 Fig. 1. Interconnect graph G. Table 2 Net (STV)
PTV1
PTV2
PTV 3
PTV4
nl (STV1) n2 (STV2) n 3 (STV3) n4 (STV4)
1 0 0 0
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nl~--.n 2. As all possible shorts are identified by PTVI and PTV2, then PTV3 and PTV4 are redundant. In this case, the length of the sequence (given by the length of the S T V ) is 2. For compaction, the test vectors generated using the adjacency relationship have numerous do
not care and 0 entries. Therefore, compaction can be employed to reduce their number, i.e. to reduce the length of the STV. This is only one aspect of compaction; a further novel aspect introduced in this paper, is given by the outcome in merging two PTVs, say PTVi and PTVj as basic step of compaction. Hence, entries of the compacted PTV are classified according to a four-value logic system (not three as in Ref. [15]): 0, 1, x (do not care) and y, where y means that the two PTVs have failed to merge, so the compacted PTV can be disregarded. The use of a fourth-logic value implies that for a failed merging step between the two test vectors, then there is no need (as in Ref. [15]) to complement the values of all entries in the vector PTV~ to account for the logic variables and then try to merge this complemented vector with the vector PTVI. Table 3 shows the new characteristics of the proposed compaction operation, where PTV k denotes the k th entry in PTV~ and PTVij is the PTV generated by compacting PTV~ with PTV~. Note that if the compacted vector has at least a y entry, then this PTV is not retained in the test set as compaction has failed.
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Table 3
PTV,
PTV
PTV,
0 0 0 1 1 1 x x
0 1 x 0 1 x 0 1
0 y 0 y 1 1 0 1
X
X
X
Therefore, the proposed approach initially utilizes the principles of the walking-1 test set together with the adjacency and continuous assumptions to construct a test set of smaller cardinality by taking into account the layout. This set is further reduced by compaction. Compaction is achieved through heuristic criteria, namely a greedy condition in the adjacency graph. As diagnosis can be thought as a covering process in which each adjacency in Gad (i.e. an edge) is uniquely covered by at least one test vector, then it is important to recognize the conditions by which shorts can occur and be diagnosed. Hereafter, the word "covering" will be used in the context of diagnosing a possible short fault, i.e. to establish the status (fault-free or faulty) of an edge in Gad. Interconnects can be tested using different approaches [3, 6-9, 15-1 which can also be distinguished according to the policy employed in the diagnosis process. Two types of diagnosis can be distinguished.
1. Adaptive diagnosis: Test vectors are generated on-line as a function of observed output responses and previous test vectors. This implies that the cardinality of the test set is a function of the scheduling of the tests as well as the location and nature of the faults in the interconnect. This may take several steps I-8]. The main advantage of this type of diagnosis is that the number of required tests can be smaller than in the static case; however, on-line computation is required and compaction may be difficult. Also, the dependency on the number of faults in the interconnect necessitates that detection and location must be handled separately. 2. Static diagnosis: Test vectors are generated and compacted a priori, i.e. off-line; this type of approach has the advantage that tests can be stored in dictionaries once they have been generated as the number of vectors is fixed for a given interconnect. The main disadvantage is that all tests must be applied for diagnosis, independently of the faults in the interconnect (as observed in the output response vectors). Also, test generation can be very time consuming if the overall number of test vector must be minimized. In the next sections, approaches for one-step and two-step diagnosis are proposed and analyzed. The one-step approach is purely static as testing is performed off-line; this may result in a potential long test generation time. However, as this process is executed once for a given interconnect, the feature of a fixed number of tests (irrespective of the number of faults present in the interconnect) may outweigh the overhead in test generation as an overall simplicity can be achieved in the diagnosis process. The proposed two-step approach represents a compromise between a static
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approach and a fully adaptive approach. Two-step diagnosis can significantly reduce testing time as detection and location are handled in a different manner as in an adaptive approach. Its disadvantage is that an interconnect must be tested twice if multiple faults exist and aliasing and/or confounding have occurred. For relatively small interconnects, simulation results will show that one-step diagnosis is better; for larger interconnects, the flexibility of a two-step diagnosis may offer a considerable advantage.
5. One-step diagnosis The first algorithm implements static diagnosis in a one-step process. One-step diagnosis is executed off-line and for a given interconnect, it requires a test set whose cardinality does not depend on the number of faults. This is achieved by finding vectors which do not yield aliasing and confounding in the presence of faults, thus test generation can be complex. In the proposed approach, the static condition is based on analyzing the adjacency graph as well as the relation between neighboring nets within a one-step process. In particular, the existence of disjoint components in Gad is exploited to generate independent tests prior to compaction. This property of Gad is used for generalizing the diagnosis to all types (either dense or sparse) of layout. This algorithm improves over the pin adjacency approach of Ref. [10] by diagnosing an interconnect without aliasing and confounding. However, prior to presenting the algorithm, it will be shown that the static algorithm of Ref. [10] yields aliasing and confounding. This will be shown through an example; consider the adjacency graph shown in Fig. 3. Table 4 shows the PTVs generated using the algorithm of Ref. [10] with initial assignment at n4. Note that in Table 4 the condition given in Ref. [10] that every net and the so-called primary and secondary nets must have different STVs, is met. Assume that n2 and na as well as n3 and n4 are shorted. Then, in this case it is not possible to establish if there is a short between nl and n2. This results in aliasing. The same example also yields confounding. 111
110
100
001
010
111
110
nl
n2
n3
n4
n5
n6
n7
Fig. 3. Adjacency graph. Table 4 Net (STV)
PTV1
PTV2
PTV3
nl (STV1) n2 (STV2) n3 (STV3) n, (STV,) n5 (STVs) /I6 (STV6) n7 (STVv)
1 1 1 0 0 1 1
1 1 0 0 1 1 1
1 0 0 1 0 1 0
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The first algorithm for diagnosis is given as follows.
Algorithm 1: One-step diagnosis Step 1: Generate from G the adjacency list and find (if any) the (disjoint) graph components of Gad. Step 2: For each connected graph component of Gad While the graph component has at least an edge (a) find the vertex (i.e. the net) with maximum degree; this is the current net; (b) generate a new vector as follows: initialize the vector with x as every entry; place a 1 to the entry corresponding to the current net; place a 0 for the entry of each net connected to the current net in the graph component; (c) delete all edges connected to the current net; endwhile end For Step 3: Compact the test vectors using the basic operation of Table 3. The computational complexity of Algorithm 1 can be calculated as follows: 1. Step 1 is O(n2). 2. Let Ni be the number of nets in the ith graph component. Then, substep (a) requires N 2 operations, substeps (b) and (c) require at most N 2 operations, respectively. Hence, Step 2 is O(SN~) = O(n2). 3. Step 3 is O(n). Hence, Algorithm 1 is O(n2). The following theorem establishes the absence of aliasing and confounding in the test set generated by Algorithm 1.
Theorem 1. There is no aliasing and confounding in the diagnosis using the test set generated by Algorithm 1.
Proof. The proof consists of two parts, by considering the test set before and after compaction. (A) Uncompacted test set: Consider the edge eij in Gad, i.e. the edge between nl and n~. This edge is covered by the PTV which has a 1 in the entry corresponding to n~ (or nj) and 0 for n~(ni); also, all other nets connected to ni (and nj) have their entries given as 0. This PTV is initially given by PTVi (PTV~). Its output response vector is such that the bit corresponding to n~(ni) will be 1 too if and only if n~ and nj are shorted among all nets currently connected to n~ (and nj). This implies that the edge e~j is covered uniquely by PTVi, hence no aliasing and confounding arises. (B) Compacted test set: The vector PTV~ (as defined before) may be merged with other vectors which are generated for other nets in different components of Gaa. Suppose PTV~ and another PTV (say PTV~) are merged to form the vector PTV~, where PTV~ is the PTV for net n~ (i.e. the entry corresponding to n~ is 1 in PTV~). As these nets are connected, then the entry in the output response vector of PTV~ for nj can be 1 due to an indirect short with either n~ or nj. In this case, there must
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be another net (denoted by n~) along the path from n, to nj such that its PTV (denoted as PTVp) has the entry corresponding to np equal to 1, while the entries corresponding to ni, nj and n, are all 0. Note however, that such a path is not connected while PTVi and PTV, are constructed independently of PTVo. Using PTVp, it is possible to find whether nj is shorted to n, (inclusive of all nets between them) as this path must exist. Moreover, it is already known if ni and nj are shorted (provided nj is shorted to n, too). If the entry corresponding to nj is not 1 from n, in PTVp and the entry corresponding to nj is 1 in PTV~,, then the entry corresponding to nj is 1 from a short with ni, i.e. the merging of PTV~ and PTV, as PTV~ does not result in aliasing and confounding. []
6. Two-step diagnosis The second approach proposed in this paper utilizes a different condition in the test generation process. The proposed algorithm for fault diagnosis is based on a two-step process, namely detection and location. Two-step diagnosis represents a compromise between a static approach and a fully adaptive approach. As diagnosis is performed on-line (as in the adaptive case), testing is dependent on the number of faults in the interconnect as well as to their confounding/aliasing characteristics, hence its flexibility and dependency on the fault pattern. In particular, this flexibility of a two-step diagnosis process makes it particularly suitable for large interconnects in which a static approach to test generation may be not very efficient if all possible fault cases must be considered. The proposed two-step approach can be described as follows. First, Algorithm 2 below detects the presence of faults as well as establishing if each individual net is either fault-free or faulty. In the second step, a modified version of Algorithm 1 is used. This algorithm (referred to as Algorithm 1A differs from Algorithm 1 in Step 1 as follows. Step 1: Delete all fault free edges from Gad and find (if any) the disjoint graph components of the new Gad" This condition is required due to the refinement nature of the two-step process to account for nets already diagnosed in the previous step. The algorithm for the first step in the two step diagnosis is as follows.
Algorithm 2: Detection Step 1: Generate from G the adjacency list. Step 2: For each net with degree greater than 0 generate a vector for the selected net as follows: (a) initialize the vector with x in every entry; (b) place a 1 to the entry corresponding to the selected net; (c) place a 0 to every entry for each net connected to the selected net; Step 3: Compact the test vectors using the basic operation of Table 3. The computational complexity of this algorithm is O(n2). The following theorem proves the correctness of Algorithm 2.
Theorem 2. All faulty nets can be detected by the test set 9enerated by Algorithm 2.
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Table 5 Net
PTVi
PTVj
tli
1
0
nj
0
1
Proof. The proof will follow the same process as for Theorem 1. (A) Uncompacted test set: By Step 2, any edge eij between nets ni and n~ in Ga~ is covered by the corresponding PTVs, PTVI and PTV~ whose entries are defined as in Table 5. If % is shorted, then by applying PTVI (PTVj) it is possible to establish if nj (ni) is faulty, i.e. if eli is shorted then the two nets are both faulty. (B) Compacted test set: As compaction does not change the values of 0 and 1, then the compacted vector still has the same characteristics of the two original vectors. Hence, the theorem is proved. []
7. Fault location An integral feature of diagnosis is the process of fault location. If the test set has undergone compaction, fault location may not be obvious such that in the worst case, an incorrect location can be found for a fault, thus resulting in a wasteful rework and repair [2]. While in the walking-1 approach only one entry in every PTV is 1, after compaction a compacted vector generated by either of the two proposed approaches, may have more than one 1 entries. This means that the output response vector must establish the location of the fault(s) by discriminating the 1 entries in the PTV as well as effects of shorts as possible through the adjacencies in the layout. This process is equivalent to finding a consistent labeling of the edges in Gad using the outcomes in the output response vectors for a given set of PTVs. The algorithm for fault location using a given set of PTVs is as follows.
Algorithm 3: Fault location Step 1: Label all edges in the graph Gad as faulty. Step 2: For each output response vector PTV' For each net ni with a 1 in PTV' For each neighboring net nj of ni with a 0 in PTV' label the edge eij (between ni and nj) as fault free; delete the edge eij from Gad Step 3: Report all edges left in the new Gad.
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The computational complexity of Algorithm 3 is calculated as follows with respect to each of its steps. 1. Step 1 is O (lED. 2. This step is O(number of fault free edges). 3. Step 3 is O(number of faulty edges). Hence the complexity of Algorithm 3 is O(IE[), i.e. O(n 2) . The correctness of the algorithm is given by the following theorem. Theorem 3. Algorithm 3 is correct, i.e. it correctly locates the faults in an interconnect. Proof. Let PTV' be the output response vector for a PTV. As in the proof of Theorem 1, let the edge eij be covered by PTVi such that the entry corresponding to ni (nj) is 1 (0). Three cases can be distinguished: 1. ei~ corresponds to a short, then in the output response vector the jth entry is 1, keep eij as faulty and no other test vector can diagnose this edge as fault free, since the ith andjth entries must be either both 1 or both 0. 2. eij is not shorted, the jth entry in PTV[ is 0. This edge is fault free. 3. eij is not shorted, but the jth entry of PTVf is 1. This edge will be still considered as faulty when PTVi' is analyzed. Using the proof of Theorem 1, there exists a PTV given by PTVa and a corresponding output response vector PTVa' in which the jth (ith) entry is 1 (0). Then, eii is fault free. The status of all edges is therefore correct, which proves the correctness of the algorithm.
[]
8. A detailed example Consider the interconnect shown in Fig. 4. Fig. 5 shows the Gad of the interconnect of Fig. 4. Table 6 shows the test set prior to compaction using Algorithm 1 in a one-step diagnosis process; compaction in Step 3 does not reduce the number of tests. nl 112 n3 - n4 n5
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T. Liu, F. Lombardi/INTEGRATION, the VLSI Journal 19 (1995) 181-198
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nl
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STV5
STV6
STV7
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Table 7
The execution of the first two steps of Algorithm 2 results in a test set made of seven vectors as shown in Table 7. Compaction can reduce the cardinality of the test set to three, as shown in Table 8. Consider now a two-step diagnosis in which Algorithm 2 is first used (just for detection) followed by Algorithm 1A (for full diagnosis). In this case, assume that n2, n3, n5 and n6 are faulty. Then, the test vectors for the second step in the diagnosis process are given in Table 9. Consider next fault location. Assume that n2 and n 3 (n5 and n6) a r e shorted together. Using the tests for one-step diagnosis of Table 8, the output response vectors shown in Table 10 are obtained. These locate the shorts between n5 and n 6 and identify that n2 and na are faulty. Using the two-step diagnosis tests of Table 9, the output response vectors are given in Table 11.
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STV,
STV5
STV6
STV7
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1 0 0
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x x
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1 0
0 0
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0 0
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T. Liu, F. Lombardi/INTEGRATION, the VLSI Journal 19 (1995) 181-198
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Prior to fault location, nl, n4 and n 7 are detected as fault free. The G~d is reduced to the graph of Fig. 6. Using Algorithm 3 and the test outcomes from the two-step diagnosis, the edges e26, e36 and e35 can be deleted from this graph. Hence, the shorts are n2(--~na and ns<--+n6.
9. Simulation results
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approaches and the proposed algorithm (i.e. Algorithm 2) for detection only for three benchmark layouts. Note that [9, 10, 12] do not yield a full diagnosis as confounding and/or aliasing may exist. Note that the average number of tests required for random interconnects with 100, 200 and 500 nets using the proposed approach is 6, 6 and 8, respectively. Let f be the probability that two nets adjacent in the interconnect are faulty through a short. Fig. 7 shows the simulation results for diagnosis using a two-step process, i.e. the proposed approach (Algorithm 2 is first executed for detection followed by Algorithm 1A for full diagnosis) is compared with the C-test approach of Ref. [8] for the three benchmarks (note that the other adaptive algorithm of [-3] is already optimized by the C-test). Fig. 8 shows the simulation results for number of tests versus f in random interconnects for n = 100, 200 and 500. Figure 9 shows the anumber of tests for large random interconnects (n = 1000, 5000 and 10000) for only smaller values o f f The following quantitative conclusions can be drawn from the simulation results. 1. The reduction in number of tests is significant in both the one-step and two-step cases compared to other approaches with no aliasing and confounding, i.e. Ref. [7] only. In the two-step case, at least 300
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a 50% reduction in number of diagnostic tests compared to Ref. [81 is achieved for the simulated benchmarks. In the one-step case, Algorithm 2 achieves a 35% reduction compared to Ref. [6]. 2. In the two-step case, the proposed approach requires a smaller number of tests than the C-test approach of Ref. [8] irrespective o f f 3. The number of tests using the proposed two-step process still shows a direct dependency with f f o r diagnosis.
10. Conclusions This paper has presented a new approach for diagnosing shorts in interconnects. The proposed approach exploits new conditions in test generation and compaction. For test generation, two algorithms with an execution complexity of O(n 2) are proposed; the first algorithm is applicable to one-step diagnosis while the second algorithm is applicable to two-step diagnosis. These algorithms are based on an adjacency analysis of the layout such that the test outcomes yield full
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T. Liu, F. Lombardi/INTEGRATION, the VLSI Journal 19 (1995) 181-198
detection and location. Correctness of the proposed algorithms is proved prior and after test compaction such that aliasing and confounding are avoided. Simulation has shown that for two-step diagnosis, the number of tests required is a function (direct proportionality) of the number of shorts in the interconnect; however, simulation results show that their number is less than previous approaches I-6-8, 10]. A further significant feature of this paper is that the two proposed diagnosis algorithms (one-step and two-step) can be used interchangeably depending on the testing requirements: if off-line testing is required, the one-step strategy is superior as the number of tests to be stored is constant for a given interconnect. If the chosen figure of merit is testing time, then two-step diagnosis may offer considerable advantages over a one-step approach because it allows a flexible execution of the diagnosis process in which detection and location are dealt separately and therefore, a lower number of tests (provided the number of faults is not very large). The advantage of a two-step diagnosis is more pronounced for larger interconnects.
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