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s in GaAs technology
Microelectronics Journal 33 (2002) 1107–1114 www.elsevier.com/locate/mejo
Differential current mode serial link for 2 Gb/s in GaAs technology R. Esper-Chaı´n*, F. Tobajas, R. Sarmiento Instituto Universitario de Microelectro´nica Aplicada, Campus Universitario de Tafira, pab. A, E-35017 Las Palmas de Gran Canaria, Spain Received 4 February 2002; revised 4 July 2002; accepted 30 July 2002
Abstract Today’s data communication systems are demanding increasing off-chip data rates. To satisfy this demand, high-speed serial links are used, saving area and power dissipation compared to highly parallel buses. However, power dissipation and noise generated by this system is still a critical issue. In this article, a novel approach using differential current mode is presented, which combines low power dissipation with low noise generated due to the reduced power transmission. q 2002 Elsevier Science Ltd. All rights reserved. Keywords: High-speed serial links; Differential current mode; Power dissipation
1. Introduction The increasing needs for bandwidth and switching capability in today’s data networks are demanding a considerable design effort, that can reach the limits of what current technologies can offer. In these systems, chipto-chip communication is becoming one of the most limiting bottlenecks, and new techniques are being introduced to achieve high data rate transfers. To increase the data rate in this chip-to-chip communication, two approaches can be taken: 1. Increase the bus width in a highly parallel data transfer environment. 2. Increase the speed of the transmission. The first approach was used in the past, however, multigigabit systems has several disadvantages related to the pincount, wide areas required in the boards and connectors, and high power dissipation. Systems such as switches are unsuitable for highly parallel approach. As example, consider a 16 £ 16 switch operating at 2.5 Gb/s, width data buses operating at a moderate level of parallelism such as 32 bits: the switch fabric will require at least 1024 pins and the back-plane and connectors 1024 lines to support the transfer among the different ports of the system. Also the power dissipation only related to the off-chip interface is a critical problem due to the high count of output drivers. * Corresponding author. Tel.: þ 34-928-451-250; fax: þ34-928-451-243. E-mail address: [email protected] (R. Esper-Chaı´n).
For this reason, high rate serial links are becoming more and more popular to implement these systems, reducing the pincount, and saving power dissipation. However, the high data rates used in these systems present their own and new problems as the propagation delay from chip to chip are comparable to the decreasing bit time. Therefore distributed model of the off-chip domain should be considered instead of the lumped model. Printed circuit board traces has to be considered as transmission lines, matching its impedance to 50 V using microstrip or stripline approaches. Also clocks cannot be transmitted, as it has to be recovered from data at the receiver chip with wide use of clock recovery units and clock multiplier. A typical link is shown in Fig. 1, where the data path from the incoming parallel data stream in the transmitter’s domain to the parallel data stream obtained in the receiver is shown. The transmitter (TX) and receiver (RX) are key components to transfer the signals from the chip domain to off-chip domain. They are essentially amplifiers and some standard interfaces are widely used such as Emitters Coupled Logic (ECL), Low Voltage ECL (LVECL), Positive ECL (PECL) and Low Voltage Differential Signal (LVDS) [6]. All these techniques are voltage-based, offering at least 400 mV of voltage drop across their ports. The transmitters are based on differential stages and usually present 50 V at their outputs, while receivers are differential amplifiers with 100 V across their inputs. This high speed serial approach has improved the power dissipation compared to the traditional parallel approach, due to the fact that, even the transmitter and receiver themselves have higher power dissipation than a common
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Fig. 1. High-speed serial off-chip transmission structure.
TTL driver, the number of element used is reduced and hence the power dissipation. However, further improvements are not possible with these techniques due to the nature of the voltage-based techniques. To clarify this, and as example consider a LVDS serial link, where the minimum voltage swing in the line is around 400 mV and both, transmitter and receiver has to be internally matched to 50 V. This imposes a theoretical minimum current swing, which at the end can be translated into minimum power dissipation. To reduce this power consumption, the voltage swing has to be reduced, but the noise margin is seriously affected due to the voltage-oriented operation. So there is no room for further improvements in power dissipation with these techniques. Furthermore, the increasing speed which drives to reduced rise and fall time of the signals transmitted, together with the increasing distances and number of signals used in systems such as high rate backplanes, is turning cross-talk and EMI effects as the main concerns of the designer of those systems, urging to find solutions at a reduced power dissipation. A potential way to release the minimum voltage drop across the line is to operate in current mode, where the information is carried out in the current sent by the transmitter to the receiver. With this technique, a low input impedance amplifier is used, which reduces the voltage swing in the line. This technique can reduce potentially not only the power, but also less energy is transferred from transmitter to receiver, so higher noise immunity should be expected. Anyway, the underlying expectancy is that if this technique is extensively used,
the overall switch noise in the system is reduced and the operation of this transmitter/receiver should not be compromised in real environment. Some works demonstrated better power efficiency using this current-mode approach [1 –3]. However, they exhibited reduced noise immunity. The reason for that is, related to the asymmetric transmission mode used, voltage mode presents low noise immunity when operating above several hundred of megabit per second. To overcome this problem, a novel technique which combines current mode operation with differential transmission is presented in this article. This technique combines the benefits of the low power dissipation of the current mode technique, with the high noise immunity of the differential data transmission. This work has been developed using Gallium Arsenide technology, which is suitable for high speed operation, maintaining reduced power dissipation due to its low dependency with dynamic consumption. The logic family used is Source Coupled FET Logic (SCFL) [4], which is based on differential stages and source followers. This logic family resembles the well known bipolar ECL, that eases the design of interfaces between SCFL and ECL, LVECL and PECL.
2. Serial link structure The idea of this system is shown in Fig. 2. In the transmitter side, a differential transconductance amplifier acting as current switch is used to route the current to
Fig. 2. Differential current mode serial link structure.
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2.1. Transmitter
Fig. 3. Differential cascode amplifier used as current serial link.
the proper line depending on the information in the inputs L/LN. At the receiver side, a differential transimpedance amplifier is used to convert current to voltage. This transimpedance amplifier is sized to have 100 V of input impedance. The output voltage of this transimpedance amplifier is amplified by a set of buffers, which also translates the voltage levels to the standard SCFL levels. This can be implemented using a differential cascode amplifier splitted between transmitter and receiver. The transmitter is composed of the current source and the differential pair which itself is a differential transconductance amplifier. The receiver is composed of a pair of common gates amplifier, which acts as transimpedance amplifier, translating the information carried in the differential current into voltage. This structure is shown in Fig. 3. Also, internal matching is provided by means of 100 resistors across the differential output signals in the transmitter. With this structure, matching at both ends is provided, making easier the interconnection across connectors, enabling this structure for operation at high-speed serial back-planes.
In Fig. 4, a schematic diagram of the transmitter is shown. It is composed of a SCFL buffer, which in turn is composed of a differential stage and two stages of source followers to drive the output differential pair that performs the current switching operation. The size of the transistors in this differential pair is adjusted to manage the current of the output current source. This current is designed to be nominally 10 mA. The SCFL driver has embedded its own reference stage for the current sources used by this stage. Due to the comparatively high current at the output stage, a separated reference stage is also provided for this stage. Drain resistors of high value are added to the differential pair to avoid drains to be floating when no receiver is connected. This transmitter is designed to operate at 3.3 V. 2.2. Receiver In Fig. 5, a schematic diagram for the receiver is shown. It is composed of a pair of common gate amplifiers that translate the current received into voltage. The design of this stage has some critical points that should be studied in detail before taking decisions about the sizing of the transistors. These critical points are: 1. The bias voltage in the common gate amplifier should be high enough to make this stage compatible with all the possible transmitters fabricated. 2. The bias voltage should not be too high, to leave some head room for the differential signal recovered. 3. The sizing of the input common gate amplifier should be done to match exactly an input dynamic impedance of 100 V across their inputs.
Fig. 4. Schematic diagram for the transmitter.
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Fig. 5. Receiver schematic diagram.
The contradictory requirements for the bias voltage at the common gate amplifier requires a set of simulation, comparing all the possible corner values of both receiver and transmitter to find the point that satisfies both requirements. The solution found is shown in the schematic diagram and it is implemented by a resistor with nominal value of 1900 V followed by three diodes. The sizing of the input common gate has a requirement that impose a unique size for the input transistors. Also the tolerance of this input dynamic matching is very high, due to the deviation of the transistors in the process. To alleviate this situation, a constant current source is added to each transistor, so that the input dynamic impedance can be controlled by a combination of bias current adjustment and
size of the transistor. A resistor of 1320 V is added to do a fine tuning of the input impedance. After the common gate stage, a source follower is added to adjust the voltage level of the SCFL buffers. To perform a good recovery from low signal, two stages of buffers are added. This is done to allow situations with high attenuation between transmitter and receiver. The structure of the SCFL buffers used in the receiver does not differ from the one used in the transmitter. 2.3. Layouts In Fig. 6, the layouts for the elements of the serial link are shown. The total area used for each element is
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Fig. 6. Layouts for the components of the serial link: (a) transmitter, (b) receiver, (c) detail of the transconductance amplifier and (d) detail of the transimpedance amplifier.
880 mm £ 200 mm which is a standard area in the padring used for ECL and LVDS. The reduction in power consumption drives to smaller transistors and thinner lines in the layout, and this drives to a reduction in the parasitic capacitance. As comparison, the equivalent ECL and LVDS serial links implemented in the same technology uses almost 100% of the area presented, while this design uses less than the 40% of the total available area. Due to the availability of large area to transmit the signal, the buffers should be placed at the proper place to optimize the signal transmission. In the transmitter, the input buffer stage is placed closed to the input, at the top of the area. With this configuration, the parasitic capacitances at the input of the transmitter are reduced. The output differential pair is placed closed to the bonding pad. In the receiver, the common gate amplifier and the first buffer are placed close to the bonding pad, and the second buffer is placed close to the output, at the top of the receiver. So wiring load capacitances are reduced at the output of the receiver. Also details of the transconductance amplifier, the output current source and its reference stage are shown in Fig. 6(c). The transimpendance amplifier with all the biasing circuitry and
source followers are shown in Fig. 6(d). It should be noticed that all the rules of differential layout are respected in the design. The size of the lines should be sized to allow the worst case of maximum current flow. Big transistors are splitted into several parallel fingers to avoid large gate width, with increased resistance and reduced speed.
3. Validation of the design In order to make a proper design, an accurate model of the system is required for the simulation. In the simulation setup built to validate the signal, the complete signal path for a link from the transmitter to the receiver is included. It should be noticed that this design is point to point oriented, so no simulation will be done in multi-drop configuration, where one transmitter drives several receivers. The path used for the simulation is shown in Fig. 7. The transmitter drives a package component provided by the foundry, which models the path from the bonding pad to the pin. Then, the off-chip domain is modeled as 50 V lines, that depending on the test, attenuation can be considered. Finally, at
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Fig. 7. Simulation setup.
the receiver domain, a pair of package elements and the receiver itself is included. Although not included in the figure, 1 mm wire load and a SCFL buffer is added at the output of the receiver. Also, the transmitter is driven by a standard SCFL buffer loaded with 1 mm wiring.
In order to guarantee the quality of the design to improve the yield, a set of simulations including worst corners should be done. This set of simulations will check the proper operation of the system, achieving the expected performance in all the worst situations. To distinguish between
Fig. 8. Results obtained for the transient simulation.
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Fig. 9. Results obtained for the AC simulation.
proper and marginal operation, some acceptance criteria must be specified. Usually these criteria include operation above the nominal margin. With this technique, the designer gets a safer design, but on the other hand, too much extra margin can make life too hard. In fact, when operation is above 1 Gb/s, designs are critical, and usually the only way to speed up the system is by increasing the power involved and the power dissipation. As conclusion, with these kinds of systems, a compromise should be taken to ensure ‘quality maintaining’ as much relaxed constraint as possible. For this particular design, a set of 16 corners were simulated in all the tests performed [5]. These corners were the combination of: 1. Process spread: fast þ 2s and slow 2 2s. 2. Power supply: þ 5% and 2 10%. It should be noticed that 2 10% is taken instead of 2 5% to model possible voltage drop across the power supply path. 3. Temperature: 0 and 100 8C. 4. Resistance tolerance: ^ 20%. Also a set of tests were specified to verify the proper operation of the link. These set included: 1. Transient simulation at maximum rate: the acceptance criterion is that any recovered pulse must have at least 90% of the amplitude of the voltage swing obtained in DC. 2. Response to a single pulse inserted after a long absence of transitions. The amplitude of this pulse must also reach the 90% of the DC amplitude. Also the duty cycle distortion is measured, and the pulse period should have at least the 80% of nominal pulse. This test is important in Gallium Arsenide, because the substrate is semi-insulating and has a very slow settling time. Usually, circuitry in Gallium Arsenide has a slower response after the absence of transitions. If this test is not satisfactory, some codification such as 8B10B should be included to ensure a minimum number of densities of transitions. 3. AC simulation: the link bandwidth at 2 3 dB must be above 1 GHz, which is the maximum frequency of a 2 Gb/s switching signal. 4. Mismatch in the off-chip traces: both elements must be able to absorb some reflections at both ends. This
mismatch cannot produce wrong information recovered at the receiver. 3.1. Results obtained Fig. 8 show the results obtained for a simulation that includes a single pulse and some transitions. The first curve shows the signal at the input ports of the transmitter. The second curve shows the current transmitted from the transmitter to the receiver. Finally, the last curve shows the signal available at the load buffer at the output of the receiver. Due to the mismatch of the connectors, some reflections are observed in the line at 18 and 22 ns, but this will be absorbed by the transmitter, which is also matched. However, a more detailed study of the reflections was carried out and no error was detected at the receiver due to this phenomenon. Also an AC simulation was performed, and the results obtained are shown in Fig. 9. On these simulations, the current mode transmitter exhibited a very wide bandwidth. According to that simulation, the limiting factor in the speed of the system is the set of buffer stages at the receiver, but the current mode serial link shows capability to operate at higher data rates. The results obtained in the simulation of the system is summarized in Table 1. The total power dissipation was less Table 1 Results obtained for the current mode serial link Min
Max
Units
Transmitter Power dissipation Current swing Delay Gain Cut-off at 23 dB Cut-off at 21 dB
14 2.5 113 14.8 3.1 2.5
36 6.3 130 30.1 3.4 2.9
mW mA ps V21 GHz GHz
Receiver Power dissipation Voltage swing Delay Gain Cut-off at 23 dB Cut-off at 21 dB
37 410 172 188 1.3 0.73
77 620 235 266 1.8 1.04
mW mV ps V GHz GHz
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than 115 mW for the whole link, which is 40% of the power consumption of the equivalent LVDS interface in the same technology. As stated before, the cut-off frequencies for the transmitter is beyond 3 GHz, which shows a potential operation beyond 5 Gb/s. The system showed capability to recover from 2.5 mA in the line, but allowing lower input signal to recover at the receiver (SCFL logic is able to operate with 300 mV); the operation can be acceptable below that value.
4. Conclusion The need for higher data rates in the interchip communication with high port count are driving these systems to use high speed serial links, instead of highly parallel data buses. The introduction of these techniques has produced saving of power dissipation due to the reduction of required number of elements of interface. However, the requirement of these systems to use internal impedances to match the lines, together with the minimum voltage swing in the line impose a minimum current transmission and power transfer between transmitter and receiver. These factors are making very difficult to improve the power dissipation furthermore with existing techniques. Also, the reduction of rising and falling edge times in the increasing data rates are making noise effect such cross-talk and EMI radiation big concerns in the upcoming systems. Current mode techniques release the needs for a minimum voltage swing, allowing the transmission of smaller signals with the benefits of a power dissipation reduction. To maintain a high reliability in the system, a novel differential approach is used in the current mode
transmission from the transmitter to the receiver. This is implemented by means of a differential cascode amplifier splitted between transmitter and receiver. The work presented shows a differential current mode serial link designed to replace the existing LVDS serial link. Its benefits are the power dissipation reduction to 40% of the original link (115 mW instead of 272 mW). Also, the current mode technique exhibits capability to operate at very high frequencies, the limiting factor being the voltage amplifier at the receiver. This shows a way of operation that should be studied carefully. Introducing new structures release this speed limitation at the receiver. The reduction of power transferred between transmitter and receiver will produce a noise reduction, reducing crosstalk and EMI, making systems operate with improved bit error ratio and robustness.
References [1] S.I. Long, J.Q. Zhang, Low power GaAs current-mode 1.2 Gb/s interchip interconnections, IEEE Journal of Solid-State Circuits 32 (6) (1997) 890– 897. [2] S.I. Long, Power optimization techniques for high-speed GaAs logic, 12th NORCHIP Seminar, Gothenburg, Sweden, 1994, pp. 93–105. [3] J.Q. Zhang, S.I. Long, F.H. Ho, J.K. Madsen, Low power current mode multi-valued logic interconnect for high speed interchip communications, 17th IEEE GaAs IC Symposium, San Diego, CA, 1995, pp. 327–330. [4] S.I. Long, S.E. Butner, Gallium Arsenide Digital Integrated Circuit Design, McGraw-Hill, New York, 1990. [5] Vitesse Semiconductor Corporation, HGaAs3 Models Version, 3.11. [6] Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, IEEE Standard for Low Voltage Differential Signals for SCI (LVDS), P1596.3-94/D1.0, 1993.
Differential current mode serial link for 2 Gb/s in GaAs technology R. Esper-Chaı´n*, F. Tobajas, R. Sarmiento Instituto Universitario de Microelectro´nica Aplicada, Campus Universitario de Tafira, pab. A, E-35017 Las Palmas de Gran Canaria, Spain Received 4 February 2002; revised 4 July 2002; accepted 30 July 2002
Abstract Today’s data communication systems are demanding increasing off-chip data rates. To satisfy this demand, high-speed serial links are used, saving area and power dissipation compared to highly parallel buses. However, power dissipation and noise generated by this system is still a critical issue. In this article, a novel approach using differential current mode is presented, which combines low power dissipation with low noise generated due to the reduced power transmission. q 2002 Elsevier Science Ltd. All rights reserved. Keywords: High-speed serial links; Differential current mode; Power dissipation
1. Introduction The increasing needs for bandwidth and switching capability in today’s data networks are demanding a considerable design effort, that can reach the limits of what current technologies can offer. In these systems, chipto-chip communication is becoming one of the most limiting bottlenecks, and new techniques are being introduced to achieve high data rate transfers. To increase the data rate in this chip-to-chip communication, two approaches can be taken: 1. Increase the bus width in a highly parallel data transfer environment. 2. Increase the speed of the transmission. The first approach was used in the past, however, multigigabit systems has several disadvantages related to the pincount, wide areas required in the boards and connectors, and high power dissipation. Systems such as switches are unsuitable for highly parallel approach. As example, consider a 16 £ 16 switch operating at 2.5 Gb/s, width data buses operating at a moderate level of parallelism such as 32 bits: the switch fabric will require at least 1024 pins and the back-plane and connectors 1024 lines to support the transfer among the different ports of the system. Also the power dissipation only related to the off-chip interface is a critical problem due to the high count of output drivers. * Corresponding author. Tel.: þ 34-928-451-250; fax: þ34-928-451-243. E-mail address: [email protected] (R. Esper-Chaı´n).
For this reason, high rate serial links are becoming more and more popular to implement these systems, reducing the pincount, and saving power dissipation. However, the high data rates used in these systems present their own and new problems as the propagation delay from chip to chip are comparable to the decreasing bit time. Therefore distributed model of the off-chip domain should be considered instead of the lumped model. Printed circuit board traces has to be considered as transmission lines, matching its impedance to 50 V using microstrip or stripline approaches. Also clocks cannot be transmitted, as it has to be recovered from data at the receiver chip with wide use of clock recovery units and clock multiplier. A typical link is shown in Fig. 1, where the data path from the incoming parallel data stream in the transmitter’s domain to the parallel data stream obtained in the receiver is shown. The transmitter (TX) and receiver (RX) are key components to transfer the signals from the chip domain to off-chip domain. They are essentially amplifiers and some standard interfaces are widely used such as Emitters Coupled Logic (ECL), Low Voltage ECL (LVECL), Positive ECL (PECL) and Low Voltage Differential Signal (LVDS) [6]. All these techniques are voltage-based, offering at least 400 mV of voltage drop across their ports. The transmitters are based on differential stages and usually present 50 V at their outputs, while receivers are differential amplifiers with 100 V across their inputs. This high speed serial approach has improved the power dissipation compared to the traditional parallel approach, due to the fact that, even the transmitter and receiver themselves have higher power dissipation than a common
0026-2692/02/$ - see front matter q 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 6 9 2 ( 0 2 ) 0 0 1 1 6 - 7
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Fig. 1. High-speed serial off-chip transmission structure.
TTL driver, the number of element used is reduced and hence the power dissipation. However, further improvements are not possible with these techniques due to the nature of the voltage-based techniques. To clarify this, and as example consider a LVDS serial link, where the minimum voltage swing in the line is around 400 mV and both, transmitter and receiver has to be internally matched to 50 V. This imposes a theoretical minimum current swing, which at the end can be translated into minimum power dissipation. To reduce this power consumption, the voltage swing has to be reduced, but the noise margin is seriously affected due to the voltage-oriented operation. So there is no room for further improvements in power dissipation with these techniques. Furthermore, the increasing speed which drives to reduced rise and fall time of the signals transmitted, together with the increasing distances and number of signals used in systems such as high rate backplanes, is turning cross-talk and EMI effects as the main concerns of the designer of those systems, urging to find solutions at a reduced power dissipation. A potential way to release the minimum voltage drop across the line is to operate in current mode, where the information is carried out in the current sent by the transmitter to the receiver. With this technique, a low input impedance amplifier is used, which reduces the voltage swing in the line. This technique can reduce potentially not only the power, but also less energy is transferred from transmitter to receiver, so higher noise immunity should be expected. Anyway, the underlying expectancy is that if this technique is extensively used,
the overall switch noise in the system is reduced and the operation of this transmitter/receiver should not be compromised in real environment. Some works demonstrated better power efficiency using this current-mode approach [1 –3]. However, they exhibited reduced noise immunity. The reason for that is, related to the asymmetric transmission mode used, voltage mode presents low noise immunity when operating above several hundred of megabit per second. To overcome this problem, a novel technique which combines current mode operation with differential transmission is presented in this article. This technique combines the benefits of the low power dissipation of the current mode technique, with the high noise immunity of the differential data transmission. This work has been developed using Gallium Arsenide technology, which is suitable for high speed operation, maintaining reduced power dissipation due to its low dependency with dynamic consumption. The logic family used is Source Coupled FET Logic (SCFL) [4], which is based on differential stages and source followers. This logic family resembles the well known bipolar ECL, that eases the design of interfaces between SCFL and ECL, LVECL and PECL.
2. Serial link structure The idea of this system is shown in Fig. 2. In the transmitter side, a differential transconductance amplifier acting as current switch is used to route the current to
Fig. 2. Differential current mode serial link structure.
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2.1. Transmitter
Fig. 3. Differential cascode amplifier used as current serial link.
the proper line depending on the information in the inputs L/LN. At the receiver side, a differential transimpedance amplifier is used to convert current to voltage. This transimpedance amplifier is sized to have 100 V of input impedance. The output voltage of this transimpedance amplifier is amplified by a set of buffers, which also translates the voltage levels to the standard SCFL levels. This can be implemented using a differential cascode amplifier splitted between transmitter and receiver. The transmitter is composed of the current source and the differential pair which itself is a differential transconductance amplifier. The receiver is composed of a pair of common gates amplifier, which acts as transimpedance amplifier, translating the information carried in the differential current into voltage. This structure is shown in Fig. 3. Also, internal matching is provided by means of 100 resistors across the differential output signals in the transmitter. With this structure, matching at both ends is provided, making easier the interconnection across connectors, enabling this structure for operation at high-speed serial back-planes.
In Fig. 4, a schematic diagram of the transmitter is shown. It is composed of a SCFL buffer, which in turn is composed of a differential stage and two stages of source followers to drive the output differential pair that performs the current switching operation. The size of the transistors in this differential pair is adjusted to manage the current of the output current source. This current is designed to be nominally 10 mA. The SCFL driver has embedded its own reference stage for the current sources used by this stage. Due to the comparatively high current at the output stage, a separated reference stage is also provided for this stage. Drain resistors of high value are added to the differential pair to avoid drains to be floating when no receiver is connected. This transmitter is designed to operate at 3.3 V. 2.2. Receiver In Fig. 5, a schematic diagram for the receiver is shown. It is composed of a pair of common gate amplifiers that translate the current received into voltage. The design of this stage has some critical points that should be studied in detail before taking decisions about the sizing of the transistors. These critical points are: 1. The bias voltage in the common gate amplifier should be high enough to make this stage compatible with all the possible transmitters fabricated. 2. The bias voltage should not be too high, to leave some head room for the differential signal recovered. 3. The sizing of the input common gate amplifier should be done to match exactly an input dynamic impedance of 100 V across their inputs.
Fig. 4. Schematic diagram for the transmitter.
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Fig. 5. Receiver schematic diagram.
The contradictory requirements for the bias voltage at the common gate amplifier requires a set of simulation, comparing all the possible corner values of both receiver and transmitter to find the point that satisfies both requirements. The solution found is shown in the schematic diagram and it is implemented by a resistor with nominal value of 1900 V followed by three diodes. The sizing of the input common gate has a requirement that impose a unique size for the input transistors. Also the tolerance of this input dynamic matching is very high, due to the deviation of the transistors in the process. To alleviate this situation, a constant current source is added to each transistor, so that the input dynamic impedance can be controlled by a combination of bias current adjustment and
size of the transistor. A resistor of 1320 V is added to do a fine tuning of the input impedance. After the common gate stage, a source follower is added to adjust the voltage level of the SCFL buffers. To perform a good recovery from low signal, two stages of buffers are added. This is done to allow situations with high attenuation between transmitter and receiver. The structure of the SCFL buffers used in the receiver does not differ from the one used in the transmitter. 2.3. Layouts In Fig. 6, the layouts for the elements of the serial link are shown. The total area used for each element is
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Fig. 6. Layouts for the components of the serial link: (a) transmitter, (b) receiver, (c) detail of the transconductance amplifier and (d) detail of the transimpedance amplifier.
880 mm £ 200 mm which is a standard area in the padring used for ECL and LVDS. The reduction in power consumption drives to smaller transistors and thinner lines in the layout, and this drives to a reduction in the parasitic capacitance. As comparison, the equivalent ECL and LVDS serial links implemented in the same technology uses almost 100% of the area presented, while this design uses less than the 40% of the total available area. Due to the availability of large area to transmit the signal, the buffers should be placed at the proper place to optimize the signal transmission. In the transmitter, the input buffer stage is placed closed to the input, at the top of the area. With this configuration, the parasitic capacitances at the input of the transmitter are reduced. The output differential pair is placed closed to the bonding pad. In the receiver, the common gate amplifier and the first buffer are placed close to the bonding pad, and the second buffer is placed close to the output, at the top of the receiver. So wiring load capacitances are reduced at the output of the receiver. Also details of the transconductance amplifier, the output current source and its reference stage are shown in Fig. 6(c). The transimpendance amplifier with all the biasing circuitry and
source followers are shown in Fig. 6(d). It should be noticed that all the rules of differential layout are respected in the design. The size of the lines should be sized to allow the worst case of maximum current flow. Big transistors are splitted into several parallel fingers to avoid large gate width, with increased resistance and reduced speed.
3. Validation of the design In order to make a proper design, an accurate model of the system is required for the simulation. In the simulation setup built to validate the signal, the complete signal path for a link from the transmitter to the receiver is included. It should be noticed that this design is point to point oriented, so no simulation will be done in multi-drop configuration, where one transmitter drives several receivers. The path used for the simulation is shown in Fig. 7. The transmitter drives a package component provided by the foundry, which models the path from the bonding pad to the pin. Then, the off-chip domain is modeled as 50 V lines, that depending on the test, attenuation can be considered. Finally, at
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Fig. 7. Simulation setup.
the receiver domain, a pair of package elements and the receiver itself is included. Although not included in the figure, 1 mm wire load and a SCFL buffer is added at the output of the receiver. Also, the transmitter is driven by a standard SCFL buffer loaded with 1 mm wiring.
In order to guarantee the quality of the design to improve the yield, a set of simulations including worst corners should be done. This set of simulations will check the proper operation of the system, achieving the expected performance in all the worst situations. To distinguish between
Fig. 8. Results obtained for the transient simulation.
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Fig. 9. Results obtained for the AC simulation.
proper and marginal operation, some acceptance criteria must be specified. Usually these criteria include operation above the nominal margin. With this technique, the designer gets a safer design, but on the other hand, too much extra margin can make life too hard. In fact, when operation is above 1 Gb/s, designs are critical, and usually the only way to speed up the system is by increasing the power involved and the power dissipation. As conclusion, with these kinds of systems, a compromise should be taken to ensure ‘quality maintaining’ as much relaxed constraint as possible. For this particular design, a set of 16 corners were simulated in all the tests performed [5]. These corners were the combination of: 1. Process spread: fast þ 2s and slow 2 2s. 2. Power supply: þ 5% and 2 10%. It should be noticed that 2 10% is taken instead of 2 5% to model possible voltage drop across the power supply path. 3. Temperature: 0 and 100 8C. 4. Resistance tolerance: ^ 20%. Also a set of tests were specified to verify the proper operation of the link. These set included: 1. Transient simulation at maximum rate: the acceptance criterion is that any recovered pulse must have at least 90% of the amplitude of the voltage swing obtained in DC. 2. Response to a single pulse inserted after a long absence of transitions. The amplitude of this pulse must also reach the 90% of the DC amplitude. Also the duty cycle distortion is measured, and the pulse period should have at least the 80% of nominal pulse. This test is important in Gallium Arsenide, because the substrate is semi-insulating and has a very slow settling time. Usually, circuitry in Gallium Arsenide has a slower response after the absence of transitions. If this test is not satisfactory, some codification such as 8B10B should be included to ensure a minimum number of densities of transitions. 3. AC simulation: the link bandwidth at 2 3 dB must be above 1 GHz, which is the maximum frequency of a 2 Gb/s switching signal. 4. Mismatch in the off-chip traces: both elements must be able to absorb some reflections at both ends. This
mismatch cannot produce wrong information recovered at the receiver. 3.1. Results obtained Fig. 8 show the results obtained for a simulation that includes a single pulse and some transitions. The first curve shows the signal at the input ports of the transmitter. The second curve shows the current transmitted from the transmitter to the receiver. Finally, the last curve shows the signal available at the load buffer at the output of the receiver. Due to the mismatch of the connectors, some reflections are observed in the line at 18 and 22 ns, but this will be absorbed by the transmitter, which is also matched. However, a more detailed study of the reflections was carried out and no error was detected at the receiver due to this phenomenon. Also an AC simulation was performed, and the results obtained are shown in Fig. 9. On these simulations, the current mode transmitter exhibited a very wide bandwidth. According to that simulation, the limiting factor in the speed of the system is the set of buffer stages at the receiver, but the current mode serial link shows capability to operate at higher data rates. The results obtained in the simulation of the system is summarized in Table 1. The total power dissipation was less Table 1 Results obtained for the current mode serial link Min
Max
Units
Transmitter Power dissipation Current swing Delay Gain Cut-off at 23 dB Cut-off at 21 dB
14 2.5 113 14.8 3.1 2.5
36 6.3 130 30.1 3.4 2.9
mW mA ps V21 GHz GHz
Receiver Power dissipation Voltage swing Delay Gain Cut-off at 23 dB Cut-off at 21 dB
37 410 172 188 1.3 0.73
77 620 235 266 1.8 1.04
mW mV ps V GHz GHz
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than 115 mW for the whole link, which is 40% of the power consumption of the equivalent LVDS interface in the same technology. As stated before, the cut-off frequencies for the transmitter is beyond 3 GHz, which shows a potential operation beyond 5 Gb/s. The system showed capability to recover from 2.5 mA in the line, but allowing lower input signal to recover at the receiver (SCFL logic is able to operate with 300 mV); the operation can be acceptable below that value.
4. Conclusion The need for higher data rates in the interchip communication with high port count are driving these systems to use high speed serial links, instead of highly parallel data buses. The introduction of these techniques has produced saving of power dissipation due to the reduction of required number of elements of interface. However, the requirement of these systems to use internal impedances to match the lines, together with the minimum voltage swing in the line impose a minimum current transmission and power transfer between transmitter and receiver. These factors are making very difficult to improve the power dissipation furthermore with existing techniques. Also, the reduction of rising and falling edge times in the increasing data rates are making noise effect such cross-talk and EMI radiation big concerns in the upcoming systems. Current mode techniques release the needs for a minimum voltage swing, allowing the transmission of smaller signals with the benefits of a power dissipation reduction. To maintain a high reliability in the system, a novel differential approach is used in the current mode
transmission from the transmitter to the receiver. This is implemented by means of a differential cascode amplifier splitted between transmitter and receiver. The work presented shows a differential current mode serial link designed to replace the existing LVDS serial link. Its benefits are the power dissipation reduction to 40% of the original link (115 mW instead of 272 mW). Also, the current mode technique exhibits capability to operate at very high frequencies, the limiting factor being the voltage amplifier at the receiver. This shows a way of operation that should be studied carefully. Introducing new structures release this speed limitation at the receiver. The reduction of power transferred between transmitter and receiver will produce a noise reduction, reducing crosstalk and EMI, making systems operate with improved bit error ratio and robustness.
References [1] S.I. Long, J.Q. Zhang, Low power GaAs current-mode 1.2 Gb/s interchip interconnections, IEEE Journal of Solid-State Circuits 32 (6) (1997) 890– 897. [2] S.I. Long, Power optimization techniques for high-speed GaAs logic, 12th NORCHIP Seminar, Gothenburg, Sweden, 1994, pp. 93–105. [3] J.Q. Zhang, S.I. Long, F.H. Ho, J.K. Madsen, Low power current mode multi-valued logic interconnect for high speed interchip communications, 17th IEEE GaAs IC Symposium, San Diego, CA, 1995, pp. 327–330. [4] S.I. Long, S.E. Butner, Gallium Arsenide Digital Integrated Circuit Design, McGraw-Hill, New York, 1990. [5] Vitesse Semiconductor Corporation, HGaAs3 Models Version, 3.11. [6] Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, IEEE Standard for Low Voltage Differential Signals for SCI (LVDS), P1596.3-94/D1.0, 1993.