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Digital Controller Design Based on Logic Neural Networks
Digital Controller Design Based on Logic Neural Networks Emil Pop, Monica Leba System Control, Applied Informatics and Computer Engineering Department, University of Petrosani, Str.Universitatii, nr.20, 332006, Romania, email: [email protected], [email protected] Abstract: In this paper a new approach on digital controller design based on logic neural networks is presented. In the first part of the paper the logic neuron and its logic function are introduced. Based on this, there is written the general equation for a logic neural network, which allows the easy design of any digital controller directly from the truth table. This solution is validated through MatLab Simulink modeling and simulation and then is implemented in a VLSI chip using PALASM HDL language and also in a ladder diagram PLC device. This method has the advantages of simplicity and flexibility and represents an easy to design modern solution. Keywords: logic neuron, VLSI, HDL, PLC, neural network, controller design y = u 2 ⋅ u1 ⋅ u0 + u 2 ⋅ u1 ⋅ u0 + u 2 ⋅ u1 ⋅ u0
1. INTRODUCTION A digital control system is described by truth tables or logic and timing functions. For example, a logic function with 3 variables called u0, u1 and u2 has the truth table of 23=8 lines that generate eight logic terms as shown in fig.1.a. The terms selection is made through other logic variables xi, i=0..7, for which the output y=1. In fig.1 the output y is given by the equation (1), where “·”, “+” and “¯” represent the AND, OR and NOT logic operators.
(1)
Analyzing the truth table there can be noticed that each column achieves a logic commutation from 0 to 1 with increasing frequencies from 20 to 22. This commutation can be represented using bi-positional switches, as presented in fig.1.b and fig.1.c. According to the truth table results the diagrams from fig.1.d and fig.1.e. This diagram can be simplified if there are switches with the same value of inputs, as shown in fig.1.f and fig.1.g.
Fig.1. Commutation diagram: a) truth table b) switch; c) block representation; d) general case; e) block general case; f) simplified function; g) block simplified function From fig.1.c and fig.1.e there can be noticed that these diagrams are similar to the neural networks, where each switch is a logic neuron with one output and three inputs, two used for learning and one for control, but the commutation is done by a logic equation. (Arbib, 2003).
Considering the n control inputs neural network from fig.2.b, the logic function for this is:
(
)
y = un ⋅ [un −1 ⋅ ... ⋅ u0 ⋅ x0 + u0 ⋅ x1 +
The logic equation is: y = u0 ⋅ x0 + u0 ⋅ x1
Depending on the input values x0, x1 and u0 there can be obtained elementary logic functions, as shown in fig.2.a.
(2)
Further in this paper, this element will be called logic neuron.
(
)
+ un −1 ⋅ ... ⋅ u0 ⋅ x2 n−1 − 2 + u0 ⋅ x2 n−1 −1 ] +
(
)
+ un ⋅ [un −1 ⋅ ... ⋅ u0 ⋅ x2 n−1 + u0 ⋅ x2 n−1 +1 +
(
)
+ u1 ⋅ ... ⋅ u0 ⋅ x2 n − 2 + u0 ⋅ x2 n −1 ]
(3)
programmable logic device. (Du et al., 2006). The main advantages of this method are generality, flexibility and simplicity. Next, there will be presented an example for the bidirectional control of an electrical drive system. The classic scheme is shown in fig.3.a and the logic functions are: KL = O ⋅ (PL + KL ) ⋅ KR KR = O ⋅ (PR + KR ) ⋅ KL
(4)
Fig.2. a) Elementary logic functions; b) Neural network This approach allows designing any logic structure, modeling, simulating and implementing using a
In fig.3.c are shown the truth tables for the above functions. These are necessary to build the simplified neural network diagram from fig.3.b.
Fig.3. Bidirectional control of an electrical drive system: a) Classic diagram; b) Neural network; c) Truth table
Fig.4. Bidirectional control: a) neural model; b) simulation results
Based on fig.3 there was modeled and simulated the neural network approach on the bidirectional control of the electric drive with the results from fig.4. As can be noticed in the simulation model, it is formed up by the interconnection of a number of identical blocks, so this represents an easy solution for VLSI code design using hardware description language (HDL) and also for PLC device programming. 2. HDL NEURAL BASED PROGRAMMING In order to design process control programs it is necessary to introduce timing functions and chose an implementation method, like VLSI embedded controller. 2.1. Timing functions In this approach, the timing functions will be achieved using the integration principle, like ramp generation or counter register. (Leba et al., 2008).
Fig.5. Timing functions: a) model; b) detail; c) simulation In fig.5 there are presented the models for time relays and the simulation results. The time relays can have different combinations of switches. In fig.5.a are presented four of these possibilities, like: normal opened timing on closing (NOTC↓), normal closed timing on opening (NCTO↑), normal closed timing on closing (NCTC↓) and normal opened timing on opening (NOTO↑).
Fig.6. Neuron and application: a) source code; b) controller test kit; c) simulation results 2.2. Implementation strategy The implementation strategy is based on VLSI embedded design using hardware description language (HDL). (Pedroni et al., 2004). For simple logic functions there can be used PALASM or ABEL languages, but for more complex logic functions it is necessary to use VHDL or Verilog languages. First we will implement in PALASM the logic neuron having the logic function (1) for Y. Then, based on this neuron, there is designed the code for the bidirectional controller presented above. The neural logic functions are the equations (4) for KL and KR.
The PALASM HDL code for the neuron and for the bidirectional controller application is presented in fig.6.a and in fig.6.c there are the simulation results. In fig.6.b is shown the hardware test kit based on a GAL16V8 chip. 3. APPLICATION 3.1. Star-Delta bidirectional drive control In this section there will present a complex application using the neural approach for bidirectional star-delta control of an electric drive. Using the push buttons PL and PR can be chosen the drive movement direction. Then, the controller starts instantly the drive in star connection for a preset time. Next, the star connection is opened for several milliseconds and then the delta connection is establishes. This connection
is used for the entire functioning period of the drive until it is pushed the O button which stops everything.
STAR = RTS ⋅ RTS ↑
(9)
The logic equations used for the star-delta bidirectional control are:
DELTA = RTS ⋅ RTD ↓
(10)
KL = O ⋅ (PL + KL ) ⋅ KR
(5)
KR = O ⋅ (PR + KR ) ⋅ KL
(6)
RTS = KL + KR
(7)
RTD = RTS ⋅ RTS ↓
(8)
There can be noticed that the star-delta connection needs to introduce the timing relays in this controller. These are
RTS ↓ , RTS ↑ and RTD ↓ . In fig.7.a is presented the neural model of the star-delta bidirectional controller and in fig.7.b the simulation results. In fig.7.c is shown the HDL-PALASM code for this application and in fig.7.d the HDL simulation results.
Fig.7. Star-delta control: a) neural model; b) simulation results; c) PALASM-HDL code; d) HDL simulation results
3.2. Water drain process control We’ll consider the hydraulic process of the water caption and evacuation using a plant having two pumps, one master and the second slave, controlled with a PLC by y1, y2 signals. The water is monitored by three level transducers, two of them named L1, L2 at superior position used to start the corresponding pumps and the third L0 at inferior level to stop all. If the master pump cannot evacuate the water, then the slave pump must help it. (Pop, 1983). The pumps must run cyclically for uniform wear and to maintain the drive rotor dry. Then, after a number of working cycles, the master pump becomes slave and vice versa.
This commutation is done by a counter signal c which exchanges the order of superior levels. The current levels are u1 and u2 and depend of L1, L2 and c. First we determine the truth tables for commutation signals u1, u2 and for control signals y1, y2, as shown in fig.8. Based on the truth tables, results the logic functions: y1 = L0 ⋅ (u1 + y1 )
(11)
y 2 = L0 ⋅ (u 2 + y 2 )
(12)
u1 = c ⋅ L1 + c ⋅ L2
(13)
u 2 = c ⋅ L2 + c ⋅ L1
(14)
Fig.8. Truth tables: a) commutation signals; b) control signals Then, there are determined the logic neural network model (fig.9) and the simulation results (fig.10). The above equations can be implemented in HDL PALASM and in a PAL chip (fig.12) or even in a PLC device.
Fig.9. Logic neural network model
Fig.10. Logic neural network simulation results In fig.11 is presented the ladder implementation. (Pop et al., 2003).
Fig.11. Ladder diagram PLC implementation
diagram
PLC
Fig.12. PALASM code and simulation results 4. CONCLUSIONS
REFERENCES
In this paper a new design approach based on logic neurons is presented.
Pop, E. and Leba, M. (2003). Microcontrollere si automate programabile. Editura Didactica si Pedagogica, Bucuresti. Pop, E. (1983). Automatizari in industria miniera. Editura Didactica si Pedagogica, Bucuresti. * * * (1996). PALASM Language Guide. NDSUEE Department. * * * (2000). High Performance PLD. Latice Corporation. Pedroni, V. (2004). Circuit Design with VHDL. MIT Press Cambridge, Massachusetts London, England. Arbib, M. (2003). The Hanbook of Brain Theory and Neural Networks, MIT Press, USA. Du, K.-L. and Swamy, M.N.S. (2006). Neural Networks in a Softcomputing Framework, Springer-Verlag London Limited. Leba, M. and Pop, E. (2008). New Distribution Properties and Applications in Digital Control. In Proceedings of
First it is defined the neuron logic function and is validated through modeling and simulation both in MatLab environment and in hardware description language. Then, there is written and tested the general logic function for a logic neural network. The possibilities to use this new method are shown by several practical examples. The projects were implemented in PALASM HDL language on a VLSI chip. Introducing the timing functions, there can be achieved easily digital controller, especially the modern VLSI embedded solution, but also the classical PLC implementation. As a first complex example, there was designed a star-delta bidirectional controller for an electrical drive, that was modeled, simulated and implemented in a GAL16V8 chip. The second complex example was designed for the water drain process control. This controller was designed using the same method. It was implemented as an embedded controller in HDL language and also as ladder diagram in a PLC. This new method is simple to use and ensures generality, flexibility and reliability.
the 7th WSEAS International Conference on ADVANCED TOPICS on SIGNAL PROCESSING, ROBOTICS and AUTOMATION, Cambridge, U.K., ISBN 978 960 6766 44 2, ISSN 1790 5117, pp. 43-48.
1. INTRODUCTION A digital control system is described by truth tables or logic and timing functions. For example, a logic function with 3 variables called u0, u1 and u2 has the truth table of 23=8 lines that generate eight logic terms as shown in fig.1.a. The terms selection is made through other logic variables xi, i=0..7, for which the output y=1. In fig.1 the output y is given by the equation (1), where “·”, “+” and “¯” represent the AND, OR and NOT logic operators.
(1)
Analyzing the truth table there can be noticed that each column achieves a logic commutation from 0 to 1 with increasing frequencies from 20 to 22. This commutation can be represented using bi-positional switches, as presented in fig.1.b and fig.1.c. According to the truth table results the diagrams from fig.1.d and fig.1.e. This diagram can be simplified if there are switches with the same value of inputs, as shown in fig.1.f and fig.1.g.
Fig.1. Commutation diagram: a) truth table b) switch; c) block representation; d) general case; e) block general case; f) simplified function; g) block simplified function From fig.1.c and fig.1.e there can be noticed that these diagrams are similar to the neural networks, where each switch is a logic neuron with one output and three inputs, two used for learning and one for control, but the commutation is done by a logic equation. (Arbib, 2003).
Considering the n control inputs neural network from fig.2.b, the logic function for this is:
(
)
y = un ⋅ [un −1 ⋅ ... ⋅ u0 ⋅ x0 + u0 ⋅ x1 +
The logic equation is: y = u0 ⋅ x0 + u0 ⋅ x1
Depending on the input values x0, x1 and u0 there can be obtained elementary logic functions, as shown in fig.2.a.
(2)
Further in this paper, this element will be called logic neuron.
(
)
+ un −1 ⋅ ... ⋅ u0 ⋅ x2 n−1 − 2 + u0 ⋅ x2 n−1 −1 ] +
(
)
+ un ⋅ [un −1 ⋅ ... ⋅ u0 ⋅ x2 n−1 + u0 ⋅ x2 n−1 +1 +
(
)
+ u1 ⋅ ... ⋅ u0 ⋅ x2 n − 2 + u0 ⋅ x2 n −1 ]
(3)
programmable logic device. (Du et al., 2006). The main advantages of this method are generality, flexibility and simplicity. Next, there will be presented an example for the bidirectional control of an electrical drive system. The classic scheme is shown in fig.3.a and the logic functions are: KL = O ⋅ (PL + KL ) ⋅ KR KR = O ⋅ (PR + KR ) ⋅ KL
(4)
Fig.2. a) Elementary logic functions; b) Neural network This approach allows designing any logic structure, modeling, simulating and implementing using a
In fig.3.c are shown the truth tables for the above functions. These are necessary to build the simplified neural network diagram from fig.3.b.
Fig.3. Bidirectional control of an electrical drive system: a) Classic diagram; b) Neural network; c) Truth table
Fig.4. Bidirectional control: a) neural model; b) simulation results
Based on fig.3 there was modeled and simulated the neural network approach on the bidirectional control of the electric drive with the results from fig.4. As can be noticed in the simulation model, it is formed up by the interconnection of a number of identical blocks, so this represents an easy solution for VLSI code design using hardware description language (HDL) and also for PLC device programming. 2. HDL NEURAL BASED PROGRAMMING In order to design process control programs it is necessary to introduce timing functions and chose an implementation method, like VLSI embedded controller. 2.1. Timing functions In this approach, the timing functions will be achieved using the integration principle, like ramp generation or counter register. (Leba et al., 2008).
Fig.5. Timing functions: a) model; b) detail; c) simulation In fig.5 there are presented the models for time relays and the simulation results. The time relays can have different combinations of switches. In fig.5.a are presented four of these possibilities, like: normal opened timing on closing (NOTC↓), normal closed timing on opening (NCTO↑), normal closed timing on closing (NCTC↓) and normal opened timing on opening (NOTO↑).
Fig.6. Neuron and application: a) source code; b) controller test kit; c) simulation results 2.2. Implementation strategy The implementation strategy is based on VLSI embedded design using hardware description language (HDL). (Pedroni et al., 2004). For simple logic functions there can be used PALASM or ABEL languages, but for more complex logic functions it is necessary to use VHDL or Verilog languages. First we will implement in PALASM the logic neuron having the logic function (1) for Y. Then, based on this neuron, there is designed the code for the bidirectional controller presented above. The neural logic functions are the equations (4) for KL and KR.
The PALASM HDL code for the neuron and for the bidirectional controller application is presented in fig.6.a and in fig.6.c there are the simulation results. In fig.6.b is shown the hardware test kit based on a GAL16V8 chip. 3. APPLICATION 3.1. Star-Delta bidirectional drive control In this section there will present a complex application using the neural approach for bidirectional star-delta control of an electric drive. Using the push buttons PL and PR can be chosen the drive movement direction. Then, the controller starts instantly the drive in star connection for a preset time. Next, the star connection is opened for several milliseconds and then the delta connection is establishes. This connection
is used for the entire functioning period of the drive until it is pushed the O button which stops everything.
STAR = RTS ⋅ RTS ↑
(9)
The logic equations used for the star-delta bidirectional control are:
DELTA = RTS ⋅ RTD ↓
(10)
KL = O ⋅ (PL + KL ) ⋅ KR
(5)
KR = O ⋅ (PR + KR ) ⋅ KL
(6)
RTS = KL + KR
(7)
RTD = RTS ⋅ RTS ↓
(8)
There can be noticed that the star-delta connection needs to introduce the timing relays in this controller. These are
RTS ↓ , RTS ↑ and RTD ↓ . In fig.7.a is presented the neural model of the star-delta bidirectional controller and in fig.7.b the simulation results. In fig.7.c is shown the HDL-PALASM code for this application and in fig.7.d the HDL simulation results.
Fig.7. Star-delta control: a) neural model; b) simulation results; c) PALASM-HDL code; d) HDL simulation results
3.2. Water drain process control We’ll consider the hydraulic process of the water caption and evacuation using a plant having two pumps, one master and the second slave, controlled with a PLC by y1, y2 signals. The water is monitored by three level transducers, two of them named L1, L2 at superior position used to start the corresponding pumps and the third L0 at inferior level to stop all. If the master pump cannot evacuate the water, then the slave pump must help it. (Pop, 1983). The pumps must run cyclically for uniform wear and to maintain the drive rotor dry. Then, after a number of working cycles, the master pump becomes slave and vice versa.
This commutation is done by a counter signal c which exchanges the order of superior levels. The current levels are u1 and u2 and depend of L1, L2 and c. First we determine the truth tables for commutation signals u1, u2 and for control signals y1, y2, as shown in fig.8. Based on the truth tables, results the logic functions: y1 = L0 ⋅ (u1 + y1 )
(11)
y 2 = L0 ⋅ (u 2 + y 2 )
(12)
u1 = c ⋅ L1 + c ⋅ L2
(13)
u 2 = c ⋅ L2 + c ⋅ L1
(14)
Fig.8. Truth tables: a) commutation signals; b) control signals Then, there are determined the logic neural network model (fig.9) and the simulation results (fig.10). The above equations can be implemented in HDL PALASM and in a PAL chip (fig.12) or even in a PLC device.
Fig.9. Logic neural network model
Fig.10. Logic neural network simulation results In fig.11 is presented the ladder implementation. (Pop et al., 2003).
Fig.11. Ladder diagram PLC implementation
diagram
PLC
Fig.12. PALASM code and simulation results 4. CONCLUSIONS
REFERENCES
In this paper a new design approach based on logic neurons is presented.
Pop, E. and Leba, M. (2003). Microcontrollere si automate programabile. Editura Didactica si Pedagogica, Bucuresti. Pop, E. (1983). Automatizari in industria miniera. Editura Didactica si Pedagogica, Bucuresti. * * * (1996). PALASM Language Guide. NDSUEE Department. * * * (2000). High Performance PLD. Latice Corporation. Pedroni, V. (2004). Circuit Design with VHDL. MIT Press Cambridge, Massachusetts London, England. Arbib, M. (2003). The Hanbook of Brain Theory and Neural Networks, MIT Press, USA. Du, K.-L. and Swamy, M.N.S. (2006). Neural Networks in a Softcomputing Framework, Springer-Verlag London Limited. Leba, M. and Pop, E. (2008). New Distribution Properties and Applications in Digital Control. In Proceedings of
First it is defined the neuron logic function and is validated through modeling and simulation both in MatLab environment and in hardware description language. Then, there is written and tested the general logic function for a logic neural network. The possibilities to use this new method are shown by several practical examples. The projects were implemented in PALASM HDL language on a VLSI chip. Introducing the timing functions, there can be achieved easily digital controller, especially the modern VLSI embedded solution, but also the classical PLC implementation. As a first complex example, there was designed a star-delta bidirectional controller for an electrical drive, that was modeled, simulated and implemented in a GAL16V8 chip. The second complex example was designed for the water drain process control. This controller was designed using the same method. It was implemented as an embedded controller in HDL language and also as ladder diagram in a PLC. This new method is simple to use and ensures generality, flexibility and reliability.
the 7th WSEAS International Conference on ADVANCED TOPICS on SIGNAL PROCESSING, ROBOTICS and AUTOMATION, Cambridge, U.K., ISBN 978 960 6766 44 2, ISSN 1790 5117, pp. 43-48.