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Digital redesign of analog smith predictor for systems with long input time delays
Accepted Manuscript
Digital Redesign of Analog Smith Predictor for Systems with Long Input Time Delays Linbo Xie , Leang-San Shieh , Jason Sheng-Hong Tsai , Shu-Mei Guo , Alex C Dunn PII: DOI: Reference:
S0016-0032(17)30328-9 10.1016/j.jfranklin.2017.07.014 FI 3053
To appear in:
Journal of the Franklin Institute
Received date: Revised date: Accepted date:
1 August 2016 21 April 2017 1 July 2017
Please cite this article as: Linbo Xie , Leang-San Shieh , Jason Sheng-Hong Tsai , Shu-Mei Guo , Alex C Dunn , Digital Redesign of Analog Smith Predictor for Systems with Long Input Time Delays, Journal of the Franklin Institute (2017), doi: 10.1016/j.jfranklin.2017.07.014
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Digital Redesign of Analog Smith Predictor for Systems with Long Input Time Delays Linbo Xiea, Leang-San Shiehb, Jason Sheng-Hong Tsaic, Shu-Mei Guod, Alex C. Dunne
b
c
Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77204-4005, USA ([email protected])
(Corresponding author)Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan, ROC ([email protected])
d
e
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Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education) Jiangnan University, Wuxi, 214122, Jiangsu, China ([email protected])
Department of Computer Science and Information Engineering, National Cheng-Kung University, Tainan 701, Taiwan, ROC ([email protected])
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a
United States Patent and Trademark Office (USPTO), Alexandria, United States ([email protected])
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Abstract The discretization of the analog Smith predictor by using the prediction-based state-matching digital redesign method for systems with various input time delays was recently investigated in the literature. This paper presents an alternative Chebyshev quadrature state-matching digital redesign method for discretization of the analog Smith predictor for systems with a long input time delay. In order to implement the digitally redesigned Smith predictor by utilizing the output-feedback of the plant, an ideal state reconstructor for the long input-delayed plant is established. The long dead time of interest is an integer plus a fractional input delay. An illustrative example is given to demonstrate the effective of the proposed approach.
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Keywords Smith predictor; Digital redesign; Long time delay; Input delay system; Sampled-data system
1. Introduction
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A time delay is often encountered in many practical processes, such as industrial processes, engineering systems, economical and biological systems. Such time delay is seen for example in the transport delay in a reactor, process piping, or the approximated modelling of high-order systems with low-order models with delays, such as the first-order plus dead time (FOPDT) and the second-order plus dead time (SOPDT) [1-3]. Various popular methods have been developed and several open problems have been raised in an effort to improve the performance of time-delay systems [3, 4]. The Smith predictor [5-7] is one of the most popular methods for solving time-delay problems in industry
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and several extensions and modifications, such as the internal model control (IMC) [8-15] have been proposed to improve the performance of the Smith predictor. The resulting analog Smith predictor is often required to be digitally implemented for better reliability, lower cost, smaller size, more flexibility and better performance. A detailed explanation of the advantages of the digital controller over the analog one can be found in [2, 16]. In the literature, the Smith predictor is usually represented
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in the frequency domain by its transfer function. For digital implementation, it is desirable to obtain the time-domain representation such as the state-space model of the Smith predictor. The prediction-based state-matching digital design method together with various case studies on the lengths of the input dead times were investigated in [17, 18] for the systems with relatively short dead times. For instance, the prediction-based state-matching digital redesign method proposed in [17, 18] works well for the input-delayed system with the integer delay part N 0 and the fractional delay part 0 in the time
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delay Td ( N )T , where T is the sampling period. However, it was reported in [18] that when the input dead time is relatively long, the digitally redesigned sampled-data system exhibits unstable response. In general, the integer part can be easily converted into its digital equivalent, but this is not the case with the fractional part. When this fractional delay cannot be ignored or cannot be effectively
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approximated by means of any method (such as Pade’s method), it must be considered and included in both the digital redesign and the ideal state reconstruction, for sampled-data control of the time-delay
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systems.
It is generally known that the Smith predictor can simplify the design of systems with input/output delays [4-15], using the knowledge of the output dead times and feedback control law of the plant. In
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addition, the mismatch between the internal model used for the prediction-based control and its actual plant may destabilize the whole closed-loop system. In order to discretize the analog Smith predictor
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using the reformulated augmented system, the extended state of the plant is required for the development and implementation of the digital counterpart of the designed analog Smith predictor. If
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the state of the plant is not available, then a state estimator such as an observer is naturally required to estimate the plant states. In this case, additional dynamics would be introduced in the closed-loop system and the dimension of the resulting system could become very high. In this paper, a simple and unique digital redesign method via the Chebyshev quadrature formula
[19, 20] is developed to find the digitally redesigned Smith predictor for systems with long input dead times. First, the designed analog Smith predictor together with the plant is reformulated into a state-augmented system with long input time delay. Then, an alternative Chebyshev quadrature state-matching digital redesign method is developed to obtain the digital counterpart by extending the 2
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method developed for the delay-free systems [19, 20] to long time-delay systems. If the states of the input time-delay plant are not available for measurement and for the output feedback requirement of the digitally redesigned Smith predictor, an ideal state reconstructor, which takes advantage of the multirate sampling technique, for the aforementioned augmented time-delay system is developed. The advantages of using the multirate sampling technique for the ideal state reconstruction are: (i) it does
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not introduce additional dynamics in the closed-loop system as is the case with the traditional observer; (ii) it decreases the dimension and complexity of the overall system; and (iii) it allows the utilization of the state feedback controller without an observer. The paper concludes with an illustrative example to demonstrate the effectiveness of the developed approach.
2. Problem formulation
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Consider that the Smith predictor can be designed as shown in Fig. 1, where G1 ( s)e sTd is a time-delay analog plant with long input time delay Td ( N )T , where N 0 is the integer delay part; 0 1 is the fractional delay part and T the sampling period.
Ec
e( t )
uc2 (t)
G1 ( s )
uc3 (t )
uc1 (t )
yc2(t)
G1(s)e sTd
yc1(t )
1 e sTd
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yc3 (t )
G2 ( s )
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r (t )
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Fig. 1 Smith predictor formulation
The state-space representations of the subsystems in Fig. 1 are given in the following.
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G2 ( s ) :
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G1 ( s)e sTd :
G1 ( s) 1 e sTd :
xc1 (t ) A1 xc1 (t ) B1uc1 (t Td ) yc1 (t ) C1 xc1 (t ) xc 2 (t ) A2 xc 2 (t ) B2uc 2 (t ) yc 2 (t ) C2 xc 2 (t ) D2uc 2 (t ) uc1 (t ) xc 3 (t ) A1 xc 3 (t ) B1 uc1 (t ) uc1 (t Td ) yc 3 (t ) C1 xc 3 (t )
(1)
(2)
(3)
where xc1 (t ) R n1 , xc 2 (t ) R n2 , xc 3 (t ) R n1 , uc1 (t ) R m1 , uc 2 (t ) R p1 , uc 3 (t ) R m1 , yc1 (t ) R p1 , yc 2 (t ) R m1 and yc 3 (t ) R p1 . The matrices ( A1, B1, C1, A2 , B2 , C2 , D2 ) are of appropriate dimensions.
From Fig. 1, we obtain the input-output transfer function 3
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yc1 ( s ) G2 ( s )G1 ( s)e sTd Ec r ( s ) 1 G2 ( s)G1 ( s)(1 e sTd )
If we set Td 0 in (4), then we have
G2 ( s )G1 ( s)e sTd G2 ( s)G1 ( s)e sTd 1 sTd 1 G2 ( s)G1 ( s)(1 e ) 1 G2 ( s )G1 ( s)
(4)
yc1 ( s ) G2 ( s )G1 ( s ) . Hence, the numerator polynomial of Ec r ( s ) 1 G2 ( s )G1 ( s )
1 G2 (s)G1 (s) is the denominator polynomial of the transfer function Yc1 (s) /( Ec r (s)) in (4) with Td 0 .
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The stabilizing controller G2 ( s) should make such transfer function stable. In the time-domain, the corresponding augmented state-space equations for (1)-(3) can be represented as xec (t ) Ae xec (t ) Beuc1 (t Td ) Fˆec rˆ(t )
(5a)
uc1 (t ) Kec xec (t ) Eec rˆ(t )
(5b)
yc1 (t ) Ce xec (t )
0 xc1 (t ) A1 xec (t ) xc 2 (t ) , Ae B2C1 A2 xc 3 (t ) B1D2C1 B1C2
0 B1 0 ˆ B2C1 , Be 0 , Fec B2 , Fec Fˆec Ec , Eec D2 , A1 B1D2C1 B1 B1D2
D2C1 , and Ce C1 0 0 . When Td 0 , the transfer function of the closed-loop
system in (5) becomes
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Kec D2C1 C2
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where rˆ(t ) Ec r(t ) , and
(5c)
yc1 ( s ) G2 ( s )G1 ( s ) , and it is stable and can be represented from (5) as Ec r ( s ) 1 G2 ( s )G1 ( s )
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yc1 (t ) Ce sI n ( Ae Be Kec ) ( Be Eec Fˆec )rˆ( s) Ce sI n Aec Bec Ec r( s) 1
(6)
Bec Be Eec Fˆec . The characteristic equation
Aec Ae Be Kec , and
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where rˆ( s) Ec r( s) ,
1
( det( sI n Aec ) 0 ) of the system in (6) is asymptotically stable. As a result, the closed-loop system
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matrix Aec is asymptotically stable. In order to retain the stability of Aec in (5) for Td 0 , the control
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law in (5b) should be expressed as uc1 (t ) Kec xec (t Td ) Eec rˆ(t Td )
(7a)
or
uc1 (t Td ) Kec xec (t ) Eec rˆ(t )
(7b)
where rˆ(t ) Ec r (t ) and r (t ) is a unit-step reference input. Since rˆ(t ) is a constant reference input for t 0 , the predicted constant reference input rˆ(t Td ) will be equal to rˆ(t ) . The objective of this paper is to digitally redesign the analog Smith predictor control system (5) so that the analog and the
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discrete states match each other closely for the long input time delay Td . Suppose the corresponding closed-loop hybrid systems of (5) with Td 0 and t kT is represented as xed (t ) Ae xed (t ) Beud 1 (t Td ) Fˆec rˆ(t )
(8a)
ud 1 (kT ) Ked xed (kT Td ) Eed rˆ(kT )
(8b)
where ud 1 (kT ) R m is a piecewise-constant signal after a zero-order hold with the sampling period T ,
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the xed (kT Td ) in (8b) is the discretization of the analog state xec (t Td ) in (7a), and the digital gains ( Ked , Eed ) in (8b) can be approximately obtained from the analog gains ( Kec , Eec ) in (7a) or (5b) via the Chebyshev quadrature digital redesign method described in the following Section 3.
In [18], it was intended to assume that if the dead time Td in (7) is sufficiently small ( Td 1 ) and
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the state xec (t ) in (5b) can be approximately equal to xec (t Td ) in (7a), as a result, the uc1 (t ) in (5b) can be approximately represented as
uc1 (t ) Kec xec (t Td ) Eec rˆ(t ) for Td 1
(8c)
Substituting (8c) into (5a) results in the closed-loop system matrix as ( Ae Be Kec ) . If ( Ae Be Kec ) is
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still asymptotically stable, then various prediction-based digital control laws ud 1 (kT ) in (8b) were redesigned according to the length of various dead time Td for digital control of the sampled-data
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system in (8). In this paper, the Chebyshev quadrature digital redesign method is utilized to develop a simple and unique digital control law ud 1 (kT ) in (8b) for any length of the dead time Td in the
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following.
3. Chebyshev quadrature digital redesign method
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3.1 Chebyshev quadrature formulation The discrete-time solution of xec (t ) at time instant t kT T in (5a) with Td 0 is
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xec (kT T ) e AeT xec (kT )
kT T
e Ae ( kT T ) Beuc1 ( )d
kT
kT T
e Ae ( kT T ) Fˆec rˆ( )d
(9)
kT
The right-hand side of (9) can be approximately evaluated by the Chebyshev quadrature equation [19, 20]. The general Chebyshev quadrature formula can be re-formulated for utilization of digital redesign as
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b
a
N
N b b 1 1 N ( ) d f ( ) ( ) d lim f (i ) i a N N 1 N 1 a i 0 i 0
( ) f ( )d W f (i ) i 0
N b N (b a ) 1 b ( )d lim f (i ) ( )d f ( )d a a N ( N 1)( b a ) N b a a i 0
(10)
b
where ( ) is a constant sign weighting function in [a, b] , W is the weighting factor determined b 1 ( )d , and N 1 a
f (i ) are the values of the function
f ( )
evaluated at
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by W
i a i(b a) N , for i 0,1, , N . 3.2 Approximate discrete-time model
According to (10), the first integral term in the right-hand side of (9) can be represented as
kT
where H e
kT T
kT
e
kT T 1 kT T e Ae ( kT T ) Beuc1 ( )d e Ae ( kT T ) Bed uc1 ( )d H euc1 (t ) kT T kT
Ae ( kT T )
(11)
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kT T
Bed [Ge I n ] A B , Ge e 1 e e
AeT
1 and uc1 (t ) T
kT T
uc1 ( )d . It is noticed that when
kT
i Ae is a singular matrix, the matrix H e Ge I n Ae1Be becomes H e T i 0 AeT (i 1)!Be .
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Hence, the discrete-time solution of (9) at t kT T is
where H er
kT T
kT
(12)
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xec (kT T ) Ge xec (kT ) H euc1 (t ) H er rˆ(kT )
e Ae ( kT T ) Fˆec d [Ge I n ] Ae1Fˆec and rˆ(kT ) is the piecewise-constant reference
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input. Discretization of (8a) and (8b) with both Td 0 yields kT T
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xed (kT T ) e AeT xed (kT )
e Ae ( kT T ) Beud 1 ( )d
kT
kT T
e Ae ( kT T ) Fˆec rˆ( )d
kT
(13)
Ge xed (kT ) H eud 1 (kT ) H er rˆ(kT )
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Comparing (12) and (13), we observe that if we let xec (kT T ) in (12) approximately equal to xed (kT T ) in (13) and xec (kT ) in (12) approximately equal to xed (kT ) in (13), then uc1 (t ) in
(12) would be approximately equal to ud 1 (kT ) in (13). As a result, uc1 (t ) in (12) can be approximately evaluated from (11) and (7a) with Td 0 as
uc1 (t )
1 T
kT T
uc1 ( )d
kT
6
Kec T
kT T
kT
xec ( )d Eec rˆ(kT )
(14)
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3.3 The improved digital redesign method The integral term in the right-hand side of (14) can be exactly evaluated by integrating the closed-loop system of (5a) and (7a) with Td 0 as kT T
kT T
xec (t )dt Aec
kT
xec ( )d ( Be Eec Fˆec )
kT
kT T
rˆ( )d
(15)
kT
kT T
x
ec
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The first integral term in the right-hand side of (15) can be solved from (15) as
( )d Aec1[ xec (kT T ) xec (kT ) T ( Be Eec Fˆec )rˆ(kT )]
kT
Substituting (16) into (14), we have
uc1 (t ) Kec ( AecT )1[ xec (kT T ) xec (kT ) T ( Be Eec Fˆec )rˆ(kT )] Eecrˆ(kT )
(16)
(17)
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Since it is desired to closely match the xed (t T ) and xed (t ) in (13) with the xec (t T ) and xec (t ) in (12), respectively, with a little abuse of the notation we consider xec (t T ) xed (t T ), xec (t ) xed (t ) and uc1 (kT ) ud1 (kT ). Then, (17) becomes
Substituting (13) into (18), we have
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ud 1 (kT ) Kec ( AecT )1[ xed (kT T ) xed (kT ) T ( Be Eec Fˆec )rˆ(kT )] Eecrˆ(kT ) ud 1 (kT ) Kec ( AecT )1 (Ge I n ) xed (kT ) H eud 1 (kT ) ( H er TBec )rˆ(kT ) Eecrˆ(kT )
(18)
(19)
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Solving ud 1 (kT ) from (19) and equating its result to the digital control law in (8b) with Td 0 gives ud 1 (kT ) Ked xed (kT ) Eed rˆ(kT )
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where
Ked [ I m Kec ( AecT )1 H e ]1 Kec ( AecT )1 (Ge I n )
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Eed [ I m Kec ( AecT )1 H e ]1 Eec Kec ( AecT )1 ( H er TBec )
(20)
(21a) (21b)
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where Aec Ae Be Kec , Ge e AeT , H e (Ge I n ) Ae1Be , H er [Ge I n ] Ae1Fˆec and Bec Be Eec Fˆec . The digital control gains ( Ked , Eed ) obtained in (21) can be further simplified as follows. Substituting (5b) into (5a) with Td 0 yields the closed-loop system as xec (t ) Aec xec (t ) Bec rˆ(t ) Aec xec (t ) Bec Ec r (t ) yc1 (t ) Ce xec (t )
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(22a)
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For tracking the unit-step reference input r (t ) in (22a) and by applying the final-value theorem to (22a), we can determine the reference input gain Ec in (22a) for a multivariable system with
yc1 (t ) R p1 , r(t ) R m1 and p1 m1 as Ec Ce ( Aec ) 1 Bec
1
(22b)
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Since xec (t T ) xed (t T ) and xec (t ) xed (t ) , the discretization of (22a) becomes xed (kT T ) Gec xed (kT ) H ec rˆ(kT )
(23)
where Gec e AecT e( Ae Be Kec )T , and H ec (Gec I n ) Aec1Bec . Also, the discretization of (5a) with Td 0 gives
xed (kT T ) Ge xed (kT ) H eud 1 (kT ) H er rˆ(kT )
(24a)
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where Ge e AeT , H e (Ge I n ) Ae1Be , and H er (Ge I n ) Ae1Fˆec . Substituting (8b) with Td 0 into (24a) results in
xed (kT T ) (Ge H e Ked ) xed (kT ) ( H e Eed H er )rˆ(kT )
Comparing (24b) with (23) yields
(24b)
Gec Ge H e Ked and H ec H e Eed H er
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(24c)
Pre-multiplying both sides of (21a) with
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m
m
Kec ( AecT )1 H e and utilizing the relationship obtained
Kec ( AecT )1 H e Ked Kec ( AecT )1 Ge I n or
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in (24c) gives
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Ked Kec ( AecT )1 Ge I n H e Ked Kec ( AecT )1 (Gec I n )
CE
Hence
(25a)
Ked Kec ( AecT )1 (Gec I n )
where Aec Ae Be Kec . Also, pre-multiplying both sides of (21b) with
(25b)
I
m
Kec ( AecT )1 H e and
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using the relationship in (24c) gives
I
m
Kec ( AecT )1 H e Eed Eec Kec ( AecT )1 ( H er TBec )
or
Eed Eec Kec ( AecT ) 1 H er Kec Aec1Bec Kec ( AecT ) 1 ( H ec H er ) Eec Kec Aec1Bec Kec ( AecT )1 (Gec I n ) Aec1Bec Eec ( Kec Ked ) Aec1Bec
Hence,
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(25c)
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Eed Eec ( Kec Ked ) Aec1Bec
(25d)
3.4 Digital redesign for a long time-delay system For Td ( N )T 0 , N 0 , 0 1
and rˆ(kT ) Ec r (kT ) , the digitally redesigned control law
in (8) with Td 0 becomes ud 1 (kT ) Ked xed (kT Td ) Eed rˆ(kT )
(26)
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The discrete-time state xed (kT Td ) in (26) with Td 0 is the discretization of the analog state xec (t Td ) in (7a) with Td 0 and can be determined from (5a) with Td 0 as follows:
xed (kT Td ) e
AeTd
xed (kT )
kT Td
e
Ae ( kT Td )
Beud 1 ( Td )d
kT Td
kT
kT kT
e Ae ( kT ) Beud 1 ( )d
kT NT T kT NT
kT NT T
kT Td
e Ae ( kT Td ) Fˆecd rˆ(kT )
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e Ae ( N )T xed (kT ) Ge( N ) xed (kT )
e Ae ( kT Td ) Fˆec rˆ( )d
kT
N
e Ae ( kT ) Beud 1 ( )d i 1
kT iT T
kT iT
T
d e Ae ( kT ) Beud 1 ( )d e Ae Fˆecd rˆ(kT )
Ge( N ) xed (kT ) Ge( N ) H e( )ud 1 (kT NT T ) Ge( N 1) H e(1)ud 1 (kT NT )
0
H eud 1 (kT T ) H er( N )rˆ(kT ) (27)
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where Ge( N ) e Ae ( N )T , H e( ) (Ge( ) I n ) Ae1Be , H e(1) (Ge(1) I n ) Ae1Be H e and H er( N ) (Ge( N ) I n ) Ae1Fˆec . Substituting (27) into (26) results in the desirable digitally redesigned control law for the long
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time-delayed analog control law in (4a) with Td 0 as ud 1 (kT ) Kˆ ed xed (kT ) FN 1ud 1 (kT NT T ) FN ud 1 (kT NT ) N 1
F1ud 1 (kT T ) ( Eed Hˆ er( N ) )rˆ(kT )
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Kˆ ed xed (kT ) Fi ud 1 (kT iT ) ( Eed Hˆ er( N ) )rˆ(kT ) i 1
CE
(28)
where Kˆ ed Ked Ge( N ) , FN 1 Ked Ge( N ) H e( ) , FN Ked Ge( N 1) H e ,…, F1 Ked H e , Hˆ er( N ) Ked H er( N ) ,
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rˆ(kT ) Ec r(kT ) , and r(kT ) is a unit-step reference input function. The digital gains K ed and Eed
in (28) can be found in (25b) and (25d), respectively, and Ec is determined from (22b). It is noticed that when T 0 , the digitally redesigned gains ( Ked , Eed ) in (25b) and (25d) can be reduced to the analog gains ( Kec , Eec ) in (5b), respectively.
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3.5 Improvement of the existing method in [18] Now, from (5), (8c) and (27), it can be concluded that for the prediction-based state-matching digital redesign method proposed in [18] to work well, it is not only required for the dead time Td ( N )T to be very small, but also the integer N in the Td must be sufficient small, such that the percentage error
between
the
analogously
controlled
system
and
the
digitally
redesigned
system
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( Gec Ge H e Ked ) Gec 100% % in (24c) (for instance 5 ), where the digitally redesigned
gain K ed is obtained in [18]. For example, the prediction-based state-matching digital redesign method proposed in [17, 18] works well for the input-delayed system with N 0 and 0 in Td . Nevertheless, when the integer N in Td is not sufficiently small, there exists a large discrepancy
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between the discretized state xed (kT Td ) in (25), (which is set to be equal to the analog state xec (t Td ) at t kT and Td ( N )T in (8c) or the state xec (t Td ) in
(5a) via the state-matching
digital redesign method proposed in [18]), and the analog state xec (t ) at t kT in (5b). In other words, the prediction-based state-matching digital redesign method proposed in [18] works well, if the sampling period T lies within (3-10)b , (where the b is the bandwidth), and both the dead
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time Td and the integer N in Td are sufficiently small, such that both the state xec (t Td ) in (5a)
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the state xec (t ) in (5b) and the percentage error ( Gec Ge H e Ked ) Gec 100% % in (24c). This is evident in the simulations shown in Fig. 9 in [18], in which (i) the performance of the response is fairly good for Td ( N )T 0.192 1 , where T 0.035s , 0.49 and N 5 , and (ii) the
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and N 10 .
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performance of the response is degraded for Td ( N )T 0.367 1 , where T 0.035s , 0.49
4. Ideal state reconstructor for long input time delay
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If the state of the plant xed 1 (t ) , which is contained in the extended state xed (t ) in (8) and is required for the implementation of (28), is not available, the following multirate sampling technique (called the ideal state reconstructor for a long input-delay system) is applied within one sampling period to reconstruct the ideal (exact) state xed 1 (kT ) , i.e., with the errors in the states going to zero in one sample period. It should be noted that xed 2 (kT ) and xed 3 (kT ) contained in xed (kT ) are the states of the digital Smith predictor, which are always realizable and available. To increase the accuracy in reconstructing the ideal state in (28), two cases are considered regarding the value of : (i) 10
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0 1/ 2 and (ii) 1/ 2 1 . The method for reconstructing the ideal state for case (ii) is developed
in Appendix A. ud 1 ( kT NT )
ud1(kT NT T )
ud1(kT NT T )
TNˆ
yd1(t) ·······
kT TNˆ kT
kT T
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fast sampled data {YF}
kT T kT T T
Fig. 2 Multirate sampling sequence for ideal state reconstructor (case (i))
Suppose that the discretized counterpart of (1) after a zero-order hold with sampling period T is
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represented as xd 1 (t ) A1 xd 1 (t ) B1ud 1 (t Td )
(29)
yd 1 (t ) C1 xd 1 (t )
where xd 1 (t ) R n1 , yd 1 R p1 , ud 1 (t Td ) R m1 is the digital counterpart of the continuous time (1 )T T is the Nˆ
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control law uc1 (t Td ) in (1). Consider the case N 0 and 0 1/ 2 , let TNˆ
ˆ ˆ , Nˆ n , T ( N )T , ˆ , and the multirate sampling fast sampling period, T T NT 1 d N
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sequence shown in Fig. 2. The solution of (29) at time instants t kT T and t0 kT is given as xd 1 (kT T ) e A1 T xd 1 (kT )
kT T
kT
e A1 ( kT T ) B1ud 1 ( NT T )d
where G1( ) e A T 1
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G1( ) xd 1 (kT ) H1( )ud 1 (kT NT T )
and
H1( )
kT T
kT
e A1 ( kT T ) B1d (G1( ) I ) A11B1 . Considering t kT T
(30)
and
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t0 kT TNˆ in (12), and since ud 1 (t ) ud 1 (kT NT T ) when t kT TNˆ , kT T , the solution
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xd 1 (kT T ) G1(ˆ ) xd 1 (kT TNˆ )
kT T
kT TNˆ
( ˆ ) 1 d1
e A1 ( kT T ) B1d ud 1 (kT NT T )
( ˆ ) 1 d1
(31)
G x (kT TNˆ ) H u (kT NT T )
is found, where H1(ˆ )
kT T
kT TNˆ
e A1 ( kT T ) B1d (e A1ˆT I ) A11B1 (G1(ˆ ) I ) A11B1 . From (31), we obtain
xd 1 (kT TNˆ ) G1( ˆ ) xd 1 (kT T ) G1( ˆ ) H1(ˆ )ud 1 (kT NT T ) , k N where G1( ˆ ) H1(ˆ ) (G1( ˆ ) I ) A11B1 H1( ˆ ) . Substituting xd 1 (kT T ) in (30) into (32), we get
11
(32)
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xd 1 (kT TNˆ ) G1( ) xd 1 (kT ) H1( )ud 1 (kT NT T )
(33)
where G1( ) e A T , H1( ) G1( ˆ ) H1( ) H1( ˆ ) (G1( ) I ) A11B1 . Since it is known that ud 1 (kT NT T ) is 1
piecewise constant (i.e., it is the output of a zero-order hold), then ud 1 (kT NT iTNˆ ) ud 1 (kT NT T ) for 0 i Nˆ . By successively shifting back TNˆ T from (33), we obtain
(34)
xd 1 (kT 3TNˆ ) G1( 3 ) xd 1 (kT ) H1( 3 )ud 1 (kT NT T ) ,
(35)
ˆ ˆ ) G( Nˆ ) x (kT ) H ( Nˆ )u (kT NT T ) . xd 1 (kT NT 1 d1 1 d1 N
(36)
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xd 1 (kT 2TNˆ ) G1( 2 ) xd 1 (kT ) H1( 2 )ud 1 (kT NT T ) ,
and in general,
y , for (i ) d1
i 1,2, , Nˆ , at time instant t kT T , can be
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Then, the fast sampled output sequence gathered as
(37)
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yd( N1ˆ ) yd 1 (kT T TNˆ ) C1 xd 1 (kT T TNˆ ) ( Nˆ 1) y (kT T 2T ) C x (kT T 2T ) d1 1 d1 Nˆ Nˆ yd 1 Dxd 1 (kT T ) Eud 1 (kT NT ) YF ˆ ˆ yd(2)1 yd 1 (kT T ( N 1)TNˆ ) C1 xd 1 (kT T ( N 1)TNˆ ) (1) y (kT T NT ˆ ˆ ) C x (kT T NT ˆ ˆ) N N yd 1 d 1 1 d1 ˆ
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T
and
T
(C1H1( N ) )T , where G1( i ) eiA T and H1( i ) (G1( i ) I ) A11B1 , Then, ˆ
1
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E (C1H1( ) )T (C1H1( 2 ) )T
from (37), we have
(C1G1( N ) )T
(C1G1( 2 ) )T
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where D (C1G1( ) )T
xd 1 (kT T ) D YF Eud 1 (kT NT )
(38)
where D ( DT D)1 DT , rank ( D) n1 and n1 is the dimension of the system (1). Thus, for digital
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implementation, we can use the exactly reconstructed state in (38) to substitute for the unknown state in the control law (28).
5. Illustrative example Consider the Smith predictor control system give in [18] and as shown in Fig. 1, in which the controller G2 ( s ) is pre-designed as PID form and the transfer functions of the plant and controller are given as
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G1 ( s)
6000 , 2 ( s 32.44s 20)(s 30)
G2 ( s)
s 2 10.42s 20 s( s 10)
(39)
The state-space models of G1 ( s) and G2 ( s) are xc1 (t ) A1 xc1 (t ) B1uc1 (t Td )
(40a)
yc1 (t ) C1 xc1 (t ) xc 2 (t ) A2 xc 2 (t ) B2uc 2 (t )
where
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yc 2 (t ) C2 xc 2 (t ) D2uc 2 (t )
(40b)
62.44 993.20 600 1 1 10 0 A1 1 0 0 B 0 B2 , , 1 , C1 0 0 6000 , A2 1 0 , 0 1 0 0 0
extended system in Fig. 1 can be represented as
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C2 0.42 20 and D2 1 . The dead time Td 0 is to be assigned. The state-space model of the
xec (t ) Ae xec (t ) Beuc1 (t Td ) Fˆec rˆ(t )
(41a)
uc1 (t ) Kec xec (t ) Eec rˆ(t )
(41b)
yc1 (t ) Ce xec (t )
(41c)
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where rˆ(t ) Ec r(t ) , Td ( N )T , N 0 , 0 1 and
0 ˆ Fec B2 , B1D2
0 0 A1 Ae B2C1 A2 B2C1 , B1D2C1 B1C2 A1 B1D2C1
Kec D2C1
D2C1 , Eec D2 , and Ce C1 0 0 . The parameters of the control law for the
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C2
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xc1 (t ) xec (t ) xc 2 (t ) , xc 3 (t )
B1 Be 0 , B1
Fec Fˆec Ec ,
system with a long input dead time Td 0 in (41) is determined as
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Kec D2C1 C2 D2C1 0 0 6000 0.4 20 0 0 6000 ,
1
Ec Ce ( Aec )1 Bec 1 , Eec 1 .
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Ked 2.6414 213.4406 5671.0939 0.9268 18.2797 2.6414 213.4406 5671.0939 , Eed 0.9537 .
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1.2
1
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Magnitude
0.8
0.6
0.4
0.2
y for N=5 d
0
0
2
4
6
8
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y for N=10
10 Time (sec)
12
14
16
d
18
20
Fig. 3 Output responses for Case 1 and Case 2
In the simulations, we consider two cases of the long input delays: Case 1: Td ( N )T 0.57 , where N 5 , 0.7 and T 0.1s .
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Case 2: Td ( N )T 1.07 , where N 10 , 0.7 and T 0.1s .
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where the sampling period is T 0.1s , which is lying in the range [1] of T [(3-10)b ] 0.033s-0.11s , where b 9.56 rad s is the bandwidth of the delay-free system. When T 0.035s
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and Td NT 0.175s with N 5 , the digitally redesigned system exhibits fairly good response. However, when T 0.1s and Td NT 0.5s with N 5 , the digitally redesigned system in [18]
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exhibits unstable response.
For Case 1, the parameters in the digital control law (28) are obtained as
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Kˆ ed 0.2375 15.7858 269.0096 0.2976 3.1528 0.2375 15.7858 269.0096 , F6 3.6840e-14 ,
F5 1.1130e-13 , F4 2.4275e-14 , F3 2.1439e-13 , F2 2.8911e-13 , F1 2.1813e-12 and
Hˆ er( N ) 0.8828 . Also, ( Gec Ge H e Ked ) Gec 100% 2.1351% % , where 5 . For Case 2, the parameters in the digital control law (28) are obtained as Kˆ ed 0.1511 9.0032 114.7063 0.1050 0.7458 0.1511 9.0032 114.7063 ,
F11 1.5584e-14 ,
F10 2.4528e-15 ,
F6 1.1210e-13 ,
F9 2.1694e-14 ,
F8 1.4918e-13 ,
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F7 8.7792e-14 ,
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F5 1.1130e-13 , F4 2.4275e-14 , F3 2.1439e-13 , F2 2.8911e-13 , F1 2.1813e-12 and
Hˆ er( N ) 0.8691 . It is noticed that Fi , for i 1,2
,5 , are the same as those in Case 1. Also,
( Gec Ge H e Ked ) Gec 100% 2.1353% % , where 5 .
The simulation results for Case 1 and Case 2 are shown in Figs. 3-5, in which the output responses of Case 1 and Case 2 are depicted in Fig. 3, and the state responses are given in Fig. 4 and Fig. 5,
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respectively. It can be seen from the simulation results that the plant outputs track the constant reference input r(t ) 1 closely for both long input time delay cases with N 5 and N 10 for the same 0.7 and T 0.1s . Furthermore, the digitally reconstructed states xri , for i 1,2 , produced by the ideal state reconstructor, match the real plant states xci closely. -4
5
0
0.5
x 10
1
0.5
x 10
1
-4
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0
2
2.5 Time (sec)
3
3.5
4
x
r1
4.5
1
1.5
2
2.5 Time (sec)
0
0.5
1
5
xc2 xr2
3
3.5
4
4.5
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Magnitude
2
0
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0.5
0
1.5
-4
xc1
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0 -2
1
Magnitude
x 10
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Magnitude
10
5
xc3 x
r3
1.5
2
2.5 Time (sec)
3
3.5
4
4.5
5
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Fig. 4 State responses of Case 1 ( xci : state of the plant; xri : reconstructed state)
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10
-4
Magnitude
xc1 x
5 0 -2
1
r1
0
0.5
x 10
1
1.5
2
-4
2.5 Time (sec)
3
3.5
4
4.5
5
x
r2
0.5
0
Magnitude
2
0
0.5
x 10
1
1.5
2
-4
2.5 Time (sec)
3
1
0
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xc2
0
0.5
1
1.5
2
3.5
4
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Magnitude
x 10
2.5 Time (sec)
3
3.5
4
4.5
5
xc3 x
r3
4.5
5
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Fig. 5 State responses of Case 2 ( xci : state of the plant; xri : reconstructed state)
6. Conclusions
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The prediction-based state-matching digital redesign method has been developed in [13] for the discretization of the analog Smith predictor for the systems with various input dead times. Various digital controllers have been developed according to the lengths of input delay times. In this paper, by
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extending the method developed for the delay-free systems [19, 20] to that for the time-delay ones, a Chebyshev quadrature state-matching digital redesign method has been proposed to find a simple
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digitally redesigned controller for the analog Smith Predictor with either a short dead time or a long one. In addition, the proposed ideal state reconstructor has extended the method developed for
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delay-free systems [21] to the time-delay systems. An illustrative example has been given to show the effectiveness of the proposed approach.
Acknowledgement This work was supported by the National Natural Science Foundation of the People’s Republic of China under grant numbers 61374047, 61273131 and National Science Council of Republic of China under contract NSC102-2221-E-006-208-MY3. 16
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References
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[1] K.J. Astrom, Computer-controlled Systems: Theory and Design, Prentice Hall, Upper Saddle River, New Jersey, 1997. [2] B.C. Kuo, Digital Control Systems, Holt, Rinehart and Winston, 1980. [3] J.P. Richard, Time-delay systems: An overview of some recent advances and open problems, Automatica 39 (2003) 1667-1694. [4] A. Seshagiri Rao, V.S.R. Rao, M. Chidambaram, Direct synthesis-based controller design for integrating processes with time delay, J. Frankl. Inst. 346 (2009) 38-56. [5] O.J. Smith, Closer control of loops with dead time, Chem. Eng. Progress 53 (1957) 217-219. [6] W. Xie, G.L. Li, GIMC architecture for linear systems with a single I/O delay, J. Frankl. Inst. 349 (2012) 2151-2162. [7] J. Herrera, A. Ibeas, S. Alcántara, M. de la Sen, S.I. Serna-Garcés, Identification and control of delayed SISO systems through pattern search methods, J. Frankl. Inst. 350 (2013) 3128-3148. [8] K.J. Astrom, C.C. Hang, B.C. Lin, A new Smith predictor for controlling a process with an integrator and long dead-time, IEEE Trans. Autom. Control 39 (1994) 343-345. [9] H.Q. Zhou, Q.G. Wang, L. Min, Modified Smith predictor design for periodic disturbance rejection, ISA Trans. 46 (2007) 493-503. [10] A.S. Rao, M. Chidambaram, Analytical design of modified Smith predictor in a two-degree-of-freedom control scheme for second order unstable processes with time delay, ISA Trans. 47 (2008) 407-419. [11] B. Zhang, W.D. Zhang, Two-degree-of-freedom control scheme for processes with large time delay, Asian J. Control 8 (2006) 50-55. [12] D.G. Padhan, S. Majhi, Modified Smith predictor based cascade control of unstable time delay processes, ISA Trans. 51 (2012) 95-104. [13] C.C. Hang, Q.G. Wang, X.P. Yang, A modified Smith predictor for a process with an integrator and long dead time, Ind. Eng. Chem. Res. 42 (2003) 484-489. [14] Q.C. Zhong, G. Weiss, A unified smith predictor based on the spectral decomposition of the plant, Int. J Control. 77 (2004) 1362-1371 [15] M.R. Matausek, A.D. Micic, On the modified Smith predictor for controlling a process with an integrator and long dead-time, IEEE Trans. Autom. Control 44 (1999) 1603-1606. [16] H. Fujimoto, A. Kawamura, M. Tomizuka, Generalized digital redesign method for linear feedback system based on N-delay control, IEEE/ASME Trans. on Mechatronics 4 (1999) 101-109. [17] Y.P. Zhang, L.S. Shieh, C.R. Liu, S.M. Guo, Digital PID controller design for multivariable analogue systems with computational input-delay, IMA J. Math. Control Info. 21 (2004) 433-456. [18] A.C. Dunn, L.S. Shieh, S.M. Guo, Digital redesign of analog Smith predictor for systems with input time delays, ISA Trans. 43 (2004) 33-47. [19] A. Ralston, A First Course in Numerical Analysis, McGraw-Hill, New York, 1965. [20] L.S. Shieh, W.M. Wang, M.K. Appu Panicker, Design of PAM and PWM digital controllers for cascaded analog systems, ISA Trans. 37 (1998) 201-213. [21] M.E. Polites, Ideal state reconstructor for deterministic digital control systems, Int. J. Syst. Sci. 49 (1989) 2001-2011.
Appendix A: Ideal state reconstructor for case (ii) ( 1/ 2 1 ) of long input time delay Considering the discretized system (29) and the multirate sampling sequence shown in Fig. 6 with 1/ 2 1 , TNˆ T Nˆ T ( Nˆ n1 ) and Td ( N )T , we have
xd 1 (kT T TNˆ ) G1( ) xd 1 (kT T ) H1( )ud 1 (kT NT )
17
(A.1)
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where G1( ) e
, H1( ) (G1( ) I ) A11B1 . By successively shifting (A.1) forward by TNˆ , we obtain
A1TNˆ
xd 1 (kT T 2TNˆ ) G1( ) xd 1 (kT T TNˆ ) H1( )ud 1 (kT NT ) G1(2 ) xd 1 (kT T ) H1(2 )ud 1 (kT NT )
where G1(2 ) e
A1 2TNˆ
, H1(2 ) (G1(2 ) I ) A11B1 , and in general, xd 1 (kT T iTNˆ ) G1(i ) xd 1 (kT T ) H1(i )ud 1 (kT NT )
(A.3)
, H1(i ) (G1(i ) I ) A11B1 , with i 1,2, , Nˆ . The sampled output sequence yd(i1) ,
for i 1,2, , Nˆ , at time instant t kT T , can be gathered as ud1(kT NT T )
ud1(kT NT )
ud1(kT NT T)
TNˆ
yd1(t) {YF}
···
kT 2T
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kT T kTT
kT
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where G1( i ) e
A1iTNˆ
(A.2)
kT T T
kT2TT
Fig. 6 Multirate sampling sequence for ideal state reconstructor (case (ii))
ˆ ˆ ) C x (kT T NT ˆ ˆ) y yd 1 (kT T NT 1 d1 N N ( Nˆ 1) ˆ ˆ yd 1 yd 1 (kT T ( N 1)TNˆ ) C1 xd 1 (kT T ( N 1)TNˆ ) YF Dxd 1 (kT T ) Eud 1 (kT NT ) (A.4) (1) yd 1 yd 1 (kT T TNˆ ) C1 xd 1 (kT T TNˆ )
where D (C1G1( N ) )T ˆ
ˆ
E (C1H1( N ) )T (C1H1(( N 1) ) )T ˆ
T
(C1G1( ) )T , T
(C1H1( ) )T . Then, from (A.4), we obtain xd 1 (kT T ) D YF Eud 1 (kT NT )
PT
ˆ
ED
(C1G1(( N 1) ) )T
M
( Nˆ ) d1
AC
CE
where D ( DT D)1 DT , rank ( D) n1 and n1 is the order of system (1) .
18
(A.5)
Digital Redesign of Analog Smith Predictor for Systems with Long Input Time Delays Linbo Xie , Leang-San Shieh , Jason Sheng-Hong Tsai , Shu-Mei Guo , Alex C Dunn PII: DOI: Reference:
S0016-0032(17)30328-9 10.1016/j.jfranklin.2017.07.014 FI 3053
To appear in:
Journal of the Franklin Institute
Received date: Revised date: Accepted date:
1 August 2016 21 April 2017 1 July 2017
Please cite this article as: Linbo Xie , Leang-San Shieh , Jason Sheng-Hong Tsai , Shu-Mei Guo , Alex C Dunn , Digital Redesign of Analog Smith Predictor for Systems with Long Input Time Delays, Journal of the Franklin Institute (2017), doi: 10.1016/j.jfranklin.2017.07.014
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Digital Redesign of Analog Smith Predictor for Systems with Long Input Time Delays Linbo Xiea, Leang-San Shiehb, Jason Sheng-Hong Tsaic, Shu-Mei Guod, Alex C. Dunne
b
c
Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77204-4005, USA ([email protected])
(Corresponding author)Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan, ROC ([email protected])
d
e
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Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education) Jiangnan University, Wuxi, 214122, Jiangsu, China ([email protected])
Department of Computer Science and Information Engineering, National Cheng-Kung University, Tainan 701, Taiwan, ROC ([email protected])
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a
United States Patent and Trademark Office (USPTO), Alexandria, United States ([email protected])
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Abstract The discretization of the analog Smith predictor by using the prediction-based state-matching digital redesign method for systems with various input time delays was recently investigated in the literature. This paper presents an alternative Chebyshev quadrature state-matching digital redesign method for discretization of the analog Smith predictor for systems with a long input time delay. In order to implement the digitally redesigned Smith predictor by utilizing the output-feedback of the plant, an ideal state reconstructor for the long input-delayed plant is established. The long dead time of interest is an integer plus a fractional input delay. An illustrative example is given to demonstrate the effective of the proposed approach.
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Keywords Smith predictor; Digital redesign; Long time delay; Input delay system; Sampled-data system
1. Introduction
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A time delay is often encountered in many practical processes, such as industrial processes, engineering systems, economical and biological systems. Such time delay is seen for example in the transport delay in a reactor, process piping, or the approximated modelling of high-order systems with low-order models with delays, such as the first-order plus dead time (FOPDT) and the second-order plus dead time (SOPDT) [1-3]. Various popular methods have been developed and several open problems have been raised in an effort to improve the performance of time-delay systems [3, 4]. The Smith predictor [5-7] is one of the most popular methods for solving time-delay problems in industry
1
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and several extensions and modifications, such as the internal model control (IMC) [8-15] have been proposed to improve the performance of the Smith predictor. The resulting analog Smith predictor is often required to be digitally implemented for better reliability, lower cost, smaller size, more flexibility and better performance. A detailed explanation of the advantages of the digital controller over the analog one can be found in [2, 16]. In the literature, the Smith predictor is usually represented
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in the frequency domain by its transfer function. For digital implementation, it is desirable to obtain the time-domain representation such as the state-space model of the Smith predictor. The prediction-based state-matching digital design method together with various case studies on the lengths of the input dead times were investigated in [17, 18] for the systems with relatively short dead times. For instance, the prediction-based state-matching digital redesign method proposed in [17, 18] works well for the input-delayed system with the integer delay part N 0 and the fractional delay part 0 in the time
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delay Td ( N )T , where T is the sampling period. However, it was reported in [18] that when the input dead time is relatively long, the digitally redesigned sampled-data system exhibits unstable response. In general, the integer part can be easily converted into its digital equivalent, but this is not the case with the fractional part. When this fractional delay cannot be ignored or cannot be effectively
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approximated by means of any method (such as Pade’s method), it must be considered and included in both the digital redesign and the ideal state reconstruction, for sampled-data control of the time-delay
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systems.
It is generally known that the Smith predictor can simplify the design of systems with input/output delays [4-15], using the knowledge of the output dead times and feedback control law of the plant. In
PT
addition, the mismatch between the internal model used for the prediction-based control and its actual plant may destabilize the whole closed-loop system. In order to discretize the analog Smith predictor
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using the reformulated augmented system, the extended state of the plant is required for the development and implementation of the digital counterpart of the designed analog Smith predictor. If
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the state of the plant is not available, then a state estimator such as an observer is naturally required to estimate the plant states. In this case, additional dynamics would be introduced in the closed-loop system and the dimension of the resulting system could become very high. In this paper, a simple and unique digital redesign method via the Chebyshev quadrature formula
[19, 20] is developed to find the digitally redesigned Smith predictor for systems with long input dead times. First, the designed analog Smith predictor together with the plant is reformulated into a state-augmented system with long input time delay. Then, an alternative Chebyshev quadrature state-matching digital redesign method is developed to obtain the digital counterpart by extending the 2
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method developed for the delay-free systems [19, 20] to long time-delay systems. If the states of the input time-delay plant are not available for measurement and for the output feedback requirement of the digitally redesigned Smith predictor, an ideal state reconstructor, which takes advantage of the multirate sampling technique, for the aforementioned augmented time-delay system is developed. The advantages of using the multirate sampling technique for the ideal state reconstruction are: (i) it does
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not introduce additional dynamics in the closed-loop system as is the case with the traditional observer; (ii) it decreases the dimension and complexity of the overall system; and (iii) it allows the utilization of the state feedback controller without an observer. The paper concludes with an illustrative example to demonstrate the effectiveness of the developed approach.
2. Problem formulation
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Consider that the Smith predictor can be designed as shown in Fig. 1, where G1 ( s)e sTd is a time-delay analog plant with long input time delay Td ( N )T , where N 0 is the integer delay part; 0 1 is the fractional delay part and T the sampling period.
Ec
e( t )
uc2 (t)
G1 ( s )
uc3 (t )
uc1 (t )
yc2(t)
G1(s)e sTd
yc1(t )
1 e sTd
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yc3 (t )
G2 ( s )
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r (t )
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Fig. 1 Smith predictor formulation
The state-space representations of the subsystems in Fig. 1 are given in the following.
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G2 ( s ) :
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G1 ( s)e sTd :
G1 ( s) 1 e sTd :
xc1 (t ) A1 xc1 (t ) B1uc1 (t Td ) yc1 (t ) C1 xc1 (t ) xc 2 (t ) A2 xc 2 (t ) B2uc 2 (t ) yc 2 (t ) C2 xc 2 (t ) D2uc 2 (t ) uc1 (t ) xc 3 (t ) A1 xc 3 (t ) B1 uc1 (t ) uc1 (t Td ) yc 3 (t ) C1 xc 3 (t )
(1)
(2)
(3)
where xc1 (t ) R n1 , xc 2 (t ) R n2 , xc 3 (t ) R n1 , uc1 (t ) R m1 , uc 2 (t ) R p1 , uc 3 (t ) R m1 , yc1 (t ) R p1 , yc 2 (t ) R m1 and yc 3 (t ) R p1 . The matrices ( A1, B1, C1, A2 , B2 , C2 , D2 ) are of appropriate dimensions.
From Fig. 1, we obtain the input-output transfer function 3
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yc1 ( s ) G2 ( s )G1 ( s)e sTd Ec r ( s ) 1 G2 ( s)G1 ( s)(1 e sTd )
If we set Td 0 in (4), then we have
G2 ( s )G1 ( s)e sTd G2 ( s)G1 ( s)e sTd 1 sTd 1 G2 ( s)G1 ( s)(1 e ) 1 G2 ( s )G1 ( s)
(4)
yc1 ( s ) G2 ( s )G1 ( s ) . Hence, the numerator polynomial of Ec r ( s ) 1 G2 ( s )G1 ( s )
1 G2 (s)G1 (s) is the denominator polynomial of the transfer function Yc1 (s) /( Ec r (s)) in (4) with Td 0 .
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The stabilizing controller G2 ( s) should make such transfer function stable. In the time-domain, the corresponding augmented state-space equations for (1)-(3) can be represented as xec (t ) Ae xec (t ) Beuc1 (t Td ) Fˆec rˆ(t )
(5a)
uc1 (t ) Kec xec (t ) Eec rˆ(t )
(5b)
yc1 (t ) Ce xec (t )
0 xc1 (t ) A1 xec (t ) xc 2 (t ) , Ae B2C1 A2 xc 3 (t ) B1D2C1 B1C2
0 B1 0 ˆ B2C1 , Be 0 , Fec B2 , Fec Fˆec Ec , Eec D2 , A1 B1D2C1 B1 B1D2
D2C1 , and Ce C1 0 0 . When Td 0 , the transfer function of the closed-loop
system in (5) becomes
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Kec D2C1 C2
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where rˆ(t ) Ec r(t ) , and
(5c)
yc1 ( s ) G2 ( s )G1 ( s ) , and it is stable and can be represented from (5) as Ec r ( s ) 1 G2 ( s )G1 ( s )
ED
yc1 (t ) Ce sI n ( Ae Be Kec ) ( Be Eec Fˆec )rˆ( s) Ce sI n Aec Bec Ec r( s) 1
(6)
Bec Be Eec Fˆec . The characteristic equation
Aec Ae Be Kec , and
PT
where rˆ( s) Ec r( s) ,
1
( det( sI n Aec ) 0 ) of the system in (6) is asymptotically stable. As a result, the closed-loop system
CE
matrix Aec is asymptotically stable. In order to retain the stability of Aec in (5) for Td 0 , the control
AC
law in (5b) should be expressed as uc1 (t ) Kec xec (t Td ) Eec rˆ(t Td )
(7a)
or
uc1 (t Td ) Kec xec (t ) Eec rˆ(t )
(7b)
where rˆ(t ) Ec r (t ) and r (t ) is a unit-step reference input. Since rˆ(t ) is a constant reference input for t 0 , the predicted constant reference input rˆ(t Td ) will be equal to rˆ(t ) . The objective of this paper is to digitally redesign the analog Smith predictor control system (5) so that the analog and the
4
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discrete states match each other closely for the long input time delay Td . Suppose the corresponding closed-loop hybrid systems of (5) with Td 0 and t kT is represented as xed (t ) Ae xed (t ) Beud 1 (t Td ) Fˆec rˆ(t )
(8a)
ud 1 (kT ) Ked xed (kT Td ) Eed rˆ(kT )
(8b)
where ud 1 (kT ) R m is a piecewise-constant signal after a zero-order hold with the sampling period T ,
CR IP T
the xed (kT Td ) in (8b) is the discretization of the analog state xec (t Td ) in (7a), and the digital gains ( Ked , Eed ) in (8b) can be approximately obtained from the analog gains ( Kec , Eec ) in (7a) or (5b) via the Chebyshev quadrature digital redesign method described in the following Section 3.
In [18], it was intended to assume that if the dead time Td in (7) is sufficiently small ( Td 1 ) and
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the state xec (t ) in (5b) can be approximately equal to xec (t Td ) in (7a), as a result, the uc1 (t ) in (5b) can be approximately represented as
uc1 (t ) Kec xec (t Td ) Eec rˆ(t ) for Td 1
(8c)
Substituting (8c) into (5a) results in the closed-loop system matrix as ( Ae Be Kec ) . If ( Ae Be Kec ) is
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still asymptotically stable, then various prediction-based digital control laws ud 1 (kT ) in (8b) were redesigned according to the length of various dead time Td for digital control of the sampled-data
ED
system in (8). In this paper, the Chebyshev quadrature digital redesign method is utilized to develop a simple and unique digital control law ud 1 (kT ) in (8b) for any length of the dead time Td in the
PT
following.
3. Chebyshev quadrature digital redesign method
CE
3.1 Chebyshev quadrature formulation The discrete-time solution of xec (t ) at time instant t kT T in (5a) with Td 0 is
AC
xec (kT T ) e AeT xec (kT )
kT T
e Ae ( kT T ) Beuc1 ( )d
kT
kT T
e Ae ( kT T ) Fˆec rˆ( )d
(9)
kT
The right-hand side of (9) can be approximately evaluated by the Chebyshev quadrature equation [19, 20]. The general Chebyshev quadrature formula can be re-formulated for utilization of digital redesign as
5
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b
a
N
N b b 1 1 N ( ) d f ( ) ( ) d lim f (i ) i a N N 1 N 1 a i 0 i 0
( ) f ( )d W f (i ) i 0
N b N (b a ) 1 b ( )d lim f (i ) ( )d f ( )d a a N ( N 1)( b a ) N b a a i 0
(10)
b
where ( ) is a constant sign weighting function in [a, b] , W is the weighting factor determined b 1 ( )d , and N 1 a
f (i ) are the values of the function
f ( )
evaluated at
CR IP T
by W
i a i(b a) N , for i 0,1, , N . 3.2 Approximate discrete-time model
According to (10), the first integral term in the right-hand side of (9) can be represented as
kT
where H e
kT T
kT
e
kT T 1 kT T e Ae ( kT T ) Beuc1 ( )d e Ae ( kT T ) Bed uc1 ( )d H euc1 (t ) kT T kT
Ae ( kT T )
(11)
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kT T
Bed [Ge I n ] A B , Ge e 1 e e
AeT
1 and uc1 (t ) T
kT T
uc1 ( )d . It is noticed that when
kT
i Ae is a singular matrix, the matrix H e Ge I n Ae1Be becomes H e T i 0 AeT (i 1)!Be .
M
Hence, the discrete-time solution of (9) at t kT T is
where H er
kT T
kT
(12)
ED
xec (kT T ) Ge xec (kT ) H euc1 (t ) H er rˆ(kT )
e Ae ( kT T ) Fˆec d [Ge I n ] Ae1Fˆec and rˆ(kT ) is the piecewise-constant reference
PT
input. Discretization of (8a) and (8b) with both Td 0 yields kT T
CE
xed (kT T ) e AeT xed (kT )
e Ae ( kT T ) Beud 1 ( )d
kT
kT T
e Ae ( kT T ) Fˆec rˆ( )d
kT
(13)
Ge xed (kT ) H eud 1 (kT ) H er rˆ(kT )
AC
Comparing (12) and (13), we observe that if we let xec (kT T ) in (12) approximately equal to xed (kT T ) in (13) and xec (kT ) in (12) approximately equal to xed (kT ) in (13), then uc1 (t ) in
(12) would be approximately equal to ud 1 (kT ) in (13). As a result, uc1 (t ) in (12) can be approximately evaluated from (11) and (7a) with Td 0 as
uc1 (t )
1 T
kT T
uc1 ( )d
kT
6
Kec T
kT T
kT
xec ( )d Eec rˆ(kT )
(14)
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3.3 The improved digital redesign method The integral term in the right-hand side of (14) can be exactly evaluated by integrating the closed-loop system of (5a) and (7a) with Td 0 as kT T
kT T
xec (t )dt Aec
kT
xec ( )d ( Be Eec Fˆec )
kT
kT T
rˆ( )d
(15)
kT
kT T
x
ec
CR IP T
The first integral term in the right-hand side of (15) can be solved from (15) as
( )d Aec1[ xec (kT T ) xec (kT ) T ( Be Eec Fˆec )rˆ(kT )]
kT
Substituting (16) into (14), we have
uc1 (t ) Kec ( AecT )1[ xec (kT T ) xec (kT ) T ( Be Eec Fˆec )rˆ(kT )] Eecrˆ(kT )
(16)
(17)
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Since it is desired to closely match the xed (t T ) and xed (t ) in (13) with the xec (t T ) and xec (t ) in (12), respectively, with a little abuse of the notation we consider xec (t T ) xed (t T ), xec (t ) xed (t ) and uc1 (kT ) ud1 (kT ). Then, (17) becomes
Substituting (13) into (18), we have
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ud 1 (kT ) Kec ( AecT )1[ xed (kT T ) xed (kT ) T ( Be Eec Fˆec )rˆ(kT )] Eecrˆ(kT ) ud 1 (kT ) Kec ( AecT )1 (Ge I n ) xed (kT ) H eud 1 (kT ) ( H er TBec )rˆ(kT ) Eecrˆ(kT )
(18)
(19)
ED
Solving ud 1 (kT ) from (19) and equating its result to the digital control law in (8b) with Td 0 gives ud 1 (kT ) Ked xed (kT ) Eed rˆ(kT )
PT
where
Ked [ I m Kec ( AecT )1 H e ]1 Kec ( AecT )1 (Ge I n )
CE
Eed [ I m Kec ( AecT )1 H e ]1 Eec Kec ( AecT )1 ( H er TBec )
(20)
(21a) (21b)
AC
where Aec Ae Be Kec , Ge e AeT , H e (Ge I n ) Ae1Be , H er [Ge I n ] Ae1Fˆec and Bec Be Eec Fˆec . The digital control gains ( Ked , Eed ) obtained in (21) can be further simplified as follows. Substituting (5b) into (5a) with Td 0 yields the closed-loop system as xec (t ) Aec xec (t ) Bec rˆ(t ) Aec xec (t ) Bec Ec r (t ) yc1 (t ) Ce xec (t )
7
(22a)
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For tracking the unit-step reference input r (t ) in (22a) and by applying the final-value theorem to (22a), we can determine the reference input gain Ec in (22a) for a multivariable system with
yc1 (t ) R p1 , r(t ) R m1 and p1 m1 as Ec Ce ( Aec ) 1 Bec
1
(22b)
CR IP T
Since xec (t T ) xed (t T ) and xec (t ) xed (t ) , the discretization of (22a) becomes xed (kT T ) Gec xed (kT ) H ec rˆ(kT )
(23)
where Gec e AecT e( Ae Be Kec )T , and H ec (Gec I n ) Aec1Bec . Also, the discretization of (5a) with Td 0 gives
xed (kT T ) Ge xed (kT ) H eud 1 (kT ) H er rˆ(kT )
(24a)
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where Ge e AeT , H e (Ge I n ) Ae1Be , and H er (Ge I n ) Ae1Fˆec . Substituting (8b) with Td 0 into (24a) results in
xed (kT T ) (Ge H e Ked ) xed (kT ) ( H e Eed H er )rˆ(kT )
Comparing (24b) with (23) yields
(24b)
Gec Ge H e Ked and H ec H e Eed H er
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(24c)
Pre-multiplying both sides of (21a) with
I
m
m
Kec ( AecT )1 H e and utilizing the relationship obtained
Kec ( AecT )1 H e Ked Kec ( AecT )1 Ge I n or
ED
in (24c) gives
I
PT
Ked Kec ( AecT )1 Ge I n H e Ked Kec ( AecT )1 (Gec I n )
CE
Hence
(25a)
Ked Kec ( AecT )1 (Gec I n )
where Aec Ae Be Kec . Also, pre-multiplying both sides of (21b) with
(25b)
I
m
Kec ( AecT )1 H e and
AC
using the relationship in (24c) gives
I
m
Kec ( AecT )1 H e Eed Eec Kec ( AecT )1 ( H er TBec )
or
Eed Eec Kec ( AecT ) 1 H er Kec Aec1Bec Kec ( AecT ) 1 ( H ec H er ) Eec Kec Aec1Bec Kec ( AecT )1 (Gec I n ) Aec1Bec Eec ( Kec Ked ) Aec1Bec
Hence,
8
(25c)
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Eed Eec ( Kec Ked ) Aec1Bec
(25d)
3.4 Digital redesign for a long time-delay system For Td ( N )T 0 , N 0 , 0 1
and rˆ(kT ) Ec r (kT ) , the digitally redesigned control law
in (8) with Td 0 becomes ud 1 (kT ) Ked xed (kT Td ) Eed rˆ(kT )
(26)
CR IP T
The discrete-time state xed (kT Td ) in (26) with Td 0 is the discretization of the analog state xec (t Td ) in (7a) with Td 0 and can be determined from (5a) with Td 0 as follows:
xed (kT Td ) e
AeTd
xed (kT )
kT Td
e
Ae ( kT Td )
Beud 1 ( Td )d
kT Td
kT
kT kT
e Ae ( kT ) Beud 1 ( )d
kT NT T kT NT
kT NT T
kT Td
e Ae ( kT Td ) Fˆecd rˆ(kT )
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e Ae ( N )T xed (kT ) Ge( N ) xed (kT )
e Ae ( kT Td ) Fˆec rˆ( )d
kT
N
e Ae ( kT ) Beud 1 ( )d i 1
kT iT T
kT iT
T
d e Ae ( kT ) Beud 1 ( )d e Ae Fˆecd rˆ(kT )
Ge( N ) xed (kT ) Ge( N ) H e( )ud 1 (kT NT T ) Ge( N 1) H e(1)ud 1 (kT NT )
0
H eud 1 (kT T ) H er( N )rˆ(kT ) (27)
M
where Ge( N ) e Ae ( N )T , H e( ) (Ge( ) I n ) Ae1Be , H e(1) (Ge(1) I n ) Ae1Be H e and H er( N ) (Ge( N ) I n ) Ae1Fˆec . Substituting (27) into (26) results in the desirable digitally redesigned control law for the long
ED
time-delayed analog control law in (4a) with Td 0 as ud 1 (kT ) Kˆ ed xed (kT ) FN 1ud 1 (kT NT T ) FN ud 1 (kT NT ) N 1
F1ud 1 (kT T ) ( Eed Hˆ er( N ) )rˆ(kT )
PT
Kˆ ed xed (kT ) Fi ud 1 (kT iT ) ( Eed Hˆ er( N ) )rˆ(kT ) i 1
CE
(28)
where Kˆ ed Ked Ge( N ) , FN 1 Ked Ge( N ) H e( ) , FN Ked Ge( N 1) H e ,…, F1 Ked H e , Hˆ er( N ) Ked H er( N ) ,
AC
rˆ(kT ) Ec r(kT ) , and r(kT ) is a unit-step reference input function. The digital gains K ed and Eed
in (28) can be found in (25b) and (25d), respectively, and Ec is determined from (22b). It is noticed that when T 0 , the digitally redesigned gains ( Ked , Eed ) in (25b) and (25d) can be reduced to the analog gains ( Kec , Eec ) in (5b), respectively.
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3.5 Improvement of the existing method in [18] Now, from (5), (8c) and (27), it can be concluded that for the prediction-based state-matching digital redesign method proposed in [18] to work well, it is not only required for the dead time Td ( N )T to be very small, but also the integer N in the Td must be sufficient small, such that the percentage error
between
the
analogously
controlled
system
and
the
digitally
redesigned
system
CR IP T
( Gec Ge H e Ked ) Gec 100% % in (24c) (for instance 5 ), where the digitally redesigned
gain K ed is obtained in [18]. For example, the prediction-based state-matching digital redesign method proposed in [17, 18] works well for the input-delayed system with N 0 and 0 in Td . Nevertheless, when the integer N in Td is not sufficiently small, there exists a large discrepancy
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between the discretized state xed (kT Td ) in (25), (which is set to be equal to the analog state xec (t Td ) at t kT and Td ( N )T in (8c) or the state xec (t Td ) in
(5a) via the state-matching
digital redesign method proposed in [18]), and the analog state xec (t ) at t kT in (5b). In other words, the prediction-based state-matching digital redesign method proposed in [18] works well, if the sampling period T lies within (3-10)b , (where the b is the bandwidth), and both the dead
M
time Td and the integer N in Td are sufficiently small, such that both the state xec (t Td ) in (5a)
ED
the state xec (t ) in (5b) and the percentage error ( Gec Ge H e Ked ) Gec 100% % in (24c). This is evident in the simulations shown in Fig. 9 in [18], in which (i) the performance of the response is fairly good for Td ( N )T 0.192 1 , where T 0.035s , 0.49 and N 5 , and (ii) the
CE
and N 10 .
PT
performance of the response is degraded for Td ( N )T 0.367 1 , where T 0.035s , 0.49
4. Ideal state reconstructor for long input time delay
AC
If the state of the plant xed 1 (t ) , which is contained in the extended state xed (t ) in (8) and is required for the implementation of (28), is not available, the following multirate sampling technique (called the ideal state reconstructor for a long input-delay system) is applied within one sampling period to reconstruct the ideal (exact) state xed 1 (kT ) , i.e., with the errors in the states going to zero in one sample period. It should be noted that xed 2 (kT ) and xed 3 (kT ) contained in xed (kT ) are the states of the digital Smith predictor, which are always realizable and available. To increase the accuracy in reconstructing the ideal state in (28), two cases are considered regarding the value of : (i) 10
ACCEPTED MANUSCRIPT
0 1/ 2 and (ii) 1/ 2 1 . The method for reconstructing the ideal state for case (ii) is developed
in Appendix A. ud 1 ( kT NT )
ud1(kT NT T )
ud1(kT NT T )
TNˆ
yd1(t) ·······
kT TNˆ kT
kT T
CR IP T
fast sampled data {YF}
kT T kT T T
Fig. 2 Multirate sampling sequence for ideal state reconstructor (case (i))
Suppose that the discretized counterpart of (1) after a zero-order hold with sampling period T is
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represented as xd 1 (t ) A1 xd 1 (t ) B1ud 1 (t Td )
(29)
yd 1 (t ) C1 xd 1 (t )
where xd 1 (t ) R n1 , yd 1 R p1 , ud 1 (t Td ) R m1 is the digital counterpart of the continuous time (1 )T T is the Nˆ
M
control law uc1 (t Td ) in (1). Consider the case N 0 and 0 1/ 2 , let TNˆ
ˆ ˆ , Nˆ n , T ( N )T , ˆ , and the multirate sampling fast sampling period, T T NT 1 d N
ED
sequence shown in Fig. 2. The solution of (29) at time instants t kT T and t0 kT is given as xd 1 (kT T ) e A1 T xd 1 (kT )
kT T
kT
e A1 ( kT T ) B1ud 1 ( NT T )d
where G1( ) e A T 1
PT
G1( ) xd 1 (kT ) H1( )ud 1 (kT NT T )
and
H1( )
kT T
kT
e A1 ( kT T ) B1d (G1( ) I ) A11B1 . Considering t kT T
(30)
and
CE
t0 kT TNˆ in (12), and since ud 1 (t ) ud 1 (kT NT T ) when t kT TNˆ , kT T , the solution
AC
xd 1 (kT T ) G1(ˆ ) xd 1 (kT TNˆ )
kT T
kT TNˆ
( ˆ ) 1 d1
e A1 ( kT T ) B1d ud 1 (kT NT T )
( ˆ ) 1 d1
(31)
G x (kT TNˆ ) H u (kT NT T )
is found, where H1(ˆ )
kT T
kT TNˆ
e A1 ( kT T ) B1d (e A1ˆT I ) A11B1 (G1(ˆ ) I ) A11B1 . From (31), we obtain
xd 1 (kT TNˆ ) G1( ˆ ) xd 1 (kT T ) G1( ˆ ) H1(ˆ )ud 1 (kT NT T ) , k N where G1( ˆ ) H1(ˆ ) (G1( ˆ ) I ) A11B1 H1( ˆ ) . Substituting xd 1 (kT T ) in (30) into (32), we get
11
(32)
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xd 1 (kT TNˆ ) G1( ) xd 1 (kT ) H1( )ud 1 (kT NT T )
(33)
where G1( ) e A T , H1( ) G1( ˆ ) H1( ) H1( ˆ ) (G1( ) I ) A11B1 . Since it is known that ud 1 (kT NT T ) is 1
piecewise constant (i.e., it is the output of a zero-order hold), then ud 1 (kT NT iTNˆ ) ud 1 (kT NT T ) for 0 i Nˆ . By successively shifting back TNˆ T from (33), we obtain
(34)
xd 1 (kT 3TNˆ ) G1( 3 ) xd 1 (kT ) H1( 3 )ud 1 (kT NT T ) ,
(35)
ˆ ˆ ) G( Nˆ ) x (kT ) H ( Nˆ )u (kT NT T ) . xd 1 (kT NT 1 d1 1 d1 N
(36)
CR IP T
xd 1 (kT 2TNˆ ) G1( 2 ) xd 1 (kT ) H1( 2 )ud 1 (kT NT T ) ,
and in general,
y , for (i ) d1
i 1,2, , Nˆ , at time instant t kT T , can be
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Then, the fast sampled output sequence gathered as
(37)
M
yd( N1ˆ ) yd 1 (kT T TNˆ ) C1 xd 1 (kT T TNˆ ) ( Nˆ 1) y (kT T 2T ) C x (kT T 2T ) d1 1 d1 Nˆ Nˆ yd 1 Dxd 1 (kT T ) Eud 1 (kT NT ) YF ˆ ˆ yd(2)1 yd 1 (kT T ( N 1)TNˆ ) C1 xd 1 (kT T ( N 1)TNˆ ) (1) y (kT T NT ˆ ˆ ) C x (kT T NT ˆ ˆ) N N yd 1 d 1 1 d1 ˆ
CE
T
and
T
(C1H1( N ) )T , where G1( i ) eiA T and H1( i ) (G1( i ) I ) A11B1 , Then, ˆ
1
PT
E (C1H1( ) )T (C1H1( 2 ) )T
from (37), we have
(C1G1( N ) )T
(C1G1( 2 ) )T
ED
where D (C1G1( ) )T
xd 1 (kT T ) D YF Eud 1 (kT NT )
(38)
where D ( DT D)1 DT , rank ( D) n1 and n1 is the dimension of the system (1). Thus, for digital
AC
implementation, we can use the exactly reconstructed state in (38) to substitute for the unknown state in the control law (28).
5. Illustrative example Consider the Smith predictor control system give in [18] and as shown in Fig. 1, in which the controller G2 ( s ) is pre-designed as PID form and the transfer functions of the plant and controller are given as
12
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G1 ( s)
6000 , 2 ( s 32.44s 20)(s 30)
G2 ( s)
s 2 10.42s 20 s( s 10)
(39)
The state-space models of G1 ( s) and G2 ( s) are xc1 (t ) A1 xc1 (t ) B1uc1 (t Td )
(40a)
yc1 (t ) C1 xc1 (t ) xc 2 (t ) A2 xc 2 (t ) B2uc 2 (t )
where
CR IP T
yc 2 (t ) C2 xc 2 (t ) D2uc 2 (t )
(40b)
62.44 993.20 600 1 1 10 0 A1 1 0 0 B 0 B2 , , 1 , C1 0 0 6000 , A2 1 0 , 0 1 0 0 0
extended system in Fig. 1 can be represented as
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C2 0.42 20 and D2 1 . The dead time Td 0 is to be assigned. The state-space model of the
xec (t ) Ae xec (t ) Beuc1 (t Td ) Fˆec rˆ(t )
(41a)
uc1 (t ) Kec xec (t ) Eec rˆ(t )
(41b)
yc1 (t ) Ce xec (t )
(41c)
M
where rˆ(t ) Ec r(t ) , Td ( N )T , N 0 , 0 1 and
0 ˆ Fec B2 , B1D2
0 0 A1 Ae B2C1 A2 B2C1 , B1D2C1 B1C2 A1 B1D2C1
Kec D2C1
D2C1 , Eec D2 , and Ce C1 0 0 . The parameters of the control law for the
PT
C2
ED
xc1 (t ) xec (t ) xc 2 (t ) , xc 3 (t )
B1 Be 0 , B1
Fec Fˆec Ec ,
system with a long input dead time Td 0 in (41) is determined as
CE
Kec D2C1 C2 D2C1 0 0 6000 0.4 20 0 0 6000 ,
1
Ec Ce ( Aec )1 Bec 1 , Eec 1 .
AC
Ked 2.6414 213.4406 5671.0939 0.9268 18.2797 2.6414 213.4406 5671.0939 , Eed 0.9537 .
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1.2
1
CR IP T
Magnitude
0.8
0.6
0.4
0.2
y for N=5 d
0
0
2
4
6
8
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y for N=10
10 Time (sec)
12
14
16
d
18
20
Fig. 3 Output responses for Case 1 and Case 2
In the simulations, we consider two cases of the long input delays: Case 1: Td ( N )T 0.57 , where N 5 , 0.7 and T 0.1s .
M
Case 2: Td ( N )T 1.07 , where N 10 , 0.7 and T 0.1s .
ED
where the sampling period is T 0.1s , which is lying in the range [1] of T [(3-10)b ] 0.033s-0.11s , where b 9.56 rad s is the bandwidth of the delay-free system. When T 0.035s
PT
and Td NT 0.175s with N 5 , the digitally redesigned system exhibits fairly good response. However, when T 0.1s and Td NT 0.5s with N 5 , the digitally redesigned system in [18]
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exhibits unstable response.
For Case 1, the parameters in the digital control law (28) are obtained as
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Kˆ ed 0.2375 15.7858 269.0096 0.2976 3.1528 0.2375 15.7858 269.0096 , F6 3.6840e-14 ,
F5 1.1130e-13 , F4 2.4275e-14 , F3 2.1439e-13 , F2 2.8911e-13 , F1 2.1813e-12 and
Hˆ er( N ) 0.8828 . Also, ( Gec Ge H e Ked ) Gec 100% 2.1351% % , where 5 . For Case 2, the parameters in the digital control law (28) are obtained as Kˆ ed 0.1511 9.0032 114.7063 0.1050 0.7458 0.1511 9.0032 114.7063 ,
F11 1.5584e-14 ,
F10 2.4528e-15 ,
F6 1.1210e-13 ,
F9 2.1694e-14 ,
F8 1.4918e-13 ,
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F7 8.7792e-14 ,
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F5 1.1130e-13 , F4 2.4275e-14 , F3 2.1439e-13 , F2 2.8911e-13 , F1 2.1813e-12 and
Hˆ er( N ) 0.8691 . It is noticed that Fi , for i 1,2
,5 , are the same as those in Case 1. Also,
( Gec Ge H e Ked ) Gec 100% 2.1353% % , where 5 .
The simulation results for Case 1 and Case 2 are shown in Figs. 3-5, in which the output responses of Case 1 and Case 2 are depicted in Fig. 3, and the state responses are given in Fig. 4 and Fig. 5,
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respectively. It can be seen from the simulation results that the plant outputs track the constant reference input r(t ) 1 closely for both long input time delay cases with N 5 and N 10 for the same 0.7 and T 0.1s . Furthermore, the digitally reconstructed states xri , for i 1,2 , produced by the ideal state reconstructor, match the real plant states xci closely. -4
5
0
0.5
x 10
1
0.5
x 10
1
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0
2
2.5 Time (sec)
3
3.5
4
x
r1
4.5
1
1.5
2
2.5 Time (sec)
0
0.5
1
5
xc2 xr2
3
3.5
4
4.5
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Magnitude
2
0
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0.5
0
1.5
-4
xc1
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0 -2
1
Magnitude
x 10
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Magnitude
10
5
xc3 x
r3
1.5
2
2.5 Time (sec)
3
3.5
4
4.5
5
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Fig. 4 State responses of Case 1 ( xci : state of the plant; xri : reconstructed state)
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10
-4
Magnitude
xc1 x
5 0 -2
1
r1
0
0.5
x 10
1
1.5
2
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2.5 Time (sec)
3
3.5
4
4.5
5
x
r2
0.5
0
Magnitude
2
0
0.5
x 10
1
1.5
2
-4
2.5 Time (sec)
3
1
0
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xc2
0
0.5
1
1.5
2
3.5
4
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Magnitude
x 10
2.5 Time (sec)
3
3.5
4
4.5
5
xc3 x
r3
4.5
5
M
Fig. 5 State responses of Case 2 ( xci : state of the plant; xri : reconstructed state)
6. Conclusions
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The prediction-based state-matching digital redesign method has been developed in [13] for the discretization of the analog Smith predictor for the systems with various input dead times. Various digital controllers have been developed according to the lengths of input delay times. In this paper, by
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extending the method developed for the delay-free systems [19, 20] to that for the time-delay ones, a Chebyshev quadrature state-matching digital redesign method has been proposed to find a simple
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digitally redesigned controller for the analog Smith Predictor with either a short dead time or a long one. In addition, the proposed ideal state reconstructor has extended the method developed for
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delay-free systems [21] to the time-delay systems. An illustrative example has been given to show the effectiveness of the proposed approach.
Acknowledgement This work was supported by the National Natural Science Foundation of the People’s Republic of China under grant numbers 61374047, 61273131 and National Science Council of Republic of China under contract NSC102-2221-E-006-208-MY3. 16
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References
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[1] K.J. Astrom, Computer-controlled Systems: Theory and Design, Prentice Hall, Upper Saddle River, New Jersey, 1997. [2] B.C. Kuo, Digital Control Systems, Holt, Rinehart and Winston, 1980. [3] J.P. Richard, Time-delay systems: An overview of some recent advances and open problems, Automatica 39 (2003) 1667-1694. [4] A. Seshagiri Rao, V.S.R. Rao, M. Chidambaram, Direct synthesis-based controller design for integrating processes with time delay, J. Frankl. Inst. 346 (2009) 38-56. [5] O.J. Smith, Closer control of loops with dead time, Chem. Eng. Progress 53 (1957) 217-219. [6] W. Xie, G.L. Li, GIMC architecture for linear systems with a single I/O delay, J. Frankl. Inst. 349 (2012) 2151-2162. [7] J. Herrera, A. Ibeas, S. Alcántara, M. de la Sen, S.I. Serna-Garcés, Identification and control of delayed SISO systems through pattern search methods, J. Frankl. Inst. 350 (2013) 3128-3148. [8] K.J. Astrom, C.C. Hang, B.C. Lin, A new Smith predictor for controlling a process with an integrator and long dead-time, IEEE Trans. Autom. Control 39 (1994) 343-345. [9] H.Q. Zhou, Q.G. Wang, L. Min, Modified Smith predictor design for periodic disturbance rejection, ISA Trans. 46 (2007) 493-503. [10] A.S. Rao, M. Chidambaram, Analytical design of modified Smith predictor in a two-degree-of-freedom control scheme for second order unstable processes with time delay, ISA Trans. 47 (2008) 407-419. [11] B. Zhang, W.D. Zhang, Two-degree-of-freedom control scheme for processes with large time delay, Asian J. Control 8 (2006) 50-55. [12] D.G. Padhan, S. Majhi, Modified Smith predictor based cascade control of unstable time delay processes, ISA Trans. 51 (2012) 95-104. [13] C.C. Hang, Q.G. Wang, X.P. Yang, A modified Smith predictor for a process with an integrator and long dead time, Ind. Eng. Chem. Res. 42 (2003) 484-489. [14] Q.C. Zhong, G. Weiss, A unified smith predictor based on the spectral decomposition of the plant, Int. J Control. 77 (2004) 1362-1371 [15] M.R. Matausek, A.D. Micic, On the modified Smith predictor for controlling a process with an integrator and long dead-time, IEEE Trans. Autom. Control 44 (1999) 1603-1606. [16] H. Fujimoto, A. Kawamura, M. Tomizuka, Generalized digital redesign method for linear feedback system based on N-delay control, IEEE/ASME Trans. on Mechatronics 4 (1999) 101-109. [17] Y.P. Zhang, L.S. Shieh, C.R. Liu, S.M. Guo, Digital PID controller design for multivariable analogue systems with computational input-delay, IMA J. Math. Control Info. 21 (2004) 433-456. [18] A.C. Dunn, L.S. Shieh, S.M. Guo, Digital redesign of analog Smith predictor for systems with input time delays, ISA Trans. 43 (2004) 33-47. [19] A. Ralston, A First Course in Numerical Analysis, McGraw-Hill, New York, 1965. [20] L.S. Shieh, W.M. Wang, M.K. Appu Panicker, Design of PAM and PWM digital controllers for cascaded analog systems, ISA Trans. 37 (1998) 201-213. [21] M.E. Polites, Ideal state reconstructor for deterministic digital control systems, Int. J. Syst. Sci. 49 (1989) 2001-2011.
Appendix A: Ideal state reconstructor for case (ii) ( 1/ 2 1 ) of long input time delay Considering the discretized system (29) and the multirate sampling sequence shown in Fig. 6 with 1/ 2 1 , TNˆ T Nˆ T ( Nˆ n1 ) and Td ( N )T , we have
xd 1 (kT T TNˆ ) G1( ) xd 1 (kT T ) H1( )ud 1 (kT NT )
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(A.1)
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where G1( ) e
, H1( ) (G1( ) I ) A11B1 . By successively shifting (A.1) forward by TNˆ , we obtain
A1TNˆ
xd 1 (kT T 2TNˆ ) G1( ) xd 1 (kT T TNˆ ) H1( )ud 1 (kT NT ) G1(2 ) xd 1 (kT T ) H1(2 )ud 1 (kT NT )
where G1(2 ) e
A1 2TNˆ
, H1(2 ) (G1(2 ) I ) A11B1 , and in general, xd 1 (kT T iTNˆ ) G1(i ) xd 1 (kT T ) H1(i )ud 1 (kT NT )
(A.3)
, H1(i ) (G1(i ) I ) A11B1 , with i 1,2, , Nˆ . The sampled output sequence yd(i1) ,
for i 1,2, , Nˆ , at time instant t kT T , can be gathered as ud1(kT NT T )
ud1(kT NT )
ud1(kT NT T)
TNˆ
yd1(t) {YF}
···
kT 2T
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kT T kTT
kT
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where G1( i ) e
A1iTNˆ
(A.2)
kT T T
kT2TT
Fig. 6 Multirate sampling sequence for ideal state reconstructor (case (ii))
ˆ ˆ ) C x (kT T NT ˆ ˆ) y yd 1 (kT T NT 1 d1 N N ( Nˆ 1) ˆ ˆ yd 1 yd 1 (kT T ( N 1)TNˆ ) C1 xd 1 (kT T ( N 1)TNˆ ) YF Dxd 1 (kT T ) Eud 1 (kT NT ) (A.4) (1) yd 1 yd 1 (kT T TNˆ ) C1 xd 1 (kT T TNˆ )
where D (C1G1( N ) )T ˆ
ˆ
E (C1H1( N ) )T (C1H1(( N 1) ) )T ˆ
T
(C1G1( ) )T , T
(C1H1( ) )T . Then, from (A.4), we obtain xd 1 (kT T ) D YF Eud 1 (kT NT )
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ˆ
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(C1G1(( N 1) ) )T
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( Nˆ ) d1
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where D ( DT D)1 DT , rank ( D) n1 and n1 is the order of system (1) .
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(A.5)