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Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing
Materials Science in Semiconductor Processing 5 (2003) 519–524
Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing Sang Hyun Leea, Ohsung Songa,*, C.S. Yoonb, C.K. Kimb a
Department of Materials Science and Engineering, The University of Seoul, Seoul 130-743, South Korea b Department of Materials Science and Engineering, Hanyang University, Seoul 133-791, South Korea Received 1 April 2002; received in revised form 20 June 2002; accepted 9 July 2002
Abstract ( ( 2000 A-SiO 2/Si(1 0 0) and 560 A-Si3N4/Si(1 0 0) wafers, that are 10 cm in diameter, were directly bonded using a rapid thermal annealing method, so-called fast linear annealing (FLA), in which two wafers scanned with a high-power halogen lamp. It was demonstrated that at lamp power of 550 W, corresponding to the surface temperature of B4501C, the measured bonded area was close to 100%. At the same lamp power, the bond strength of the SiO28Si3N4 wafer pair reached 2500 mJ/m2, which was attained only above 10001C with conventional furnace annealing for 2 h. The results clearly show that the FLA method is far superior in producing high-quality directly bonded Si wafer pairs with SiO2 and Si3N4 films (Si/SiO28Si3N4/Si) compared to the conventional method. r 2002 Elsevier Science Ltd. All rights reserved. Keywords: Direct bonding; Bonding of Si wafer pairs with SiO2 and Si3N4 films (Si/SiO28Si3N4/Si); Fast linear annealing; Heterogeneous bonding
1. Introduction Direct bonding of wafers was first introduced in 1985 and 1986 by two independent researchers: Shimbo [1] and Lasky [2]. Surfaces of two wafers are cleaned and physically brought together so that two wafers can be bonded together through Van der Waal’s interaction or hydrogen bonding. The weakly bonded surfaces are subsequently thermally treated in order to increase the bonding strength. For Si wafers temperatures in excess of 11001C is typically required to provide sufficient interfacial strength. Direct wafer bonding [3] was successfully applied to silicon on insulator (SOI) technology on a commercial scale in low-power, low-voltage devices. Today the technology has been extended to other materials as well as heterogeneous surfaces [4]. Especially, since the invention of the smart-cut method [5] in which Si thin *Corresponding author. Fax: +82-2-2215-5863. E-mail address: [email protected] (O. Song).
film is split from the SOI substrate utilizing the ion implantation and hydrogen embrittlement effect to produce cheap, reliable SOI wafers, direct wafer bonding has become one of the key technologies in the semiconductor industry. Even though direct bonding of similar surfaces such as Si/Si [6] has been successfully carried out, a minimal amount work has been published on the direct bonding dissimilar surfaces. In our previous experiment, we demonstrated the fast linear annealing (FLA) process employing single halogen lamp with a parabolic mirror to heat treat the directly bonded wafers. The combination provides a concentrated heat source that can be scanned over the substrate in order to generate rapid thermal annealing effects. Compared to the conventional furnace annealing, the FLA method was effective in removing the gaseous interface defects [7,8]. Micro-electro-mechanical system (MEMS) typically utilizes multilayer thin films consisting of Si/SiO28Si3N4/ Si in fabricating micro-cantilevers [9] or micro-pumps [10]. In order to expedite the fabrication, the direct
1369-8001/02/$ - see front matter r 2002 Elsevier Science Ltd. All rights reserved. PII: S 1 3 6 9 - 8 0 0 1 ( 0 2 ) 0 0 0 5 9 - 8
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S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
bonding of different SiO2 and Si3N4 surfaces is of a great interest. In addition to the MEMS process, oxide–nitride–oxide (ONO) [11] structure based on SiO–Si3N4–SiO2 triple layers may be used as the gate in the dynamic random access memory (DRAM) manufacturing due to its high dielectric constant of Si3N4; however, the added cost of fabricating of ONO wafers remains to be solved. In the research, we have explored the possibility of applying the FLA process to the direct bonding of two dissimilar surfaces: SiO2 and Si3N4 at a relatively low temperature to produce a high-quality Si wafer pairs with two different insulating layers.
Fig. 1. Schematic illustration of the FLA system.
2. Experimental procedure ( thick Si3N4 film was deposited Using LPCVD, 560 A onto a p-type Si(1 0 0) wafer with diameter of 10 cm. The deposition was done at 7851C using Si2Cl2 at 28.9 sccm and NH3 at 100 sccm as precursor gases. Multiple number of Si3N4/Si wafers were deposited under ( thick SiO2 thermal oxide identical conditions. 2000 A was grown on p-type Si(1 0 0) wafers simultaneously using dry O2. The thickness of the thermal oxide was measured using an ellipsometer at 20 different locations for each wafer. Wafers whose thickness variation of the deposited films was less than 7% over the entire surface were used for the subsequent direct bonding experiment. The final thickness of the Si3N4 and SiO2 films was ( respectively. 2000718 and 56074 A, The SiO2/Si wafers were cleaned with a mixture of H2SO4 and H2O2 in the ratio of 4:1 and deionized water. After the cleaning process, the wafers were dried in a spin dryer in order to activate the OH surface species [12] while the identically cleaned Si3N4 wafers further treated with 10% HF and rinsed twice with deionized water. The Si3N4 wafers were again dried in a spin dryer after which should be covered with H+ on the surface [12] in order to facilitate the bonding with the OH activated SiO2 surfaces. Two clean wafers brought to contact in a Class #100 grade clean room using an aligner at room temperature. Using an IR camera, it was ensured that no air traps or voids existed at the interface of the wafer pair prior to annealing. The wafer pairs were then annealed using the FLA method. The experimental setup for the FLA is shown in Fig. 1 and has been described in detail
Fig. 2. Plot of the surface temperature of the wafers versus lamp power (’: this work, Si/SiO28Si3N4/Si).
S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
elsewhere [7,8]. The lamp power was varied from 320 to 550 W, while scan speed was fixed by 0.8 mm/s. The scan speed is critical since too slow scan speed can induce wafer warping or thermal stress on the wafer pair while insufficient thermal energy will be transferred with excessively fast scan speed. Optimal scan speed appears to depend on the bonding materials as the SiO2 films was optimally annealed at 0.1 mm/s [7]; however, in case of the Si3N4 and SiO2 films, the scanning speed of 0.8 mm/s was determined to be the maximum speed at which the wafer pair can be annealed. Local surface
521
temperatures were measured by placing eight thermocouples below the wafer pair along the scan direction and the measured temperature distribution was verified using a calculated model, which is detailed elsewhere [8]. Measured peak temperature during the annealing is shown in Fig. 2. Entire annealing process was finished in 125 s. Bonded area was verified using an IR camera [13] and image analyzing software and the bonding strength was measured with the razor-blade crack-opening method [3].
Fig. 3. Plot of bonding area versus heat input (’: this work, Si/SiO28Si3N4/Si).
Fig. 4. Plot of the interface energy versus heat input (’: this work, Si/SiO28Si3N4/Si).
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S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
3. Results and discussion Shown in Fig. 3 is the percentage of the bonded area measured with an IR camera. All wafers showed over 80% in bonded area and the value increased to nearly 100% at 550 W as the lamp power was raised. Below 400 W, the heat input was not sufficiently high to obtain fully bonded wafers. The values for bonded area for these wafers are far better compared to the previous work on the direct bonding of the Si8SiO2/Si wafers using the FLA method [7]; the improvement can be attributed to the use of aligner which ensured that ( between two surfaces was average distance of B20 A maintained throughout the wafer pair prior to the annealing process. Use of the aligner allows two surfaces to come in contact in a gradual and controlled manner.
Thus, the aligner not only facilitates the mechanical process of bringing the two surfaces together, but also improves the initial physical bonding of the wafers by removing the possible trapped air [14]. In Fig. 4 is the result of interface strength measurements carried out using the razor-blade crack opening method. As can be seen, initially, the interface energy rapidly increased with increasing surface temperature. The interface energy plateaus at 2300 mJ/m2 above 400 W (B4001C). Even after considering the expected inaccuracy of B20% in estimating the bond energy using the razor-blade method [3], the measured bonding strength of the FLA method was comparable to the value obtained for the conventional furnace annealing wafers [14]. In order to better evaluate the FLA method against the conventional annealing method, the bond
Fig. 5. Plot of the interface energy versus annealing temperature: (a) (’) this work; and (b) (K) Lee et al. [14].
S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
energies measured using the razor-blade method for two annealing processes are shown in Fig. 5. At 4001C, the bond energy for the FLA method have already attained the maximum value, which was obtained using the conventional furnace method above 10001C. Fig. 5 clearly demonstrates the superiority of the FLA method in directly bonding two heterogeneous surfaces. Fig. 6 shows the bonded area measured for both FLA method and conventional furnace annealing. It is interesting to note that the bonded area for the conventional annealing reached nearly B100% even at 4001C although the maximum bonding strength was not reached above 10001C. The result is consistent with the X-ray topography of the SOI wafers which showed the voids generated at low temperatures disappeared with
523
high-temperature annealing in excess of 10001C [15]. It is likely that in the conventional annealing process, excess H2O and OH are trapped within the microscopic voids between two wafers during the slow heating process as the whole surface of the wafer is evenly heated. The trapped phases will require relatively high temperatures to gain enough surface mobility so that the gaseous phases can escape and covalent bonding can take place between two wafers. In contrast, comparing Fig. 3 and 4, the bonding strength measured for the FLA bonded wafers increases with the increasing bonded area up to 90% bonded area and then the bonding strength plateaus reaching the maximum attainable bonding strength unlike those of the conventional furnace annealing. In the FLA method, the thermal energy is
Fig. 6. Plot of bonding area versus surface temperature: (a) (’) this work; and (b) (K) Lee et al. [14].
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S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
concentrated into a localized region. During the thermal scan, excess H2O and OH are quickly vaporized from the small area and allowed to escape through the interfacial gap in the unheated section of the wafer as long as the heat input is high enough for vaporization of the excess surface phases [7] so that the maximum bond strength is quickly reached. It can be inferred that there is a critical amount of thermal energy required to vaporize surface phases and drive out the resulting gaseous phases during the thermal scan of the FLA process. This appears to be around B3501C for our wafer pairs since the maximum bonding strength is nearly reached at this point [8]. Further input of thermal energy only slightly improves the bonding quality. In conclusion, it appears that the FLA method utilizes the thermal energy more effectively to bond two different surfaces compared to the conventional furnace annealing. Using the FLA method, it was possible to directly bond two dissimilar surfaces at temperatures substantially lower than temperature typically used in the conventional furnace annealing method. The relatively low processing temperature allows the FLA method to minimize the problems associated with warping of the wafers and thermal expansion mismatch that may arise during the annealing at excessively high temperatures. The FLA method not only provides a reasonable bonding strength for the Si/SiO28Si3N4/Si films at B4001C, but also considerably reduces the processing time, hence increasing the throughput. The conventional furnace heating requires nearly 2 h for heating and cooling the wafers whereas only 125 s/wafer is needed to impart sufficient bond energy to the Si/SiO28Si3N4/Si films in the FLA method.
4. Conclusion It was demonstrated that high quality Si/SiO28Si3N4/ Si wafers, that are directly bonded can be obtained using the FLA method. The FLA method has many advantages over the conventional furnace annealing in that the annealing is performed at comparatively low temperatures avoiding problems such as thermal expansion mismatch. The FLA method is also a rapid annealing process, so that it is easily adoptable to the large-scale manufacturing with high yield. Acknowledgement This study was supported by the 2002 Research Fund of the University of Seoul.
References [1] Shimbo M, Furukawa K, Fukuda K, Tanzawa K. Siliconto-silicon direct bonding method. J Appl Phys 1986; 60(8):2987. [2] Lasky JB. Wafer bonding for silicon-on-insulator technologies. Appl Phys Lett 1986;48:78. [3] Tong QY, Goesele U. In: Semiconductor wafer bonding. Science and technology. New York: Wiley, 1999. [4] Lehmann V, Mitani K, Stengl R, Mii T, Goesele U. Bubble-free wafer bonding of GaAs and InP on silicon in a microcleanroom. Jpn J Appl Phys 1989;28(12):L2141. [5] Bruel M, Aspar B, Auberton-Herve AJ. Smart-cut: a new silicon on insulator material technology based on hydrogen implantation and wafer Bonding. Jpn J Appl Phys 1997;36:1636. [6] Abe T, Nakomo M, Itoh T. In: Schmidt DN, editor. Silicon-on-insulator technology and devices. Pennington: Electrochemical Society, 1990. p. 61. [7] Lee JW, Kang CS, Song OS, Kim CK. Application of linear annealing method to Si8SiO2/Si wafer direct bonding. Thin Solid Films 2001;394:272. [8] Joo YC, Lee JW, Song OS, Joo YC, Kang CS. Effect of moving velocity of the heat source on bonding strength in the direct silicon wafer using linear annealing method. J Korean Inst Met Mater 2001;39(1):110. [9] Jensen BD, de Boer MP, Masters ND, Bitsie F, LaVan DA. Interferometry of actuated microcantilevers to determine material properties and test structure nonidealities in MEMS. J Micro Syst 2001;10:336. [10] Zahn JD, Deshmukh AA, Pisano AP, Liepmann D. Continuous on-chip micropumping through a microneedle. In: Microelectro mechanical systems, MEMS 2001. The 14th IEEE International Conference proceedings, Interlaken, Switzerland, 2001. p. 503. [11] Robertson J, Powell MJ. Gap states in silicon nitride. Appl Phys Lett 1984;44:415. [12] Israelachvili J. Intermolecular and surface forces, 2nd ed.. London: Academic Press, 1991. [13] Martini T, Steinkirchner J, Gosele U. The crack opening method in silicon wafer bonding. How useful is it? J Electrochem Soc 1997;144(1):354. [14] Lee SH, Yi SD, Seo TY, Song OS. Direct bonding of Si8SiO2/Si3N48Si wafer pairs with a furnace. Mater Res Soc Korea 2002;12(2):117. [15] Abe T, Takei T, Uchiyama A, Yoshizawa K, Nakazato Y. Silicone wafer bonding mechanism for silicon-on-insulator structures. Jpn J Appl Phys 1990;29(12):L2311.
Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing Sang Hyun Leea, Ohsung Songa,*, C.S. Yoonb, C.K. Kimb a
Department of Materials Science and Engineering, The University of Seoul, Seoul 130-743, South Korea b Department of Materials Science and Engineering, Hanyang University, Seoul 133-791, South Korea Received 1 April 2002; received in revised form 20 June 2002; accepted 9 July 2002
Abstract ( ( 2000 A-SiO 2/Si(1 0 0) and 560 A-Si3N4/Si(1 0 0) wafers, that are 10 cm in diameter, were directly bonded using a rapid thermal annealing method, so-called fast linear annealing (FLA), in which two wafers scanned with a high-power halogen lamp. It was demonstrated that at lamp power of 550 W, corresponding to the surface temperature of B4501C, the measured bonded area was close to 100%. At the same lamp power, the bond strength of the SiO28Si3N4 wafer pair reached 2500 mJ/m2, which was attained only above 10001C with conventional furnace annealing for 2 h. The results clearly show that the FLA method is far superior in producing high-quality directly bonded Si wafer pairs with SiO2 and Si3N4 films (Si/SiO28Si3N4/Si) compared to the conventional method. r 2002 Elsevier Science Ltd. All rights reserved. Keywords: Direct bonding; Bonding of Si wafer pairs with SiO2 and Si3N4 films (Si/SiO28Si3N4/Si); Fast linear annealing; Heterogeneous bonding
1. Introduction Direct bonding of wafers was first introduced in 1985 and 1986 by two independent researchers: Shimbo [1] and Lasky [2]. Surfaces of two wafers are cleaned and physically brought together so that two wafers can be bonded together through Van der Waal’s interaction or hydrogen bonding. The weakly bonded surfaces are subsequently thermally treated in order to increase the bonding strength. For Si wafers temperatures in excess of 11001C is typically required to provide sufficient interfacial strength. Direct wafer bonding [3] was successfully applied to silicon on insulator (SOI) technology on a commercial scale in low-power, low-voltage devices. Today the technology has been extended to other materials as well as heterogeneous surfaces [4]. Especially, since the invention of the smart-cut method [5] in which Si thin *Corresponding author. Fax: +82-2-2215-5863. E-mail address: [email protected] (O. Song).
film is split from the SOI substrate utilizing the ion implantation and hydrogen embrittlement effect to produce cheap, reliable SOI wafers, direct wafer bonding has become one of the key technologies in the semiconductor industry. Even though direct bonding of similar surfaces such as Si/Si [6] has been successfully carried out, a minimal amount work has been published on the direct bonding dissimilar surfaces. In our previous experiment, we demonstrated the fast linear annealing (FLA) process employing single halogen lamp with a parabolic mirror to heat treat the directly bonded wafers. The combination provides a concentrated heat source that can be scanned over the substrate in order to generate rapid thermal annealing effects. Compared to the conventional furnace annealing, the FLA method was effective in removing the gaseous interface defects [7,8]. Micro-electro-mechanical system (MEMS) typically utilizes multilayer thin films consisting of Si/SiO28Si3N4/ Si in fabricating micro-cantilevers [9] or micro-pumps [10]. In order to expedite the fabrication, the direct
1369-8001/02/$ - see front matter r 2002 Elsevier Science Ltd. All rights reserved. PII: S 1 3 6 9 - 8 0 0 1 ( 0 2 ) 0 0 0 5 9 - 8
520
S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
bonding of different SiO2 and Si3N4 surfaces is of a great interest. In addition to the MEMS process, oxide–nitride–oxide (ONO) [11] structure based on SiO–Si3N4–SiO2 triple layers may be used as the gate in the dynamic random access memory (DRAM) manufacturing due to its high dielectric constant of Si3N4; however, the added cost of fabricating of ONO wafers remains to be solved. In the research, we have explored the possibility of applying the FLA process to the direct bonding of two dissimilar surfaces: SiO2 and Si3N4 at a relatively low temperature to produce a high-quality Si wafer pairs with two different insulating layers.
Fig. 1. Schematic illustration of the FLA system.
2. Experimental procedure ( thick Si3N4 film was deposited Using LPCVD, 560 A onto a p-type Si(1 0 0) wafer with diameter of 10 cm. The deposition was done at 7851C using Si2Cl2 at 28.9 sccm and NH3 at 100 sccm as precursor gases. Multiple number of Si3N4/Si wafers were deposited under ( thick SiO2 thermal oxide identical conditions. 2000 A was grown on p-type Si(1 0 0) wafers simultaneously using dry O2. The thickness of the thermal oxide was measured using an ellipsometer at 20 different locations for each wafer. Wafers whose thickness variation of the deposited films was less than 7% over the entire surface were used for the subsequent direct bonding experiment. The final thickness of the Si3N4 and SiO2 films was ( respectively. 2000718 and 56074 A, The SiO2/Si wafers were cleaned with a mixture of H2SO4 and H2O2 in the ratio of 4:1 and deionized water. After the cleaning process, the wafers were dried in a spin dryer in order to activate the OH surface species [12] while the identically cleaned Si3N4 wafers further treated with 10% HF and rinsed twice with deionized water. The Si3N4 wafers were again dried in a spin dryer after which should be covered with H+ on the surface [12] in order to facilitate the bonding with the OH activated SiO2 surfaces. Two clean wafers brought to contact in a Class #100 grade clean room using an aligner at room temperature. Using an IR camera, it was ensured that no air traps or voids existed at the interface of the wafer pair prior to annealing. The wafer pairs were then annealed using the FLA method. The experimental setup for the FLA is shown in Fig. 1 and has been described in detail
Fig. 2. Plot of the surface temperature of the wafers versus lamp power (’: this work, Si/SiO28Si3N4/Si).
S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
elsewhere [7,8]. The lamp power was varied from 320 to 550 W, while scan speed was fixed by 0.8 mm/s. The scan speed is critical since too slow scan speed can induce wafer warping or thermal stress on the wafer pair while insufficient thermal energy will be transferred with excessively fast scan speed. Optimal scan speed appears to depend on the bonding materials as the SiO2 films was optimally annealed at 0.1 mm/s [7]; however, in case of the Si3N4 and SiO2 films, the scanning speed of 0.8 mm/s was determined to be the maximum speed at which the wafer pair can be annealed. Local surface
521
temperatures were measured by placing eight thermocouples below the wafer pair along the scan direction and the measured temperature distribution was verified using a calculated model, which is detailed elsewhere [8]. Measured peak temperature during the annealing is shown in Fig. 2. Entire annealing process was finished in 125 s. Bonded area was verified using an IR camera [13] and image analyzing software and the bonding strength was measured with the razor-blade crack-opening method [3].
Fig. 3. Plot of bonding area versus heat input (’: this work, Si/SiO28Si3N4/Si).
Fig. 4. Plot of the interface energy versus heat input (’: this work, Si/SiO28Si3N4/Si).
522
S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
3. Results and discussion Shown in Fig. 3 is the percentage of the bonded area measured with an IR camera. All wafers showed over 80% in bonded area and the value increased to nearly 100% at 550 W as the lamp power was raised. Below 400 W, the heat input was not sufficiently high to obtain fully bonded wafers. The values for bonded area for these wafers are far better compared to the previous work on the direct bonding of the Si8SiO2/Si wafers using the FLA method [7]; the improvement can be attributed to the use of aligner which ensured that ( between two surfaces was average distance of B20 A maintained throughout the wafer pair prior to the annealing process. Use of the aligner allows two surfaces to come in contact in a gradual and controlled manner.
Thus, the aligner not only facilitates the mechanical process of bringing the two surfaces together, but also improves the initial physical bonding of the wafers by removing the possible trapped air [14]. In Fig. 4 is the result of interface strength measurements carried out using the razor-blade crack opening method. As can be seen, initially, the interface energy rapidly increased with increasing surface temperature. The interface energy plateaus at 2300 mJ/m2 above 400 W (B4001C). Even after considering the expected inaccuracy of B20% in estimating the bond energy using the razor-blade method [3], the measured bonding strength of the FLA method was comparable to the value obtained for the conventional furnace annealing wafers [14]. In order to better evaluate the FLA method against the conventional annealing method, the bond
Fig. 5. Plot of the interface energy versus annealing temperature: (a) (’) this work; and (b) (K) Lee et al. [14].
S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
energies measured using the razor-blade method for two annealing processes are shown in Fig. 5. At 4001C, the bond energy for the FLA method have already attained the maximum value, which was obtained using the conventional furnace method above 10001C. Fig. 5 clearly demonstrates the superiority of the FLA method in directly bonding two heterogeneous surfaces. Fig. 6 shows the bonded area measured for both FLA method and conventional furnace annealing. It is interesting to note that the bonded area for the conventional annealing reached nearly B100% even at 4001C although the maximum bonding strength was not reached above 10001C. The result is consistent with the X-ray topography of the SOI wafers which showed the voids generated at low temperatures disappeared with
523
high-temperature annealing in excess of 10001C [15]. It is likely that in the conventional annealing process, excess H2O and OH are trapped within the microscopic voids between two wafers during the slow heating process as the whole surface of the wafer is evenly heated. The trapped phases will require relatively high temperatures to gain enough surface mobility so that the gaseous phases can escape and covalent bonding can take place between two wafers. In contrast, comparing Fig. 3 and 4, the bonding strength measured for the FLA bonded wafers increases with the increasing bonded area up to 90% bonded area and then the bonding strength plateaus reaching the maximum attainable bonding strength unlike those of the conventional furnace annealing. In the FLA method, the thermal energy is
Fig. 6. Plot of bonding area versus surface temperature: (a) (’) this work; and (b) (K) Lee et al. [14].
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S.H. Lee et al. / Materials Science in Semiconductor Processing 5 (2003) 519–524
concentrated into a localized region. During the thermal scan, excess H2O and OH are quickly vaporized from the small area and allowed to escape through the interfacial gap in the unheated section of the wafer as long as the heat input is high enough for vaporization of the excess surface phases [7] so that the maximum bond strength is quickly reached. It can be inferred that there is a critical amount of thermal energy required to vaporize surface phases and drive out the resulting gaseous phases during the thermal scan of the FLA process. This appears to be around B3501C for our wafer pairs since the maximum bonding strength is nearly reached at this point [8]. Further input of thermal energy only slightly improves the bonding quality. In conclusion, it appears that the FLA method utilizes the thermal energy more effectively to bond two different surfaces compared to the conventional furnace annealing. Using the FLA method, it was possible to directly bond two dissimilar surfaces at temperatures substantially lower than temperature typically used in the conventional furnace annealing method. The relatively low processing temperature allows the FLA method to minimize the problems associated with warping of the wafers and thermal expansion mismatch that may arise during the annealing at excessively high temperatures. The FLA method not only provides a reasonable bonding strength for the Si/SiO28Si3N4/Si films at B4001C, but also considerably reduces the processing time, hence increasing the throughput. The conventional furnace heating requires nearly 2 h for heating and cooling the wafers whereas only 125 s/wafer is needed to impart sufficient bond energy to the Si/SiO28Si3N4/Si films in the FLA method.
4. Conclusion It was demonstrated that high quality Si/SiO28Si3N4/ Si wafers, that are directly bonded can be obtained using the FLA method. The FLA method has many advantages over the conventional furnace annealing in that the annealing is performed at comparatively low temperatures avoiding problems such as thermal expansion mismatch. The FLA method is also a rapid annealing process, so that it is easily adoptable to the large-scale manufacturing with high yield. Acknowledgement This study was supported by the 2002 Research Fund of the University of Seoul.
References [1] Shimbo M, Furukawa K, Fukuda K, Tanzawa K. Siliconto-silicon direct bonding method. J Appl Phys 1986; 60(8):2987. [2] Lasky JB. Wafer bonding for silicon-on-insulator technologies. Appl Phys Lett 1986;48:78. [3] Tong QY, Goesele U. In: Semiconductor wafer bonding. Science and technology. New York: Wiley, 1999. [4] Lehmann V, Mitani K, Stengl R, Mii T, Goesele U. Bubble-free wafer bonding of GaAs and InP on silicon in a microcleanroom. Jpn J Appl Phys 1989;28(12):L2141. [5] Bruel M, Aspar B, Auberton-Herve AJ. Smart-cut: a new silicon on insulator material technology based on hydrogen implantation and wafer Bonding. Jpn J Appl Phys 1997;36:1636. [6] Abe T, Nakomo M, Itoh T. In: Schmidt DN, editor. Silicon-on-insulator technology and devices. Pennington: Electrochemical Society, 1990. p. 61. [7] Lee JW, Kang CS, Song OS, Kim CK. Application of linear annealing method to Si8SiO2/Si wafer direct bonding. Thin Solid Films 2001;394:272. [8] Joo YC, Lee JW, Song OS, Joo YC, Kang CS. Effect of moving velocity of the heat source on bonding strength in the direct silicon wafer using linear annealing method. J Korean Inst Met Mater 2001;39(1):110. [9] Jensen BD, de Boer MP, Masters ND, Bitsie F, LaVan DA. Interferometry of actuated microcantilevers to determine material properties and test structure nonidealities in MEMS. J Micro Syst 2001;10:336. [10] Zahn JD, Deshmukh AA, Pisano AP, Liepmann D. Continuous on-chip micropumping through a microneedle. In: Microelectro mechanical systems, MEMS 2001. The 14th IEEE International Conference proceedings, Interlaken, Switzerland, 2001. p. 503. [11] Robertson J, Powell MJ. Gap states in silicon nitride. Appl Phys Lett 1984;44:415. [12] Israelachvili J. Intermolecular and surface forces, 2nd ed.. London: Academic Press, 1991. [13] Martini T, Steinkirchner J, Gosele U. The crack opening method in silicon wafer bonding. How useful is it? J Electrochem Soc 1997;144(1):354. [14] Lee SH, Yi SD, Seo TY, Song OS. Direct bonding of Si8SiO2/Si3N48Si wafer pairs with a furnace. Mater Res Soc Korea 2002;12(2):117. [15] Abe T, Takei T, Uchiyama A, Yoshizawa K, Nakazato Y. Silicone wafer bonding mechanism for silicon-on-insulator structures. Jpn J Appl Phys 1990;29(12):L2311.