D converters using fast Walsh transform

MEJ 663

Microelectronics Journal Microelectronics Journal 31 (2000) 83–90 www.elsevier.com/locate/mejo

Dynamic characterisation of A/D converters using fast Walsh transform V. Liberali*, A. Manstretta 1, G. Torelli Department of Electronics, University of Pavia, Via Ferrata 1, 27100 Pavia, Italy Accepted 12 April 1999

Abstract This work presents an application of the Walsh transform to the dynamic characterisation of analog-to-digital converters (ADCs). The Walsh Transform (WT) is an analytical operator that extracts information on ADC parameters at the bit level rather than at the channel level. The use of the WT allows the performance of an ADC to be summarised with a reduced set of values as compared to the conventional set of non-linearity errors. To limit CPU time, a fast algorithm is used to compute the WT. A characterisation environment based on this approach was developed and used to evaluate ADC performance. q 1999 Elsevier Science Ltd. All rights reserved. Keywords: Analog-to-digital converters; Fast Walsh transform; Walsh–Hadamard functions

1. Introduction In today’s very and ultra large scale integration circuits, more and more functions are integrated into a single chip. Typically, this leads to complex systems containing circuits for control and testing purposes in addition to analog and digital modules. An accurate characterisation of a mixed system requires a specific methodology and involves dedicated hardware and software tools. The same needs arise when evaluating data converters. Research efforts are being devoted to defining a testing environment able to offer a suitable tradeoff between accuracy and time. In particular, there is a trend towards dynamic testing techniques, which allow the transfer characteristic of an analog-to-digital converter (ADC) to be estimated under operating conditions. In this paper, we describe an application of the Walsh Transform (WT) to dynamic characterisation of ADCs. Dynamic techniques provide more efficient ADC characterisation as compared with conventional static approaches. The ADC is characterised by applying an input sine wave and using the specified sampling frequency. The ADC output data are then processed according to statistical algorithms to evaluate typical performance parameters such as transition levels and non-linearity errors [1–4]. By * Corresponding author. Tel.: 1 390-382-505-200; fax: 1 390-382422-583. E-mail address: [email protected] (V. Liberali) 1 Present address: STMicroelectronics, Via Olivetti 2, 20041 Agrate Brianza, Italy.

applying the WT operator to non-linearity errors, it is possible to extract a small set of parameters that completely describe the ADC inaccuracies at the bit level. This representation is useful for ADC behavioral description when simulating a complex system including the converter, as well as when developing a testing environment using the virtual test approach [5,6]. This paper is organized as follows: Section 2 presents a brief overview of the basic theory of the WT. An application of the WT to dynamic characterisation of ADCs is discussed in Section 3. Finally, Section 4 reports two case studies showing the experimental results obtained from characterising both one commercial ADC and one ADC under development.

2. Basic theory Let us suppose that k and m are integers smaller than 2 L, while k and m are their representations as binary-weighted digit sequences, as follows: kˆ

LX 21

2i k i

and

k ˆ …kL21 ; …; ki ; …; k1 ; k0 †;

…1†

iˆ0

mˆ

LX 21

2i mi

and

m ˆ …mL21 ; …; mi ; …; m1 ; m0 †;

iˆ0

…2† where ki [ {0; 1}; mi [ {0; 1}: The kth order Walsh–Paley function in m is defined as in

0026-2692/00/$ - see front matter q 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00091-9

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V. Liberali et al. / Microelectronics Journal 31 (2000) 83–90

Fig. 1. Representation of Walsh–Paley functions for k ˆ 0, 1, 2, 3 (L ˆ 2).

Ref. [7]: pal…k; m† ;

LY 21

…21†ki mL212i :

…3†

iˆ0

LY 21

…2 † …21†ki mi ˆ hkm ; L

…4†

iˆ0 …2 † is the (k, m) element of the Hadamard matrix where hkm …2L † H ; recursively defined as: L

H…1† ˆ ‰1Š;

" H

For example, Walsh–Paley functions for L ˆ 2 (with k ranging from 0 to 3) are illustrated in Fig. 1. The functions obtained with definition (3) are also referred to as dyadic-ordered Walsh functions. However, other relationships exist, leading to the same set of Walsh functions with different ordering [8]. Alternative definitions give rise to the Walsh–Hadamard functions: had…k; m† ;

Fig. 2. Relationship between the frequency of Fourier basic functions and the sequency of sequency-ordered Walsh basic functions for k ˆ 0, 1, 2, 3 (L ˆ 2).

…2†

ˆ

1

1

1

21

" H

…2n†

ˆ

# ;

H…n†

H…n†

H…n†

2H…n†

# …5†

and to the Walsh-ordered functions wal…k; m† ;

LY 21

…21†…ki 1ki11 †mL212i :

…6†

iˆ0

Definition (6) assumes kL ˆ 0. The Walsh-ordered functions defined by Eq. (6) are similar to the basic functions of Fourier analysis. Indeed, Walshordered functions can be divided into two sets, the even

V. Liberali et al. / Microelectronics Journal 31 (2000) 83–90

and the ideal transition levels are

functions (or “cal”) and the odd ones (or “sal”): for k ˆ 0; 1; …; 2L21 2 1;

cal…k; m† ; wal…2k; m† sal…k; m† ; wal…2k 2 1; m†

for k ˆ 1; 2; …; 2

85

L21

:

VID …n† ˆ VFSL 1 nQ ˆ VFSL 1 Q …7†

LX 21

2i ni

iˆ0

…11†

for n ˆ 1; 2; …; 2 2 1; L

Functions (7) correspond, respectively, to cosine and sine functions of Fourier analysis:   m cos…k; m† ˆ cos 2pk L ; 2   m sin…k; m† ˆ sin 2pk L : 2

…8†

The parameter k is referred to as sequency. Hence, the Walsh-ordered functions are also referred to as sequencyordered functions. Analogies between Walsh and Fourier functions are apparent in Fig. 2. In particular, a relationship between the frequency of Fourier basic functions and the sequency of Walsh basic functions can be observed. In the following, we will always refer to Walsh-ordered functions. The Discrete Walsh Transform (DWT) X(k) of a series of N samples x(m) is defined as: W

x…m† ! X…k†;

where n is represented in binary form as n ˆ …nL21 ; …; ni ; …; n1 ; n0 † with ni [ {0, 1}, ni being the ith bit in the digital code. Eq. (11) can be extended to include the limits of the dynamic range: VID(0) ˆ VFSL and VID(2 L) ˆ VFSH. In a real ADC, transition levels may differ from the ideal ones, due to component inaccuracies. We will denote the transition levels of a real ADC with V(n), still assuming V(0) ˆ VFSL and V(2 L) ˆ VFSH. As a consequence, the quantization channel widths may differ from the ideal quantization step, giving rise to differential and integral non-linearity errors. The width of the nth quantization channel is defined as: Qn ; V…n 1 1† 2 V…n†

L

…9†

for k ˆ 0; 1; …; 2L 2 1: The DWT is quite similar to the Discrete Fourier Transform (DFT) [9], where Fourier basic functions are used instead of Walsh ones. In addition, the DWT satisfies dual theorems as compared with DFT theorems (in particular: linearity, convolution, time-shift, Parseval’s theorems). Other theorems, with related proofs, can be found in the literature [7,10–14]. To save computation time, the Fast Walsh Transform (FWT) can be used. To this end, algorithms very similar to the Fast Fourier Transform (FFT) ones are applied. Many FFT solutions have been presented in the literature. The classical solution is based on the Cooley–Tukey algorithm (radix-2 algorithm), which calculates DFT values provided that the input sequence is composed of N samples, where N is a power of 2 [8]. 3. Application to ADC characterisation A Nyquist-rate ADC is fully characterised by means of its transfer characteristic. Assuming an L-bit converter with input dynamic range (VFSL, VFSH), the ideal quantization step is: VFSH 2 VFSL 2L

…12†

The differential non-linearity (DNL) error associated with the nth channel is defined as:

21 1 2X x…m† wal…k; m† X…k† ˆ W{x…m†} ˆ L 2 mˆ0

Qˆ

for n ˆ 0; 1; …; 2L 2 1:

…10†

dnl…n† ;

V…n 1 1† 2 V…n† Q 2 1 ˆ n 2 1: Q Q

…13†

Integral non-linearity (INL) measures the difference between the transfer characteristics of a real and an ideal quantizer. The integral non-linearity error associated with the nth channel is: inl…n† ;

V…n† 2 VID …n† : Q

…14†

Consequently, a complete ADC characterisation requires a knowledge of either the DNL or the INL set, each composed of 2 L values. However, the generic transition level of a real ADC can also be expressed as [14]: V…n† ˆ VFSL 1 Q

LX 21

…1 1 di †2i ni ;

…15†

iˆ0

where di plays the role of the relative inaccuracy associated with the generic bit ni or with the 2 i weight. Thus, the ADC performance can be fully summarised with only L values, that is, its inaccuracy vector d ˆ …dL21 ; …; di ; …; d1 ; d0 †. It can be proved that the WT is an analytical operator that allows the inaccuracy vector d to be obtained starting from non-linearity errors. A theorem is quoted to estimate di starting from the DNL set [14]: The DWT of the dnl vector (DNL terms of an L-bit

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V. Liberali et al. / Microelectronics Journal 31 (2000) 83–90

quantizer) assumes the following discrete values: 8 > 2di 2i21 for j ˆ 2L2i 2 1; > > > > < L21 X ITS…j† ; W{inl…n†} ˆ ; dr 2r21 for j ˆ 0; > > rˆ0 > > > :0 elsewhere

output code 3 2 1 0 V(0) V(1) = V FSL

…18† V(2)

V(3)

V(4) transition level = V FSH

Fig. 3. Transfer characteristic of an ideal 2-bit ADC.

quantizer) assumes the following discrete values: 8 0 for j ˆ 0; > > > > > < d0 for j ˆ 2L 2 1; DTS…j† ˆ W{dnl…n†} ˆ ; > > di for j ˆ …2r 1 1†2L2i 2 1; > > > : 2di for j ˆ …2r 1 1†2L2i …16† where r ˆ 0, 1,…, 2 i21 2 1 and i ˆ 1, 2,…, L 2 1. Inaccuracies di can then be calculated from the W{dnl} vector, which is referred to as the differential tolerance spectrum (DTS). To obtain an accurate estimate, the di terms are evaluated as: 8 DTS…2L 2 1† for i ˆ 0 > > < i21 di ˆ 1 2 X21 > > …DTS……2r 1 1†2L2i 2 1 2 DTS……2r 1 1†2L2i †† : 2i rˆ0

Another method has also been proposed to extract the relative inaccuracies of a real ADC after the INL set has been obtained by experimental evaluation. This method is based on the following theorem [14]: The DWT of the inl vector (INL terms of an L-bit

where i ˆ 0, 1,…, L 2 1. The W{inl} vector is referred to as the integral tolerance spectrum (ITS) and can be used to determine the unknown values di, which are expressed as di ˆ 222i11 ITS…2L2i 2 1†

From Eqs. (16) and (18), we can observe that the DTS and the ITS vectors are composed of 2 L values out of which only L are independent. The ADC performance can therefore be expressed with L values of the inaccuracy vector d, given by Eqs. (17) and (19), rather than by the 2 L DNL or INL values. The knowledge of bit inaccuracies can be useful in a number of applications. For some converter architectures, bit-level inaccuracies are directly related to component mismatches. For instance, in a weighted-array successiveapproximation ADC, each inaccuracy di is related to an error in the corresponding weighted element inside the converter. Theoretically, Eqs. (17) and (19) should lead to identical

for i ˆ 1; 2; …; L 2 1

output code 3

2

2

1

1

V(1) V(2)

V(3) V(4) transition level = V FSH

Fig. 4. Transfer characteristic of a non-ideal 2-bit ADC with d ˆ (0, 0.25).

:

…17†

results. Nevertheless, the calculated values may differ due to errors in experimental acquisitions. From Eq. (19) we note that ITS directly gives an estimate of the inaccuracies, where each term di is weighted by a factor 2 i21. In contrast, Eq. (17) provides a better estimate of inaccuracies di,

output code 3

0 V(0) = V FSL

for i ˆ 0; 1; …; L 2 1: …19†

0 V(0) V(1) = V FSL

V(2)

V(3) V(4) transition level = V FSH

Fig. 5. Transfer characteristic of a non-ideal 2-bit ADC with d ˆ (0.1, 0).

V. Liberali et al. / Microelectronics Journal 31 (2000) 83–90

87

Analog Input

Ethernet

External Clock TX RS232 RX

Device Under Test

Personal Computer

DAB

Workstation Fig. 6. ADC characterisation setup.

because of the averaging performed over the whole tolerance spectrum. To be specific, we shall now consider a 2-bit ADC. Its ideal transfer characteristic is shown in Fig. 3. Let us consider the inaccuracy vector of this ADC d ˆ (d1, d0). We will first suppose that the most significant bit (MSB) is not affected by errors (d1 ˆ 0), while the least significant bit (LSB) has an error equal to 1/4 of its ideal value (d0 ˆ 0.25). The transfer characteristic of the corresponding non-ideal 2-bit ADC is shown in Fig. 4. For comparison, the ideal transfer characteristic is also reported (dashed line). Using Eq. (15), the transition levels can be expressed as V…n† ˆ VFSL 1 Q

1 X

…1 1 di †2i ni

iˆ0

ˆ VFSL 1 Q

1 X

2 ni 1 Q i

iˆ0

ˆ VID …n† 1 Q

1 X

1 X

V…n† ˆ VID …n† 1 Q · 0:25 · 20 · n0 :

…21†

It is easy to verify that Q0 ˆ Q2 ˆ 1.25Q, whereas Q1 ˆ Q3 ˆ 0.75Q. Therefore, the DNL of channels 0 and 2 is 10.25 LSB, while the DNL of channels 1 and 3 is 20.25 LSB. By calculating the DWT according to Eq. (9), we obtain DTS(0) ˆ DTS(1) ˆ DTS(2) ˆ 0, DTS(3) ˆ 0.25. From Eq. (9), we go back to the DNL vector d ˆ (0, 0.25). On the contrary, assuming d ˆ (d1, d0) ˆ (0.1, 0), we obtain the transfer characteristic shown in Fig. 5. Transition levels are still given by Eq. (15), and we have V…n† ˆ VID …n† 1 Q·0:1·21 ·n1 :

i

di 2 ni

iˆ0

di 2i ni ;

…20†

iˆ0

where each V(n) differs from the ideal value VID(n) as a result of a contribution by inaccuracies di. Assuming the 0.2 0.15 0.1

…22†

In this case, each transition level having n1 ˆ 1 (that is, the MSB set to 1) will be shifted by an amount equal to 0.2 LSB. The DNL of channels 1 and 3 will be equal to 1 0.2 LSB and 2 0.2 LSB, respectively, while no DNL error is present in channels 0 and 2. The DTS vector is (0, 1 0.1, 2 0.1, 0) and, from Eq. (19), we go back to the DNL vector d ˆ (0.1, 0). INL error

DNL error

above values for d, each transition level having n0 ˆ 1 (that is, the LSB set to 1) will be shifted by an amount equal to 0.25 LSB:

0.15 0.1 0.05

0.05 0

0

-0.05

-0.05

-0.1 -0.1

-0.15 -0.2

-0.15 0

64

128

192

256

quantisation channel Fig. 7. DNL of ADC0804.

0

64

128

192

256

quantisation channel Fig. 8. INL of ADC0804.

DTS

88

V. Liberali et al. / Microelectronics Journal 31 (2000) 83–90 Table 1 Inaccuracies of the ADC0804

0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 0

64

128

192

256

sequency Fig. 9. DTS of ADC0804.

4. Case studies

0.04

di (DTS)

di (ITS)

0 1 2 3 4 5 6 7

20.000777 20.000515 0.000028 0.000445 20.000813 0.000811 0.000009 0.000454

0.000160 20.000565 0.000042 0.000056 0.000865 0.000738 0.000962 0.000773

265 000 samples were gathered at a 10 kHz sampling rate, according to the CDT requirements [1]. The converter input range was set to 10 V. In the ideal case, the characterisation should be carried out using a full-scale amplitude sine wave as the ADC input, to test all possible digital codes. However, the generation of an accurate full-scale sine wave is a difficult task, considering that overloading must absolutely be avoided to prevent saturation. In our experiments, the sine wave amplitude was kept smaller than the ADC input range. Missing codes give rise to a DNL value equal to 2 1 and to an INL value equal to 0. Figs. 7 and 8 show the measured DNL and INL errors, respectively. The results obtained (DNL within ^ 0.2 LSB in the used input voltage range) are in very good agreement with the manufacturer specifications. However, DTS and ITS analyses need complete sets of DNL and INL values. For this reason, a routine was developed to fill the DNL vector with randomly generated data, while keeping the average and standard deviation values unaffected, when the input sine wave does not have fullscale amplitude. Thus, the software developed allows an ADC to be characterised even when the sine wave applied has an amplitude smaller than its input full-scale range, so that a few extreme channels are not involved in the performance evaluation. Figs. 9 and 10 illustrate the corresponding DTS and ITS. Table 1 shows the values of the ADC inaccuracies di, DNL error

ITS

We developed a complete characterisation environment including both hardware and software tools. The experimental setup includes a low-distortion sine wave generator and a Data Acquisition Board (DAB) connected to a PC through an RS232 interface (Fig. 6). The testing software can be installed in the PC or in a remote workstation connected to it. The software environment, implemented in C language, contains routines for ADC dynamic characterisation based on the Code Density Theory (CDT), allowing both DNL and INL values to be estimated under real operating conditions [1]. The FWT was implemented using the Cooley–Tukey algorithm. The routine obtained is fast and reliable. The developed algorithm performs an FWT of a vector of N values using only (N/2) log2 N additions instead of the (N/2) additions and N multiplications needed for normal WT computing. The developed environment was validated by characterising a commercial 8-bit ADC (ADC0804) [15]. A 2.13 kHz sine wave was applied to the converter input. About

i

0.03 0.02 0.01 0

3 2 1 0

-0.01

-1

-0.02 -2

-0.03 -0.04

-3 0

64

128

192

256

sequency Fig. 10. ITS of ADC0804.

0

64

128

192

256

320

384

448

512

quantisation channel Fig. 11. DNL of the 9-bit ADC.

5 4

ITS

INL error

V. Liberali et al. / Microelectronics Journal 31 (2000) 83–90

89

0.2 0.15

3 0.1 2 0.05

1 0

0

-1

-0.05

-2 -0.1 -3 -0.15

-4

-0.2

-5 0

64

128

192

256

320

384

448

0

512

64

128

192

256

320

384

448

512

sequency

quantisation channel Fig. 14. ITS of the 9-bit ADC.

evaluated from both the DTS and the ITS vectors. As expected from the non-linearity results, the inaccuracies are very small. Finally, the proposed environment was used to characterise an ADC under development. This ADC is based on a three-step subranging architecture [16,17]. Three bits are determined at each conversion step, starting from the MSBs. Each of the three conversion steps (coarse, intermediate and fine conversion, respectively) is carried out with a flash approach. The reference voltages for each conversion step are generated by integrated resistive strings, each made up of eight identical resistors. The same set of seven comparators is used to achieve all the required partial A/D conversions. The modular ADC structure, used to save silicon area and to reduce power consumption, produces 9bit output words, even though the resolution required in our application was 8 bits. Data were gathered at a 2 MHz sampling rate, using a 3 V input sine wave at 1159 Hz. The Code Density Theory requires about 900 000 samples. Plots in Figs. 11 and 12 show the obtained DNL and INL errors. The periodicity apparent in both figures (main period ˆ 64 LSBs,

subperiod ˆ 8 LSBs) is ascribed to the topology used for the converter. DNL is below 2 LSBs (except for one only code), while INL is contained within 3.5 LSBs in the whole range. Figs. 13 and 14 illustrate the corresponding DTS and ITS. Table 2 shows the values of the inaccuracies di obtained from our ADC. As expected (see Section 3), the values obtained from the DTS and from the ITS are not identical, the former being more reliable.

DTS

Fig. 12. INL of the 9-bit ADC.

0.2 0.15 0.1

5. Conclusion An application of the WT for bit-level dynamic characterisation of ADCs is presented. The WT is calculated with a fast algorithm (FWT), thus keeping computation time low. The FWT can be successfully used in ADC characterisation to extract parameter information at the bit level from the results obtained with dynamic testing techniques. The availability of the bit-level parameters also allows the non-idealities of an ADC to be accurately represented in a behavioral model with minimum added complexity. This can be very useful to simulate the effects of such non-idealities when the ADC is included in a more complex system. Moreover, it is also useful when following the virtual test (or test simulation) approach [5,6], whereby Table 2 Inaccuracies of the 9-bit three-step subranging ADC

0.05 0

i

di (DTS)

di (ITS)

0 1 2 3 4 5 6 7 8

20.141040 20.342669 20.057107 0.007263 20.010770 0.004383 0.003317 0.000537 20.000602

20.129968 20.342071 20.100060 0.012791 0.012963 0.020239 20.000935 20.002185 20.005570

-0.05 -0.1 -0.15 -0.2 0

64

128

192

256

320

384

448

512

sequency Fig. 13. DTS of the 9-bit ADC.

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V. Liberali et al. / Microelectronics Journal 31 (2000) 83–90

the test engineer uses models of the automatic test equipment (ATE) and the device under test (DUT) to develop the test environment for a given device (the ATE and DUT models should obviously provide the best tradeoff between simulation speed and accuracy). This approach is very attractive as it allows text fixtures and programs to be validated and optimised before first silicon of the DUT is available, thus greatly increasing concurrent engineering capabilities and reducing the time between first silicon and validation of test programs.

[7] [8]

[9] [10] [11]

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