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Dynamic simulation of electron trapping and device lifetime of LDDnMOSFET
Solid-State Electronics Vol. 36, No. 2, pp. 291-299, 1993 Printed in Great Britain. All rights reserved
0038-1101/93 $6.00+0.00 Copyright 0 1993Pergamon Press Ltd
NOTE DYNAMIC SIMULATION OF ELECTRON TRAPPING AND DEVICE LIFETIME OF LDDnMOSFET (Received
19 August
We report on a dynamic time-dependent simulation of the device degradation of the lightly-doped drain (LDD) n MOSFET based on the lucky-electron model combined with a physical degradation atomic model. A physical degradation atomic model was utilized to develop an electron-trapping equation to map out the area and position of the damaged region induced by the hot-electron injection. The lateral electric field and the carrier concentration in the channel used in the simulation were obtained by the 2-D simulator MINIMOS 4 with the 1-D simulator SUPREM 3. The simulated results for the device lifetime were correlated with experimental results. INTRODUCTION Device simulations have shown that the LDD process reduces peak electric field in the transistor and also shifts the location of these peaks fields[l,2]. Although there is a large number of theoretical models[l8] that have dealt with this problem, there has not been any publication that dealt with the “complete” dynamic simulation based on the lucky electron model combined with a physical degradation atomic model. The integrated use with a physical degradation model involving electron trapping equations has been lacking. Most models to-date treated the lateral electric field, while we treat the device parameters such as the threshold voltage shift and drain current as a function of stress. Our model could provide a simple but unified approach to evaluate degradation of the different LDD structures which could facilitate optimization of LDD structures. It is noted that in the calculation of trapping process by Hiinsch et a/.[ IS], the input required is the trap distribution in the virgin oxide and the energy dependence of the density of state for the interface states. Therefore, to account for a modification of the interface states due to hot carrier stress is rather complicated. In our model, the dynamic simulation of aging was conducted by solving the trapped equation, which takes into account the probability of an electron injecting into the gate oxide and trapped by the trap center[l9]. This would alleviate the difficulty encountered in Ref.[lS]. In a short channel device, the hot-carrier effect can make the submicron device unstable and decrease its lifetime. The damage of the nMOSFET device by hot-carrier effect occurs at the Si-SiO, interface near the drain region[20]. The mechanisms of the device degradation have been widely studied. Previous studies were concerned about the trivalent Si atom. Several atom models of electron traps in Si-SiO, interface have been proposed[21-231. The hot-carrier effect results from the high peak electric field present in the channel due to the short channel length. Channel hot-electrons (CHE) gain sufficient energy to surmount the Si-SiO, barrier without suffering an energy loss collision with the- crystal while passing though the- high electric field region. Drain avalanche hot-electrons (DAHE) are the injected carriers resulting from avalanche multipli: cation at the drain. Substrate hot-electrons (SHE) are the substrate minority carrier (electron) which injects from the substrate to the gate SiO, through the depletion region. Sub-
1992)
strate current induced hot-carriers (SCHE) come from an excess of electrons that are generated from the hole substrate current impact ionization, which also can inject into the gate. Both SHE and SCHE are dependent on the substrate voltage[24], and they are neglected in our simulation. Hot electron injecting to the gate oxide can be trapped by the trapping centers making the gate oxide charged. The charged oxide layer may change the electrical characteristics of the device, such as the threshold voltage, transconductance, and drain current, etc. According to the physically atomic model and the lucky electron model, the rate of hot-electron trapping in SiO; can be modeled[l9]. In this work, we used SUPREM 3 to simulate the doping profile of the nMOSFET. A dynamic simulation of aging was conducted by solving the trapped equation simultaneously with MINIMOS 4. We used the threshold voltage to monitor the device degradation RESULTS AND DISCUSSION Figure 1 shows the electron trapping region of the sample (LDD 4) at different stress times. The maximum trapping region (Ntrap= 2 x 10” crn2) is close to 0.1 pm. The peak electric field shown in Fig. 2 is also located in the LDD region. The damaged regions appear to correlate well with the position of the peak lateral electric field. This tends to confirm that hot-electron injection occurs in the region of high electric field. As depicted in Fig. I, from time t, to time t, the damaged region quickly approaches the n+ region. After time t,, it approaches the n+ region and nearly stops there, and the maximum trapping region begins to extend to the channel. The damaged area will be limited by the electric field as the stress proceeds. The electric field at the Si-SiO, interface will change after electron is trapped in the oxide. In Fig. 2, the peak electric field is close to the n + region and it increases and moves to the n+ region rapidly after the stress is applied. Thereby the electron trapping region can extend to the n + region due to the shifted peak field at the beginning of the stress. The electric field close to the channel decreases and the hot-electron injection is subsequently suppressed. The probability of hot-electrons being present near the channel is decreased. Thus the spreading of the damaged area near the channel is not as fast as that near the n+ region. The V, shift measured by experiment and obtained from our simulation under the d.c. bias stress is shown in Fig. 3. The sample used in our experiment is an LDDnMOSFET with 1.2 pm channel length. The thickness of the gate oxide is 250A. The width of the spacer is 0.25 pm. The dose concentration and the implant energy of boron in the LDD region are 1.5 x 10’3cm-2 and 50KeV respectively. In the n + region the dose concentration and the implant energy of arsenic are 5 x IO” cmm2 and 80 KeV, respectively. The threshold voltage is 0.86 V before applying the stress. The result of the simulation agrees with the experiment, if the time t, is scaled by t,S, (the scaling term tcSeused here is 243.9). 297
298
Note
tl =lE5 t2=5E5 t3=1E6
Position
in the
channel
(pm)
Fig. 1. The electron trapping distribution of the sample (LDD 4) at different simulation times under the stress condition VD = 5.5 V, V, = 6 V and V, = V, = 0 V. It is noted that the scaling term is not known apriori, since the degradation of the device is directly related to the building up of oxide charges and interface states during the stress experiment, which could be specified by fitting experimental data. IObt
I
I
0.85
We have used the electron trapping formulation to analyze the local damaged region induced by hot-electron injection in a LDDnMOSFET. The damaged area is located just around the peak electric field. The damaged area is quickly extended toward the drain at the beginning of the
I
I
0.9
0.95
Distance
in the Y direction
1
I
3
1.05
1.1
Fig. 2. The lateral electric field of the sample (LDD 4) along the channel at different simtdation times under the stress condition V,, = 5.5 V, V. = 6 V and V, = Vs = 0 V.
299
Note
Time ( set) Fig. 3. The V, degradation
under the d.c. bias conditions (I’, = 5.5 V, V, = 6 V and V, = V, = 0 V) obtained from our experiment and simulation.
stress and pinches at the edge of the peak electric field near the drain. As the stress is applied, the damaged area will slowly extend backward to the channel.
6. Y. Hu, R. V. H. Booth and M. H. White, IEEE EIectron Devices 37, 2254 (1990). I. F. S. Lai and J. Y. Sun, IEEE Trans. Electron Devices
ED-32, 2803 (1985). CONCLUSION
Our simple model can provide insight into the physical aspects of the device for implementation in circuit simulators, which in turn could lead to tailoring the device parameters (V, and V,) for device and circuit optimization, simultaneously. Acknowledgements-Spectial thanks are due to ERSO of Industrial Technology Research Institute for help in the simulation and to Taiwan Semiconductor Manufacturing Company for supplying the test samples.
‘Departmentof Electrical Engineering
JIAN-YANGLINT Chung Cheng Institute of Technology PING-CHUNGTIEN* Ta-Shi, Tao- Yuan, Taiwan 33509, HEUY-LIANGHWANG* R.O. China *Department of Electrical Engineering National Tsing Hua University Hsin-Chu, Taiwan 30043, R.O. China
REFERENCES 1. E. Sangiorgi, M. Pinto, F. Venturi and W. Fichtner, IEEE Electron Device Lett. EDL-9, 13 (1988). 2. Y. Toyoshima, H. Nihira, M. Wada and K..Kanzaki, IEDM Tech. Dig.. D. 784 (1984). 3. Y. A. El-Man@ and A. R. Bdothroyd, IEEE Trans. Electron Devices ED-24, 254 (1977). 4. P. K. Ko, R. S. Muller and C. Hu, IEDM Tech. Dig.,
p. 600 (1981). 5. T. Y. Chan, P. K. Ko and C. Hu, IEEE Electron Device Len. EDM, 551 (1985).
8. F. S. Lai, Solid-St. Elecfron. 28, 959 (1985). 9. F. S. Lai, Y. C. Sun and S. H. Dhong, IEEE Electron Devices ED-33, 345 (1986).
Trans.
10. Y. C. Sun. M. R. Wardeman and S. E. Laux. IEEE Trans. Electron Devices ED-33, 1556 (1986). 11. K. Mayaram, J. C. Lee and C. Hu, IEEE Trans. Electron Devices ED-34, 1509 (1987). 12. G. S. Huang and C. Y. Wu, IEEE Trans. Electron Devices ED-%, 1311 (1987). 13. G. S. Huana and C. Y. Wu. IEEE Trans. Electron Devices 37, 667
(1990).
14. J. S. T. Huang, IEEE Trans. Electron Devices 35, 1158 (1988).
15. S. S. Chung, T. S. Lin and Y. G. Chen, IEEE Trans. Electron Devices 36, 1691 (1989).
16. P. H. Patek P. L. Kwang and N. Herr, IEEE Proc. 137, 291 (1990).
17. D. J. Mountain and D. M. Burnell, Solid-St. Electron. 33, 565 (1990).
18. W. Hansch, C. Mazure, A. Lill and M. K. Orlowski, IEEE Trans. Electron Devices 38, 512 (1991). 19. P. Robin. A. Samman and H. S. Bibvk, IEEE Trans. Electron Devices ED-35, 2229 (1988). _
20. Mario G. Ancona, Nelson S. Saks and Daniel McCarthy, IEEE Trans. Electron Devices ED-35, 2221 (1988). 21. Mohammad Aslam, IEEE Trans. Electron Devices ED-34, 2535 (1987). 22. P. M. Lenahan and P. V. Dressendorfer, J. appl. Phys.
55, 3459 (1984). 23. L. D. Thanh, M. Aslam and P. Balk, Solid-St. Electron. 29, 829 (1986). 24. E. Takeda, Y. Nakagome, H. Kume and S. Asia, IEE Proc. 30, 144 (1983).
0038-1101/93 $6.00+0.00 Copyright 0 1993Pergamon Press Ltd
NOTE DYNAMIC SIMULATION OF ELECTRON TRAPPING AND DEVICE LIFETIME OF LDDnMOSFET (Received
19 August
We report on a dynamic time-dependent simulation of the device degradation of the lightly-doped drain (LDD) n MOSFET based on the lucky-electron model combined with a physical degradation atomic model. A physical degradation atomic model was utilized to develop an electron-trapping equation to map out the area and position of the damaged region induced by the hot-electron injection. The lateral electric field and the carrier concentration in the channel used in the simulation were obtained by the 2-D simulator MINIMOS 4 with the 1-D simulator SUPREM 3. The simulated results for the device lifetime were correlated with experimental results. INTRODUCTION Device simulations have shown that the LDD process reduces peak electric field in the transistor and also shifts the location of these peaks fields[l,2]. Although there is a large number of theoretical models[l8] that have dealt with this problem, there has not been any publication that dealt with the “complete” dynamic simulation based on the lucky electron model combined with a physical degradation atomic model. The integrated use with a physical degradation model involving electron trapping equations has been lacking. Most models to-date treated the lateral electric field, while we treat the device parameters such as the threshold voltage shift and drain current as a function of stress. Our model could provide a simple but unified approach to evaluate degradation of the different LDD structures which could facilitate optimization of LDD structures. It is noted that in the calculation of trapping process by Hiinsch et a/.[ IS], the input required is the trap distribution in the virgin oxide and the energy dependence of the density of state for the interface states. Therefore, to account for a modification of the interface states due to hot carrier stress is rather complicated. In our model, the dynamic simulation of aging was conducted by solving the trapped equation, which takes into account the probability of an electron injecting into the gate oxide and trapped by the trap center[l9]. This would alleviate the difficulty encountered in Ref.[lS]. In a short channel device, the hot-carrier effect can make the submicron device unstable and decrease its lifetime. The damage of the nMOSFET device by hot-carrier effect occurs at the Si-SiO, interface near the drain region[20]. The mechanisms of the device degradation have been widely studied. Previous studies were concerned about the trivalent Si atom. Several atom models of electron traps in Si-SiO, interface have been proposed[21-231. The hot-carrier effect results from the high peak electric field present in the channel due to the short channel length. Channel hot-electrons (CHE) gain sufficient energy to surmount the Si-SiO, barrier without suffering an energy loss collision with the- crystal while passing though the- high electric field region. Drain avalanche hot-electrons (DAHE) are the injected carriers resulting from avalanche multipli: cation at the drain. Substrate hot-electrons (SHE) are the substrate minority carrier (electron) which injects from the substrate to the gate SiO, through the depletion region. Sub-
1992)
strate current induced hot-carriers (SCHE) come from an excess of electrons that are generated from the hole substrate current impact ionization, which also can inject into the gate. Both SHE and SCHE are dependent on the substrate voltage[24], and they are neglected in our simulation. Hot electron injecting to the gate oxide can be trapped by the trapping centers making the gate oxide charged. The charged oxide layer may change the electrical characteristics of the device, such as the threshold voltage, transconductance, and drain current, etc. According to the physically atomic model and the lucky electron model, the rate of hot-electron trapping in SiO; can be modeled[l9]. In this work, we used SUPREM 3 to simulate the doping profile of the nMOSFET. A dynamic simulation of aging was conducted by solving the trapped equation simultaneously with MINIMOS 4. We used the threshold voltage to monitor the device degradation RESULTS AND DISCUSSION Figure 1 shows the electron trapping region of the sample (LDD 4) at different stress times. The maximum trapping region (Ntrap= 2 x 10” crn2) is close to 0.1 pm. The peak electric field shown in Fig. 2 is also located in the LDD region. The damaged regions appear to correlate well with the position of the peak lateral electric field. This tends to confirm that hot-electron injection occurs in the region of high electric field. As depicted in Fig. I, from time t, to time t, the damaged region quickly approaches the n+ region. After time t,, it approaches the n+ region and nearly stops there, and the maximum trapping region begins to extend to the channel. The damaged area will be limited by the electric field as the stress proceeds. The electric field at the Si-SiO, interface will change after electron is trapped in the oxide. In Fig. 2, the peak electric field is close to the n + region and it increases and moves to the n+ region rapidly after the stress is applied. Thereby the electron trapping region can extend to the n + region due to the shifted peak field at the beginning of the stress. The electric field close to the channel decreases and the hot-electron injection is subsequently suppressed. The probability of hot-electrons being present near the channel is decreased. Thus the spreading of the damaged area near the channel is not as fast as that near the n+ region. The V, shift measured by experiment and obtained from our simulation under the d.c. bias stress is shown in Fig. 3. The sample used in our experiment is an LDDnMOSFET with 1.2 pm channel length. The thickness of the gate oxide is 250A. The width of the spacer is 0.25 pm. The dose concentration and the implant energy of boron in the LDD region are 1.5 x 10’3cm-2 and 50KeV respectively. In the n + region the dose concentration and the implant energy of arsenic are 5 x IO” cmm2 and 80 KeV, respectively. The threshold voltage is 0.86 V before applying the stress. The result of the simulation agrees with the experiment, if the time t, is scaled by t,S, (the scaling term tcSeused here is 243.9). 297
298
Note
tl =lE5 t2=5E5 t3=1E6
Position
in the
channel
(pm)
Fig. 1. The electron trapping distribution of the sample (LDD 4) at different simulation times under the stress condition VD = 5.5 V, V, = 6 V and V, = V, = 0 V. It is noted that the scaling term is not known apriori, since the degradation of the device is directly related to the building up of oxide charges and interface states during the stress experiment, which could be specified by fitting experimental data. IObt
I
I
0.85
We have used the electron trapping formulation to analyze the local damaged region induced by hot-electron injection in a LDDnMOSFET. The damaged area is located just around the peak electric field. The damaged area is quickly extended toward the drain at the beginning of the
I
I
0.9
0.95
Distance
in the Y direction
1
I
3
1.05
1.1
Fig. 2. The lateral electric field of the sample (LDD 4) along the channel at different simtdation times under the stress condition V,, = 5.5 V, V. = 6 V and V, = Vs = 0 V.
299
Note
Time ( set) Fig. 3. The V, degradation
under the d.c. bias conditions (I’, = 5.5 V, V, = 6 V and V, = V, = 0 V) obtained from our experiment and simulation.
stress and pinches at the edge of the peak electric field near the drain. As the stress is applied, the damaged area will slowly extend backward to the channel.
6. Y. Hu, R. V. H. Booth and M. H. White, IEEE EIectron Devices 37, 2254 (1990). I. F. S. Lai and J. Y. Sun, IEEE Trans. Electron Devices
ED-32, 2803 (1985). CONCLUSION
Our simple model can provide insight into the physical aspects of the device for implementation in circuit simulators, which in turn could lead to tailoring the device parameters (V, and V,) for device and circuit optimization, simultaneously. Acknowledgements-Spectial thanks are due to ERSO of Industrial Technology Research Institute for help in the simulation and to Taiwan Semiconductor Manufacturing Company for supplying the test samples.
‘Departmentof Electrical Engineering
JIAN-YANGLINT Chung Cheng Institute of Technology PING-CHUNGTIEN* Ta-Shi, Tao- Yuan, Taiwan 33509, HEUY-LIANGHWANG* R.O. China *Department of Electrical Engineering National Tsing Hua University Hsin-Chu, Taiwan 30043, R.O. China
REFERENCES 1. E. Sangiorgi, M. Pinto, F. Venturi and W. Fichtner, IEEE Electron Device Lett. EDL-9, 13 (1988). 2. Y. Toyoshima, H. Nihira, M. Wada and K..Kanzaki, IEDM Tech. Dig.. D. 784 (1984). 3. Y. A. El-Man@ and A. R. Bdothroyd, IEEE Trans. Electron Devices ED-24, 254 (1977). 4. P. K. Ko, R. S. Muller and C. Hu, IEDM Tech. Dig.,
p. 600 (1981). 5. T. Y. Chan, P. K. Ko and C. Hu, IEEE Electron Device Len. EDM, 551 (1985).
8. F. S. Lai, Solid-St. Elecfron. 28, 959 (1985). 9. F. S. Lai, Y. C. Sun and S. H. Dhong, IEEE Electron Devices ED-33, 345 (1986).
Trans.
10. Y. C. Sun. M. R. Wardeman and S. E. Laux. IEEE Trans. Electron Devices ED-33, 1556 (1986). 11. K. Mayaram, J. C. Lee and C. Hu, IEEE Trans. Electron Devices ED-34, 1509 (1987). 12. G. S. Huang and C. Y. Wu, IEEE Trans. Electron Devices ED-%, 1311 (1987). 13. G. S. Huana and C. Y. Wu. IEEE Trans. Electron Devices 37, 667
(1990).
14. J. S. T. Huang, IEEE Trans. Electron Devices 35, 1158 (1988).
15. S. S. Chung, T. S. Lin and Y. G. Chen, IEEE Trans. Electron Devices 36, 1691 (1989).
16. P. H. Patek P. L. Kwang and N. Herr, IEEE Proc. 137, 291 (1990).
17. D. J. Mountain and D. M. Burnell, Solid-St. Electron. 33, 565 (1990).
18. W. Hansch, C. Mazure, A. Lill and M. K. Orlowski, IEEE Trans. Electron Devices 38, 512 (1991). 19. P. Robin. A. Samman and H. S. Bibvk, IEEE Trans. Electron Devices ED-35, 2229 (1988). _
20. Mario G. Ancona, Nelson S. Saks and Daniel McCarthy, IEEE Trans. Electron Devices ED-35, 2221 (1988). 21. Mohammad Aslam, IEEE Trans. Electron Devices ED-34, 2535 (1987). 22. P. M. Lenahan and P. V. Dressendorfer, J. appl. Phys.
55, 3459 (1984). 23. L. D. Thanh, M. Aslam and P. Balk, Solid-St. Electron. 29, 829 (1986). 24. E. Takeda, Y. Nakagome, H. Kume and S. Asia, IEE Proc. 30, 144 (1983).