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Dynamic stressing of thin tunnel oxides: a way to emulate a single EEPROM cell programming function
Journal of Non-Crystalline Solids 245 (1999) 85±91
Dynamic stressing of thin tunnel oxides: a way to emulate a single EEPROM cell programming function C Plossu a
a,*
, J.M. Voisin a, B. Bos a, C. Raynaud a, R. Bouchakour b, P. Boivin c, B. Balland a
Laboratoire de Physique de la Mati ere (LPM), UMR CNRS 5511, Institut National des Sciences Appliqu ees de Lyon, 20 avenue A. Einstein, F-69621 Villeurbanne cedex, France b Ecole Nationale Sup erieure des T el ecommunications (ENST), 46 Rue Barrault, F-75013 Paris, France c ST Microelectronics, ZI Rousset, BP2, F-13106 Rousset cedex, France
Abstract An experimental set-up was implemented by which metal-oxide-semiconductor (MOS) capacitors are subjected to bipolar high voltage (up to 20 V) pulses similar to those used in programming electrically erasable programmable readonly memory (EEPROM) devices. Thin (9 nm) tunnel SiO2 oxides MOS capacitors were used. During stress, by means of capacitive coupling, the capacitors gate node was kept ¯oating so its potential was equivalent to that of the isolated ¯oating gate of a memory cell. The written and erased operations of memory cells which are based on Fowler± Nordheim (FN) tunneling injection mechanisms, were then reproduced on simple MOS capacitors. Via a high input impedance electronic circuit, the ¯oating gate potential was monitoring. A model based on a simple equivalent electrical circuit was used to simulate the transient regime of the FN current and the resulting ¯oating gate charge and potential during dynamic stressing. It was shown that the ¯oating gate accumulated charge is proportional to the maximum control gate voltage but is independent of the control gate pulse rise time. Ó 1999 Elsevier Science B.V. All rights reserved.
1. Introduction Stress induced degradation of thin oxides (<10 nm) under Fowler±Nordheim (FN) injection conditions represents a limiting factor in scaling down tunnel oxide thicknesses in non volatile electrically erasable programmable read-only memory (EEPROM) cells [1]. Bulk oxide charge trapping, Si/SiO2 interface degradation, and stress induced leakage current (SILC) at low pre-tunneling oxide electric ®elds (<5 MV cmÿ1 ), are the most im-
* Corresponding author. Tel.: +33-4 72 43 87 33; fax: +33-4 72 43 85 31; e-mail: [email protected]
portant phenomena involved in the degradation of thin tunnel oxides [1,2]. They have been assumed to be responsible for the programming window closure and for the decrease of the charge retention time observed in EEPROM cells after numerous write±erase programming cycles [1,2]. Stress induced oxide defects and associated conduction processes responsible of SILC are reported [3±5] but their properties still remain not well known. In most investigations, constant current or constant voltage FN injection techniques are used on metaloxide-semiconductor (MOS) capacitors or MOS transistors. These stress conditions are not representative of dynamic stressing conditions of tunnel oxides in EEPROM cells during write±erase cycles
0022-3093/99/$ ± see front matter Ó 1999 Elsevier Science B.V. All rights reserved. PII: S 0 0 2 2 - 3 0 9 3 ( 9 8 ) 0 0 8 7 5 - 8
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Fig. 1. Block-diagram of the experimental set-up for dynamic stressing of tunnel oxides. Ccer is a ceramic capacitor of 330 pF and Ctun is the capacitance of the MOS sample. VCG and VFG are, respectively, the control gate and ¯oating gate potentials.
[2,6]. During real programming operations, the tunnel oxide is subjected to short duration (<10 ms) bipolar high voltage pulses (up to 17 V) inducing more severe electric ®elds but smaller injected charge densities across the oxide compared to unipolar constant FN injection [7]. In this work, realistic voltage stress conditions of tunnel oxides in EEPROM cells were applied to macroscopic MOS capacitors. The advantage of using simple MOS capacitors is that classical techniques such as capacitance or current-voltage measurements can be easily performed after each aging step to study oxide defect generation kinetics.
tion, the MOS tunnel capacitor gate node is kept ¯oating and its potential, VFG , is ®xed by capacitive coupling as the potential of the isolated ¯oating gate in a memory cell. The capacitance, Ccer , was chosen equal to 330 pF close to that of the dielectric layer capacitance between the control gate and the ¯oating gate of an EEPROM cell in order to respect the real capacitive coupling ratio. It must be noted that the electrical wiring has been produced with precautions to avoid parasitic capacitances (short single conductor wiring rather than coaxial cables was used). In these conditions, the capacitive coupling ratio, aCG , between the control and the ¯oating gates is given by aCG
2. Experimental details Samples were fabricated 1 using a standard EEPROM technology. MOS capacitors with n+ÿ polySi gate, n-type substrate, 2 ´ 10ÿ4 cm2 area and 9 nm oxide thickness were used. The MOS samples were in the scribelines of integrated EEPROM wafers so they have undergone the same technological fabrication steps as the memory cells. The experimental set-up for dynamic stressing is described in Fig. 1. Bipolar symmetrical stress pulses, VCG , from a computer controlled pulse generator are applied to the MOS tunnel capacitor, Ctun , through a voltage ampli®er and a ceramic capacitor, Ccer . In this stress con®gura-
1 Samples were supplied by ST Microelectronics Company, Rousset, France
Ccer : Ccer Ctun
1
The VCG control gate pulses are de®ned in Fig. 2. VCGp and ÿVCGp are the maximum positive
Fig. 2. Parameters of the control gate VCG pulses. +VCGp and ÿVCGp are the maximum positive and negative voltage values, ton is the leading edge duration, tplate is the duration at the maxima and toff is the delay between two pulses.
C. Plossu et al. / Journal of Non-Crystalline Solids 245 (1999) 85±91
where q is the electronic charge, h the Planck constant, me the electron mass, me the eective mass of electrons in SiO2 (here assumed as 0.5me ) and U0 represents the potential barrier height between the injecting electrode and the tunnel oxide. The tunnel oxide electric ®eld was calculated by
and negative voltages respectively, ton is the rising time, tplate is the duration of the maximum voltages and toff is the delay at 0 V between two pulses. The ¯oating gate node could also be connected to a voltage-follower of very high input impedance (>1022 X) and very low polarization currents (<250 fA) in order not to introduce disturbances on the potential distribution across the two capacitors, Ctun and Ccer . A computer controlled digital oscilloscope was used to record VCG and VFG transient potentials during cycling. After each cycling step, the MOS capacitor could be switched to an electrometer or a capacitance meter to perform capacitance±voltage or current±voltage measurements.
Etun
3. Simulation procedure
QFG t Ccer VFG t ÿ VCG t Ctun VFG t
The simulation of the MOS capacitors dynamic behavior was based on the simple electrical model described in Fig. 3. The IFN current generator was given by the well-known FN tunneling current law [8]: B 2 ; 2 exp ÿ IFN Stun AEtun Etun where Etun is the tunnel oxide ®eld, Stun the tunnel injector area. A and B are the two FN constants which depend on the characteristics of the cathode, of the oxide and of their interface as follows [9]: p 3=2 8p 2me U0 q3 m e ; 3 ; B A 8phme U0 3hq
87
VFG ÿ VFB US ; ttun
4
where ttun is the tunnel oxide thickness, VFG the ¯oating gate voltage, VFB the ¯atband voltage of the MOS tunnel capacitor and US the surface potential at the Si±SiO2 interface. The computation of VFG time variations during one period of VCG pulses was based on the conservation of the ¯oating gate charge, QFG , as a function of time, t, which is expressed by Zt Q0
IFN t dt;
5
0
where Q0 is the initial zero time ¯oating gate charge. By deriving the two above equations, one obtains the dierential equation veri®ed by VFG i.e. dVFG t dVCG t ÿ IFN t Ccer ; 6 dt dt where IFN is expressed as a function of VFG by Eqs. (2) and (4). By solving the above equation, IFN (t), VFG (t) and QFG (t) variations can be obtained as a function of the VCG control gate pulses parameters. Ccer Ctun
4. Results 4.1. Experimental results
Fig. 3. Equivalent electrical circuit used for simulation.
Fig. 4(a) and (b) present typical experimental recordings of the control gate and ¯oating gate potential variations during one stress cycle for two control gate maximum voltage, VCGp . ton and toff were ®xed to 1 ms, tplate to 2 ms which are in the range of real operative programming conditions of an EEPROM cell. In Fig. 4(a)VCGp has been adjusted to 6 V. In these stress conditions, the electric
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Fig. 4. (a) VCG (t) and VFG (t) recordings for VCGp 6 V, ton toff 1 ms, tplate 2 ms. (b) VCG (t) and VFG (t) recordings for VCGp 17 V, ton toff 1 ms, tplate 2 ms.
®eld across the 9 nm tunnel oxide is not sucient to induce FN tunneling injection. In Fig. 4(b) VCGp has been ®xed to 17 V (typical value for EEPROM cells programmation) and very dierent VFG potential variations can be observed, due to the dynamic transient charge and discharge of the ¯oating gate during FN injection. The VFG voltage during the times, toff (VCG 0 V), called Vwrite and Verase (see Fig. 4(b)) correspond, respectively, to the written and erased states of the ¯oating gate. When holes are accumulated on the ¯oating gate, VFG is equal to Vwrite and is positive (written state) and after electrons are accumulated, VFG is equal to Verase and is negative (erased state). The experimental VFG recordings for dierent VCGp are shown in Fig. 5. While the increase of Vwrite and Verase as VCGp increases is seen, we observe that the variations of the maximum VFG and of the saturation levels VFGsat and VFGsatÿ de®ned in Fig. 4(b), when FN injection occurs (VCGp > 10.5 V), are very limited. In Fig. 6, it is shown that the variations of Vwrite , Verase , Qwrite and Qerase with VCGp are linear. Note that in Figs. 4(a), 4(b), 5 and 6, lines connecting experimental points have been drawn as guides to the eye. 4.2. Simulation results In Fig. 7, the simulated VFG has been plotted for three maximum VCGp (6 V, 15 V and 17 V) of the control gate pulses. We observe that the time variations of VFG are in excellent agreement with
Fig. 5. VFG (t) recordings for dierent VCGp s with ton toff 1 ms, tplate 2 ms. VCGp 9 V (h), 10.5 V (g), 12 V (f), 13.5 V (e), 15 V (d), 16.5 V (c), 18 V (b), 19.5 V (a).
the experimental curves of Figs. 4 and 5. For VCGp 6 V, no FN injection is possible so VFG is only determined by the capacitive coupling ratio, aCG . For VCGp 15 V and VCGp 17 V, FN injection occurs during the write and erase pulses. As on experimental curves in Fig. 5, we observe that Vwrite and Verase increase with VCGp but that VCGp has very little in¯uence no on the maximum and saturation VFG . The simulated FN current and VFG potential have been plotted in Figs. 8 and 9 respectively for three VCG rising times, ton (0.1 ms, 0.5 ms and 1 ms). As shown in Fig. 8, if ton is decreased at a
C. Plossu et al. / Journal of Non-Crystalline Solids 245 (1999) 85±91
Fig. 6. VWrite and Verase (left scale), Qwrite and Qerase (right scale) as a function of the maximum VCGp of the programming pulses (ton toff 1 ms, tplate 2 ms). For a ®xed VCGp , the difference between Verase and Vwrite is representative of the programming window width.
89
Fig. 9. Simulated VFG (t) curves for dierent leading edge durations, ton , of the control gate pulses (ton 1 ms, 0.5 ms and 0.1 ms) with tplate 2 ms and VCGp 17 V.
®xed VCGp , the maximum FN current, IFNmax , increases. On an other hand, as IFNmax increases, the injection duration decreases. In Fig. 9, it can be observed that for ®xed values of tplate and VCGp , Vwrite and Verase values do not depend on ton . 5. Discussion
Fig. 7. Simulated VFG (t) curves for three maximum voltages, VCGp (VCGp 6 V, 15 V and 17 V) with ton 1 ms, toff 1 ms and tplate 2 ms.
The dynamic transient variations of VFG as a function of the maximum VCGp have been experimentally obtained and found in agreement with simulated curves. In the stress conditions of Fig. 4(a) (VCGp 6 V), the maximum electric ®eld across the 9 nm tunnel oxide reached during one programming cycle, remains less than the threshold ®eld for FN tunneling injection so IFN is null. According to Eq. (5) with Q0 0 and QFG 0 (initially uncharged ¯oating gate), VFG is then only determined by the capacitive coupling ratio, aCG , i.e. VFG t
Fig. 8. Simulated IFN (t) curves for dierent leading edge durations, ton , of the control gate pulses (ton 1 ms, 0.5 ms and 0.1 ms) with tplate 2 ms and VCGp 17 V.
Ccer VCG t aCG VCG t: Ccer Ctun
7
ÿ From the measurements of V FGp and VFGp in Fig. 4(a), aCG was found equal to 0.82 in good agreement with the calculated aCG from Eq. (1) with Ctun 75 pF. This result proves that all parasitic capacitances due to electrical wiring and connections have been actually minimized. From the experimental curves of Fig. 4(b) (VCGp 17 V) and from the simulated curves of
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Fig. 8, we analyse the transient response of VFG in the case of the positive erase cycle, for example. The ¯oating gate is initially in the written state; its potential is Vwrite and the corresponding accumulated charge, Qwrite , on the ¯oating gate can be expressed from Eq. (5) with VCG 0 as Qwrite Ctun Ccer Vwrite :
8
Four time domains referred as Dt1 , Dt2 , Dt3 and Dt4 in Fig. 4(b) can then be distinguished. During Dt1 , VCG increases linearly with time. No tunnel injection occurs (IFN 0). By integration of Eq. (6), it is found that VFG increases linearly as a function of time according to VFG Vwrite aCG VCG :
9
At the beginning of Dt2 , VFG reaches the threshold voltage for tunnel FN injection; electrons are then injected from the substrate into the ¯oating gate. While VCG still increases, the accumulated negative charge limits the increase of VFG . When the steady state regime is reached, VFG is at its maximum. During Dt3 , VCG remains constant at its maximum, VCGp . Electrons are still injected inducing a decrease of the ¯oating gate potential until VFG becomes less than the threshold voltage for FN injection. At this time, VFG stops decreasing and reaches V FGsat displayed in Fig. 4(b). The ¯oating gate is now in the erase state and from Eq. (5), the ¯oating gate charge, Qerase , is expressed as Qerase Ccer Ctun VFGsat ÿ Ccer VCGp :
10
During Dt4 , VCG is null and the ¯oating gate potential is now Verase given by Verase
Qerase VFGsat ÿ aCG VCGp : Ccer Ctun
11
A similar argument in the case of the negative write cycle should lead to Vwrite
Qwrite ÿ VFGsat aCG VCGp ; Ccer Ctun
12
where Vÿ FGsat is the saturation VFG during the write cycle (Fig. 4(b)). As expected from Eqs. (11) and (12), the variations of Vwrite and Verase with VCGp shown in Fig. 6 are linear.
In an EEPROM cell, the MOS transistor lying under the ¯oating and control gates is called state transistor; its threshold voltage depends on the accumulated charge on the ¯oating gate. The programming window width, DVth , of the memory cell is then de®ned as the dierence between the threshold voltages of the state transistor in the written and erased states. By analogy, in our case, if no charge trapping in the tunnel oxide is assumed, DVth would be expressed as DVth
Qerase ÿ Qwrite 1 Verase ÿ Vwrite : Ccer aCG
13
The programming window width, DVth , is proportional to the total variation of the charge accumulated on the ¯oating gate between the written and erased states. So Verase ÿ Vwrite which can be experimentally determined, is proportional to DVth . The study of DVth variations after successive write±erase cycles is very important for EEPROM reliability. A closure of the programming window which is often observed can induce memory reading errors. The simulations in Figs. 8 and 9 show that the greatest in¯uence of the leading edge duration ton of the VCG control gate pulses, concerns the maximum FN current through the tunnel oxide during the write and erase cycles. From Eq. (6), the maximum current level IFNmax in the steady state regime (dVFG /dt 0) during Dt2 , is given by IFNmax Ccer
dVCG VCGp Ccer : dt ton
14
Eq. (14) shows that IFNmax is inversely proportional to ton . For example, with Ccer 330 pF and VCGp 17 V, for ton 1 ms, IFNmax is equal to 5.6 lA while for ton 0.1 ms, IFNmax is ten times greater i.e. equal to 56 lA. But in the same time, as ton is reduced, the FN injection duration decreases as shown in Fig. 8, so when the steady state is reached during the duration, tplate , the total injected charge remains constant and does not depend on ton . In Fig. 9, we can actually see that Vwrite and Verase do not vary with ton , so ton has no eect on the accumulated charge in the ¯oating gate.
C. Plossu et al. / Journal of Non-Crystalline Solids 245 (1999) 85±91
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6. Conclusion
References
A dynamic stressing technique of thin tunnel oxides was implemented. This technique is an excellent way to emulate a single EEPROM cell programming function on simple tunnel oxide MOS capacitors by reproducing similar FN injection stress conditions. The dynamic properties of MOS capacitors during one programming cycle was well simulated using a simple electrical model. From the simulation we predict the magnitude of the transient electric ®eld across the tunnel oxide and of the accumulated charge in the ¯oating gate as a function of control gate programming pulse parameters. We show that the ¯oating gate accumulated charge is proportional to the maximum VCG voltage but is independent of the VCG rise time, ton . On the contrary, the maximum FN current through the tunnel oxide is inversely proportional to ton so the magnitude of the electric ®eld across the tunnel oxide increases as ton decreases.
[1] P. Pavan, R. Bez, P. Olivo, E. Zanoni, Proc. IEEE 85 (1997) 1248. [2] J.S. Witters, G. Groeseneken, H.E. Maes, IEEE Trans. Electron Devices 36 (1989) 1663. [3] K. Sakakibara, N. Ajika, M. Hatamaka, H. Miyoshi, A. Yasuoka, IEEE Trans. Electron Devices 44 (1997) 986. [4] E.F. Runnion, S.M. Gladstone, R.S. Scott, D.J. Dumin, L. Lie, J.C. Mitros, IEEE Trans. Electron Devices 44 (1997) 993. [5] S. Satoh, G. Hemink, K. Hatakeyama, S. Aritome, IEEE Trans. Electron Devices 45 (1998) 482. [6] R. Rodriguez, N. Na®a, J. Sune, X. Aymerich, IEEE Trans. Electron Devices 45 (1998) 881. [7] M. Ciappa, A. Naitana, M. Vanzi, Microelectron. Reliability 37 (1997) 1525. [8] M. Lenzlinger, E. Snow, J. Appl. Phys. 40 (1969) 278. [9] M. Lanzoni, J. Sune, P. Olivo, B. Ricco, IEEE Trans. Electron Devices 40 (1993) 951.
Dynamic stressing of thin tunnel oxides: a way to emulate a single EEPROM cell programming function C Plossu a
a,*
, J.M. Voisin a, B. Bos a, C. Raynaud a, R. Bouchakour b, P. Boivin c, B. Balland a
Laboratoire de Physique de la Mati ere (LPM), UMR CNRS 5511, Institut National des Sciences Appliqu ees de Lyon, 20 avenue A. Einstein, F-69621 Villeurbanne cedex, France b Ecole Nationale Sup erieure des T el ecommunications (ENST), 46 Rue Barrault, F-75013 Paris, France c ST Microelectronics, ZI Rousset, BP2, F-13106 Rousset cedex, France
Abstract An experimental set-up was implemented by which metal-oxide-semiconductor (MOS) capacitors are subjected to bipolar high voltage (up to 20 V) pulses similar to those used in programming electrically erasable programmable readonly memory (EEPROM) devices. Thin (9 nm) tunnel SiO2 oxides MOS capacitors were used. During stress, by means of capacitive coupling, the capacitors gate node was kept ¯oating so its potential was equivalent to that of the isolated ¯oating gate of a memory cell. The written and erased operations of memory cells which are based on Fowler± Nordheim (FN) tunneling injection mechanisms, were then reproduced on simple MOS capacitors. Via a high input impedance electronic circuit, the ¯oating gate potential was monitoring. A model based on a simple equivalent electrical circuit was used to simulate the transient regime of the FN current and the resulting ¯oating gate charge and potential during dynamic stressing. It was shown that the ¯oating gate accumulated charge is proportional to the maximum control gate voltage but is independent of the control gate pulse rise time. Ó 1999 Elsevier Science B.V. All rights reserved.
1. Introduction Stress induced degradation of thin oxides (<10 nm) under Fowler±Nordheim (FN) injection conditions represents a limiting factor in scaling down tunnel oxide thicknesses in non volatile electrically erasable programmable read-only memory (EEPROM) cells [1]. Bulk oxide charge trapping, Si/SiO2 interface degradation, and stress induced leakage current (SILC) at low pre-tunneling oxide electric ®elds (<5 MV cmÿ1 ), are the most im-
* Corresponding author. Tel.: +33-4 72 43 87 33; fax: +33-4 72 43 85 31; e-mail: [email protected]
portant phenomena involved in the degradation of thin tunnel oxides [1,2]. They have been assumed to be responsible for the programming window closure and for the decrease of the charge retention time observed in EEPROM cells after numerous write±erase programming cycles [1,2]. Stress induced oxide defects and associated conduction processes responsible of SILC are reported [3±5] but their properties still remain not well known. In most investigations, constant current or constant voltage FN injection techniques are used on metaloxide-semiconductor (MOS) capacitors or MOS transistors. These stress conditions are not representative of dynamic stressing conditions of tunnel oxides in EEPROM cells during write±erase cycles
0022-3093/99/$ ± see front matter Ó 1999 Elsevier Science B.V. All rights reserved. PII: S 0 0 2 2 - 3 0 9 3 ( 9 8 ) 0 0 8 7 5 - 8
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C. Plossu et al. / Journal of Non-Crystalline Solids 245 (1999) 85±91
Fig. 1. Block-diagram of the experimental set-up for dynamic stressing of tunnel oxides. Ccer is a ceramic capacitor of 330 pF and Ctun is the capacitance of the MOS sample. VCG and VFG are, respectively, the control gate and ¯oating gate potentials.
[2,6]. During real programming operations, the tunnel oxide is subjected to short duration (<10 ms) bipolar high voltage pulses (up to 17 V) inducing more severe electric ®elds but smaller injected charge densities across the oxide compared to unipolar constant FN injection [7]. In this work, realistic voltage stress conditions of tunnel oxides in EEPROM cells were applied to macroscopic MOS capacitors. The advantage of using simple MOS capacitors is that classical techniques such as capacitance or current-voltage measurements can be easily performed after each aging step to study oxide defect generation kinetics.
tion, the MOS tunnel capacitor gate node is kept ¯oating and its potential, VFG , is ®xed by capacitive coupling as the potential of the isolated ¯oating gate in a memory cell. The capacitance, Ccer , was chosen equal to 330 pF close to that of the dielectric layer capacitance between the control gate and the ¯oating gate of an EEPROM cell in order to respect the real capacitive coupling ratio. It must be noted that the electrical wiring has been produced with precautions to avoid parasitic capacitances (short single conductor wiring rather than coaxial cables was used). In these conditions, the capacitive coupling ratio, aCG , between the control and the ¯oating gates is given by aCG
2. Experimental details Samples were fabricated 1 using a standard EEPROM technology. MOS capacitors with n+ÿ polySi gate, n-type substrate, 2 ´ 10ÿ4 cm2 area and 9 nm oxide thickness were used. The MOS samples were in the scribelines of integrated EEPROM wafers so they have undergone the same technological fabrication steps as the memory cells. The experimental set-up for dynamic stressing is described in Fig. 1. Bipolar symmetrical stress pulses, VCG , from a computer controlled pulse generator are applied to the MOS tunnel capacitor, Ctun , through a voltage ampli®er and a ceramic capacitor, Ccer . In this stress con®gura-
1 Samples were supplied by ST Microelectronics Company, Rousset, France
Ccer : Ccer Ctun
1
The VCG control gate pulses are de®ned in Fig. 2. VCGp and ÿVCGp are the maximum positive
Fig. 2. Parameters of the control gate VCG pulses. +VCGp and ÿVCGp are the maximum positive and negative voltage values, ton is the leading edge duration, tplate is the duration at the maxima and toff is the delay between two pulses.
C. Plossu et al. / Journal of Non-Crystalline Solids 245 (1999) 85±91
where q is the electronic charge, h the Planck constant, me the electron mass, me the eective mass of electrons in SiO2 (here assumed as 0.5me ) and U0 represents the potential barrier height between the injecting electrode and the tunnel oxide. The tunnel oxide electric ®eld was calculated by
and negative voltages respectively, ton is the rising time, tplate is the duration of the maximum voltages and toff is the delay at 0 V between two pulses. The ¯oating gate node could also be connected to a voltage-follower of very high input impedance (>1022 X) and very low polarization currents (<250 fA) in order not to introduce disturbances on the potential distribution across the two capacitors, Ctun and Ccer . A computer controlled digital oscilloscope was used to record VCG and VFG transient potentials during cycling. After each cycling step, the MOS capacitor could be switched to an electrometer or a capacitance meter to perform capacitance±voltage or current±voltage measurements.
Etun
3. Simulation procedure
QFG t Ccer VFG t ÿ VCG t Ctun VFG t
The simulation of the MOS capacitors dynamic behavior was based on the simple electrical model described in Fig. 3. The IFN current generator was given by the well-known FN tunneling current law [8]: B 2 ; 2 exp ÿ IFN Stun AEtun Etun where Etun is the tunnel oxide ®eld, Stun the tunnel injector area. A and B are the two FN constants which depend on the characteristics of the cathode, of the oxide and of their interface as follows [9]: p 3=2 8p 2me U0 q3 m e ; 3 ; B A 8phme U0 3hq
87
VFG ÿ VFB US ; ttun
4
where ttun is the tunnel oxide thickness, VFG the ¯oating gate voltage, VFB the ¯atband voltage of the MOS tunnel capacitor and US the surface potential at the Si±SiO2 interface. The computation of VFG time variations during one period of VCG pulses was based on the conservation of the ¯oating gate charge, QFG , as a function of time, t, which is expressed by Zt Q0
IFN t dt;
5
0
where Q0 is the initial zero time ¯oating gate charge. By deriving the two above equations, one obtains the dierential equation veri®ed by VFG i.e. dVFG t dVCG t ÿ IFN t Ccer ; 6 dt dt where IFN is expressed as a function of VFG by Eqs. (2) and (4). By solving the above equation, IFN (t), VFG (t) and QFG (t) variations can be obtained as a function of the VCG control gate pulses parameters. Ccer Ctun
4. Results 4.1. Experimental results
Fig. 3. Equivalent electrical circuit used for simulation.
Fig. 4(a) and (b) present typical experimental recordings of the control gate and ¯oating gate potential variations during one stress cycle for two control gate maximum voltage, VCGp . ton and toff were ®xed to 1 ms, tplate to 2 ms which are in the range of real operative programming conditions of an EEPROM cell. In Fig. 4(a)VCGp has been adjusted to 6 V. In these stress conditions, the electric
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Fig. 4. (a) VCG (t) and VFG (t) recordings for VCGp 6 V, ton toff 1 ms, tplate 2 ms. (b) VCG (t) and VFG (t) recordings for VCGp 17 V, ton toff 1 ms, tplate 2 ms.
®eld across the 9 nm tunnel oxide is not sucient to induce FN tunneling injection. In Fig. 4(b) VCGp has been ®xed to 17 V (typical value for EEPROM cells programmation) and very dierent VFG potential variations can be observed, due to the dynamic transient charge and discharge of the ¯oating gate during FN injection. The VFG voltage during the times, toff (VCG 0 V), called Vwrite and Verase (see Fig. 4(b)) correspond, respectively, to the written and erased states of the ¯oating gate. When holes are accumulated on the ¯oating gate, VFG is equal to Vwrite and is positive (written state) and after electrons are accumulated, VFG is equal to Verase and is negative (erased state). The experimental VFG recordings for dierent VCGp are shown in Fig. 5. While the increase of Vwrite and Verase as VCGp increases is seen, we observe that the variations of the maximum VFG and of the saturation levels VFGsat and VFGsatÿ de®ned in Fig. 4(b), when FN injection occurs (VCGp > 10.5 V), are very limited. In Fig. 6, it is shown that the variations of Vwrite , Verase , Qwrite and Qerase with VCGp are linear. Note that in Figs. 4(a), 4(b), 5 and 6, lines connecting experimental points have been drawn as guides to the eye. 4.2. Simulation results In Fig. 7, the simulated VFG has been plotted for three maximum VCGp (6 V, 15 V and 17 V) of the control gate pulses. We observe that the time variations of VFG are in excellent agreement with
Fig. 5. VFG (t) recordings for dierent VCGp s with ton toff 1 ms, tplate 2 ms. VCGp 9 V (h), 10.5 V (g), 12 V (f), 13.5 V (e), 15 V (d), 16.5 V (c), 18 V (b), 19.5 V (a).
the experimental curves of Figs. 4 and 5. For VCGp 6 V, no FN injection is possible so VFG is only determined by the capacitive coupling ratio, aCG . For VCGp 15 V and VCGp 17 V, FN injection occurs during the write and erase pulses. As on experimental curves in Fig. 5, we observe that Vwrite and Verase increase with VCGp but that VCGp has very little in¯uence no on the maximum and saturation VFG . The simulated FN current and VFG potential have been plotted in Figs. 8 and 9 respectively for three VCG rising times, ton (0.1 ms, 0.5 ms and 1 ms). As shown in Fig. 8, if ton is decreased at a
C. Plossu et al. / Journal of Non-Crystalline Solids 245 (1999) 85±91
Fig. 6. VWrite and Verase (left scale), Qwrite and Qerase (right scale) as a function of the maximum VCGp of the programming pulses (ton toff 1 ms, tplate 2 ms). For a ®xed VCGp , the difference between Verase and Vwrite is representative of the programming window width.
89
Fig. 9. Simulated VFG (t) curves for dierent leading edge durations, ton , of the control gate pulses (ton 1 ms, 0.5 ms and 0.1 ms) with tplate 2 ms and VCGp 17 V.
®xed VCGp , the maximum FN current, IFNmax , increases. On an other hand, as IFNmax increases, the injection duration decreases. In Fig. 9, it can be observed that for ®xed values of tplate and VCGp , Vwrite and Verase values do not depend on ton . 5. Discussion
Fig. 7. Simulated VFG (t) curves for three maximum voltages, VCGp (VCGp 6 V, 15 V and 17 V) with ton 1 ms, toff 1 ms and tplate 2 ms.
The dynamic transient variations of VFG as a function of the maximum VCGp have been experimentally obtained and found in agreement with simulated curves. In the stress conditions of Fig. 4(a) (VCGp 6 V), the maximum electric ®eld across the 9 nm tunnel oxide reached during one programming cycle, remains less than the threshold ®eld for FN tunneling injection so IFN is null. According to Eq. (5) with Q0 0 and QFG 0 (initially uncharged ¯oating gate), VFG is then only determined by the capacitive coupling ratio, aCG , i.e. VFG t
Fig. 8. Simulated IFN (t) curves for dierent leading edge durations, ton , of the control gate pulses (ton 1 ms, 0.5 ms and 0.1 ms) with tplate 2 ms and VCGp 17 V.
Ccer VCG t aCG VCG t: Ccer Ctun
7
ÿ From the measurements of V FGp and VFGp in Fig. 4(a), aCG was found equal to 0.82 in good agreement with the calculated aCG from Eq. (1) with Ctun 75 pF. This result proves that all parasitic capacitances due to electrical wiring and connections have been actually minimized. From the experimental curves of Fig. 4(b) (VCGp 17 V) and from the simulated curves of
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Fig. 8, we analyse the transient response of VFG in the case of the positive erase cycle, for example. The ¯oating gate is initially in the written state; its potential is Vwrite and the corresponding accumulated charge, Qwrite , on the ¯oating gate can be expressed from Eq. (5) with VCG 0 as Qwrite Ctun Ccer Vwrite :
8
Four time domains referred as Dt1 , Dt2 , Dt3 and Dt4 in Fig. 4(b) can then be distinguished. During Dt1 , VCG increases linearly with time. No tunnel injection occurs (IFN 0). By integration of Eq. (6), it is found that VFG increases linearly as a function of time according to VFG Vwrite aCG VCG :
9
At the beginning of Dt2 , VFG reaches the threshold voltage for tunnel FN injection; electrons are then injected from the substrate into the ¯oating gate. While VCG still increases, the accumulated negative charge limits the increase of VFG . When the steady state regime is reached, VFG is at its maximum. During Dt3 , VCG remains constant at its maximum, VCGp . Electrons are still injected inducing a decrease of the ¯oating gate potential until VFG becomes less than the threshold voltage for FN injection. At this time, VFG stops decreasing and reaches V FGsat displayed in Fig. 4(b). The ¯oating gate is now in the erase state and from Eq. (5), the ¯oating gate charge, Qerase , is expressed as Qerase Ccer Ctun VFGsat ÿ Ccer VCGp :
10
During Dt4 , VCG is null and the ¯oating gate potential is now Verase given by Verase
Qerase VFGsat ÿ aCG VCGp : Ccer Ctun
11
A similar argument in the case of the negative write cycle should lead to Vwrite
Qwrite ÿ VFGsat aCG VCGp ; Ccer Ctun
12
where Vÿ FGsat is the saturation VFG during the write cycle (Fig. 4(b)). As expected from Eqs. (11) and (12), the variations of Vwrite and Verase with VCGp shown in Fig. 6 are linear.
In an EEPROM cell, the MOS transistor lying under the ¯oating and control gates is called state transistor; its threshold voltage depends on the accumulated charge on the ¯oating gate. The programming window width, DVth , of the memory cell is then de®ned as the dierence between the threshold voltages of the state transistor in the written and erased states. By analogy, in our case, if no charge trapping in the tunnel oxide is assumed, DVth would be expressed as DVth
Qerase ÿ Qwrite 1 Verase ÿ Vwrite : Ccer aCG
13
The programming window width, DVth , is proportional to the total variation of the charge accumulated on the ¯oating gate between the written and erased states. So Verase ÿ Vwrite which can be experimentally determined, is proportional to DVth . The study of DVth variations after successive write±erase cycles is very important for EEPROM reliability. A closure of the programming window which is often observed can induce memory reading errors. The simulations in Figs. 8 and 9 show that the greatest in¯uence of the leading edge duration ton of the VCG control gate pulses, concerns the maximum FN current through the tunnel oxide during the write and erase cycles. From Eq. (6), the maximum current level IFNmax in the steady state regime (dVFG /dt 0) during Dt2 , is given by IFNmax Ccer
dVCG VCGp Ccer : dt ton
14
Eq. (14) shows that IFNmax is inversely proportional to ton . For example, with Ccer 330 pF and VCGp 17 V, for ton 1 ms, IFNmax is equal to 5.6 lA while for ton 0.1 ms, IFNmax is ten times greater i.e. equal to 56 lA. But in the same time, as ton is reduced, the FN injection duration decreases as shown in Fig. 8, so when the steady state is reached during the duration, tplate , the total injected charge remains constant and does not depend on ton . In Fig. 9, we can actually see that Vwrite and Verase do not vary with ton , so ton has no eect on the accumulated charge in the ¯oating gate.
C. Plossu et al. / Journal of Non-Crystalline Solids 245 (1999) 85±91
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6. Conclusion
References
A dynamic stressing technique of thin tunnel oxides was implemented. This technique is an excellent way to emulate a single EEPROM cell programming function on simple tunnel oxide MOS capacitors by reproducing similar FN injection stress conditions. The dynamic properties of MOS capacitors during one programming cycle was well simulated using a simple electrical model. From the simulation we predict the magnitude of the transient electric ®eld across the tunnel oxide and of the accumulated charge in the ¯oating gate as a function of control gate programming pulse parameters. We show that the ¯oating gate accumulated charge is proportional to the maximum VCG voltage but is independent of the VCG rise time, ton . On the contrary, the maximum FN current through the tunnel oxide is inversely proportional to ton so the magnitude of the electric ®eld across the tunnel oxide increases as ton decreases.
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