Effect of a DC bias on the conductivity of gadolinia doped ceria thin films

Accepted Manuscript Effect of a DC bias on the conductivity of gadolinia doped ceria thin films Soumitra S. Sulekar, John E. Ordonez, Isabel C. Arango, Maria E. Gomez, Juan C. Nino PII:

S0013-4686(19)30325-1

DOI:

https://doi.org/10.1016/j.electacta.2019.02.073

Reference:

EA 33664

To appear in:

Electrochimica Acta

Received Date: 18 August 2018 Revised Date:

24 January 2019

Accepted Date: 15 February 2019

Please cite this article as: S.S. Sulekar, J.E. Ordonez, I.C. Arango, M.E. Gomez, J.C. Nino, Effect of a DC bias on the conductivity of gadolinia doped ceria thin films, Electrochimica Acta (2019), doi: https:// doi.org/10.1016/j.electacta.2019.02.073. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

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Effect of a DC bias on the Conductivity of Gadolinia Doped Ceria

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Thin Films

Soumitra S. Sulekar1*, John E. Ordonez2, Isabel C. Arango2, Maria E. Gomez2 and Juan C. Nino1

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1

Department of Materials Science and Engineering, University of Florida, Gainesville,

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Florida 32611, USA 2

Grupo de Películas Delgadas, Departamento de Física, Universidad del Valle, A.A.

25360 Cali, Colombia

*Corresponding author. [email protected]

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Abstract

This paper studies the phenomenon of mixed ionic and electronic conductivity in magnetron sputtered gadolinia doped ceria thin films under the effect of an applied DC

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bias. Electrochemical impedance spectroscopy was used to measure the change in impedance under an alternating voltage of 300 mV, at temperatures between 25
C and

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150
C and applied biases of ~ 4 - 20 kV/mm, which are much higher than any prior study. The application of a DC bias produces a reversible decrease in both the grain and grain boundary resistances for GDC, and the films exhibit bias-induced mixed ionic and electronic conductivity. Additional features become visible in the Nyquist plots, indicating possible novel mechanisms in response to bias. Particularly interesting is the appearance of inductive loops in the low frequency regime, at very high bias values,

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rarely seen for such materials. Here this novel behavior was analyzed by fitting the data using equivalent circuits to understand the underlying mechanisms at play. Through this work, it is established that the change in behavior is attributed to electronic

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conduction through grain boundaries along the direction of the applied field.

Keywords: Impedance Spectroscopy; DC Bias; Mixed Conductivity; Electronic Injection;

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Cerium Oxide.

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1. Introduction

Rare earth doped ceria compounds are excellent ionic conductors that are used as electrolytes in intermediate temperature (500-700ºC) solid oxide fuel cells (SOFCs), and at higher temperatures (800°C and above) in sol ar-solar thermal reactors due to

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their mixed ionic-electronic conductivity and catalytic activity [1–7]. In general, doped ceria and in particular Gd-doped ceria, is attractive due to its good ionic conductivity as well as thermal and stoichiometric stability compared to other materials [8–10]. The

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ionic conductivity in ceria is made possible by rare earth acceptor dopants (in this work gadolinium) which result in the formation of oxygen vacancies to achieve charge

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balance. Here we look at the effect of an applied DC bias on the electrical conduction and specifically on the ionic and induced electronic conductivity. This charge injection phenomenon is significant from the point of view of application of doped ceria compounds as reversible mixed conductors at low temperatures. As previously stated, mixed conduction is a well-known phenomenon for ceria at high temperatures, and thus it becomes pertinent to look at the considerable amount prior work on its mixed ionic and electronic conductivity.

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For example, reducing atmospheres have been shown to introduce electronic conductivity in pure ceria materials, turning them from poor ionic conductors to good

1 OOx → VO•• + O2 + 2e′ 2

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electronic conductors. The associated reaction is shown in equation (1). (1)

It has been shown that under a reducing atmosphere, the bulk conductivity of 1%

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yttria doped ceria increases only slightly, whereas there is a drastic increase in the grain boundary conductivity [11]. Assuming a brick layer model, grain boundaries can be

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either parallel or perpendicular to the direction of current flow. Since any conductivity across grain boundaries must be in series to the bulk flow, a more pronounced partial electronic conductivity at the grain boundaries was concluded to be due to conduction along grain boundaries parallel to the current flow. Similarly, with nanocrystalline ceria,

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it has been shown that under reducing atmospheres a much higher conductivity is observed due to accumulation of electrons and depletion of oxygen vacancies in the space-charge layer near grain boundaries, in so called ‘inversion layers’.

It is the

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presence of such inversion layers with high electron concentration which makes the grain boundaries more conductive than bulk. Hence the ions flow in the bulk and across

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the grain boundaries perpendicular to the current flow, whereas electrons flow along the grain boundaries parallel to the current flow. This effect was shown for both acceptordoped and undoped ceria bulk samples [11,12]. A DC bias was initially used to study the nature of grain boundaries in acceptor doped ceria by Guo et al. [13], where individual grain boundaries showed non-linear current-voltage behavior, and the effective grain boundary thickness was found to

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increase with increasing bias. Work by Guo and Waser [14] involving yttria doped ceria, has reported asymmetrical changes in the width of space charge layers at the grain boundaries under bias. However, since the focus of the work was on the space charge

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theory for blocking grain boundaries, the mechanism behind the improved conduction was not further investigated.

The effect of bias was studied in detail only much later by Masó and West [15].

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Their study concentrated on the effect of a small DC bias on the electronic conductivity in bulk yttria stabilized zirconia (YSZ) samples. A drop in the resistance was observed

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under a DC bias, which was attributed to the onset of electronic conduction, and the possibility of variable oxidation states of oxide ions and their response to a DC bias. The behavior was modelled using equivalent circuits where a resistance starts to appear parallel to the original equivalent circuit (only low bias values ~5-100 V/cm were

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studied). This new resistance was attributed to electronic conduction introduced along a parallel pathway [15]. There has also been work on various other acceptor doped oxides like BaTiO3, CaTiO3, SrTiO3 and BiFeO3 which have attributed field enhanced

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conductivity in these materials variously to ionization processes, change in local defect equilibria, reactions between oxygen and surface species, underbonded oxide ions, and

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unique electronic structure in the defect complexes in these materials [16–21]. Most of the work has been on bulk samples under relatively low bias fields. However, given that majority of the drop in the applied voltage will be across the grain boundaries, the electric fields at grain boundaries are anticipated to be much higher. To better study this phenomenon under higher applied fields, thin films are required. Rare earth doped ceria thin films have been studied extensively for reduced temperature fuel cell

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operation owing to faster ionic conduction paths they provide. The higher conductivity is attributed mainly to dominant nano-scale and interfacial phenomena, and warrant more studies [22,23].

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More recently, Moballegh and Dickey studied the effect of bias on single crystal TiO2-x electroded with Pt [24]. The use of a single crystal instead of a polycrystalline material paints a clearer picture in this case.

The Pt electrode interfaces exhibit

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Schottky contact behavior. The applied electric field induces a redistribution of point defects throughout the crystal, causing accumulation of Ti interstitials and oxygen The same is also corroborated by the Brouwer defect

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vacancies at the cathode.

diagram for titania [24] where under low oxygen partial pressures (reducing condition at the cathode) causes an increase in oxygen vacancy and titanium interstitials. This defect concentration increase decreases the Schottky barrier at the electrode, via two

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regimes depending on field. In the low field regime, the electrical transport is dominated by local changes near electrodes, and results in macroscopic rectification behavior, with one of the electrodes being forward biased and the other being reverse biased and

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leads to a drop in the resistance when forward biased. However, at higher voltages, the extent of non-stoichiometry is such that it leads to the formation of microstructural

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defects, in this case even a new phase. A significant change in the bulk stoichiometry can lead to the conduction mechanism itself changing in such modified regions, and in this case, it leads to an increase in resistance with time under an applied bias. Building up on this prior work and, based on analysis of complex impedance data

and subsequent equivalent circuit fitting, a detailed model is proposed here for the

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evolution of defects and conductivity in GDC thin films under a wide range of DC electric fields.

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2. Experimental Procedure Gadolinia doped ceria (10 mol.% dopant concentration) thin films were made by magnetron sputtering, using a GDC target made by the conventional powder processing The films were deposited on a Pt/TiO2/SiO2/Si substrate maintained at a

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route.

temperature of 550°C under an atmosphere of highly pure oxygen (99.9992%) with a

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base pressure of 1.2x10-4 mbar and a work pressure of 10-1 mbar. The Pt layer was approximately 200 nm thick and the TiO2/SiO2 layer around 504 nm thick as received (MTI Corporation). The deposition times were varied between 60 to 150 minutes to obtain films with varying thicknesses from 100-500 nm. Based on the deposition times

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and film thicknesses, a sputtering deposition rate of 1 nm/min was estimated. The samples were annealed at 500°C for 2 hours to compl ete crystallization.

Pt top

electrodes ~50 nm thick were deposited using DC sputtering (Kurt J. Lesker Multi-

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Source RF and DC Sputter System) with a shadow mask at room temperature to give a pattern of circular electrodes each with a diameter of ~100 µm. Figure 1 shows a

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schematic of the films, and Figure 2 shows the surface and profile SEM images (SEM FEI Nova 430) of a representative film along with its X-ray diffraction pattern. The average grain size is 54.6 ± 3.4 nm with multiple grains across the thickness of the film. X-ray diffraction (Panalytical X’pert MRD) confirms the formation of the gadolinia doped ceria phase, but also shows some texturing with the (002) orientation missing. The thickness of the thin films was measured using a Tencor AS500 profilometer equipped with a diamond tipped stylus.

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Figure 1. (a) Schematic of a gadolinia doped ceria thin film on top of a Pt/TiO2/SiO2/Si substrate with Pt electrodes on top and, (b) probe contacts adapted from R.

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Kasse [25].

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Figure 2. Scanning electron micrographs of (a) the surface, (b) the edge of a gadolinia doped ceria film. (c) X-ray diffraction pattern of the film compared to 10GDC [26] and platinum [27].

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The thin film samples were electrically tested using an Agilent 4924 precision impedance analyzer and a Micromanipulator Inc. probe station. Heating was achieved using a hotplate, and an infrared thermometer was used to measure the temperature.

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Across plane complex impedance measurements were performed from 25°C to 150°C with an oscillating voltage of 300 mV and an applied DC bias ranging from 0 V to 5 V.

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Open and short circuit compensation were performed to account for the contribution of the test-setup to the measurement. The data obtained was fit to relevant equivalent circuits using Zview software

(Scribner Associates Inc.).

Using the grain and grain boundary resistance values

obtained from fitting, the grain and total conductivity of the samples were calculated using equation (2). The conductivity plotted as a function of temperature follows an

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Arrhenius type equation shown in equation (3) where the slope can be used to calculate activation energy.

(3)

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 E  σT = σ o exp − a   kT 

(2)

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L RA

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σ=

Supporting these measurements, leakage current and current-voltage (I-V) DC measurements were performed using an Agilent 4156C Precision Semiconductor Parameter Analyzer similar to work by Taibl et al.[28]. The probe and heating setup was the same as described above for bulk and thin film samples. Leakage currents for

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the thin films samples were measured for the same bias values and temperatures as used during impedance spectroscopy. The sweep speeds for I-V measurements were varied to match different frequencies in impedance data. The range for the I-V sweep

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was set at twice the oscillation voltage amplitude (mostly set at 300 mV) for impedance

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spectroscopy, with the bias value used lying in the middle of the sweep range. For example, to do a measurement equivalent to a 300 mV oscillating voltage and 2 V bias, the DC I-V sweep would be done from -1.7 V to 2.3 V, with the midpoint lying at 2 V. A pulse sweep measurement mode on the system was used.

To match the sweep

speeds with the frequency of different points on the complex impedance plot, the number of steps in the sweep range, the step size, and the integration time at each point was varied. A change in the integration time essentially modifies the pulse width

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at each of the voltage points. Using the Agilent 4156C system, which has three default integration times, short, medium and long, the short integration time mode was used which allows for the smallest possible integration time of 80 µs. The pulse width on the

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other hand, which is the sum of the pulse width and the hold time after each pulse was set to a minimum value of 5 ms. Such settings allow sweep speeds equivalent to

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frequencies in the range of a ~100 Hz.

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3. Results

Figure 3. Nyquist plot showing impedance data for a 267 nm 10GDC thin film at different temperatures.

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A representative 267 nm thickness 10 mol% GDC thin film is used to illustrate the effects of bias throughout the rest of this paper. As a reference, Figure 3 shows the Nyquist plots for this sample. As the temperature increases, the conductivity of the films

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increases, with the single arc attributed to the grain resistance (R1) becoming smaller and smaller until at about 100ºC a second arc attributed to grain boundary resistance The second arc is

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(R2) becomes visible within the experimental frequency range.

expected to be due to grain boundaries due to the films having a non-columnar grain structure with multiple grain boundaries between the electrodes, unlike that in films with columnar grains. This data can be fit using conventionally used and relatively simple equivalent circuits, where each arc is fit using a parallel combination resistance and a constant phase element (R-CPE), in series [29,30]. The conductivity follows Arrhenius behavior shown in Figure 4, and for a 267 nm thick 10 mol% gadolinia doped ceria film

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has activation energies of 1.34 eV and 0.871 eV with 95% confidence intervals. The activation energy of 0.85 eV and conductivity of 4.3 x 10-5 S/cm at 140ºC are similar to those reported for GDC films by Huang et al. [31] and Joo et al. [32]. The two different

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slopes have been observed before in bulk samples by Esposito et al. [33] and others [34,35]. They have attributed it to factors like change in defect clustering and reduced mobility of the ionic species. However, occurrence of such behavior at temperatures as

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low as 70ºC is very intriguing and needs further study.

Figure 4. Arrhenius plot showing the average grain ionic conductivity for multiple

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electrodes on a 10GDC thin film with 95% confidence bands.

Figure 5. Nyquist plot showing the example of a DC bias effect on a 267 nm thick 10

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mol% GDC film at 120
C. Inset is zoomed in at the origin.

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Figure 5 shows a complex impedance plot for a 10 mol% GDC film at 120
C, with different bias values at intervals of 0.5 V. For the 267 nm thick film considered here, a DC bias value of 3 V translates to a field of 112 kV/cm. This value is helpful for comparison with literature and is not accurate as a majority of the voltage drop is across the electrode interface instead of the entire film, resulting in much higher fields [15]. It is important to note that despite the relatively high effective field, the observed behavior is reversible, that is, there was no dielectric breakdown or related permanent damage

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resulting in the films. The time required for the behavior to stabilize at each bias value is about 30-45 seconds depending on the temperature. Although reversible, a higher time of about 1-1.5 minutes is required for the behavior to revert back to normal after

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removal of the field. Data collected for zero bias before and after the entire data set under bias was measured, did not show any appreciable differences. It was found that with increasing bias, the impedance response for the sample changes.

With an

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increase in bias, the impedance arcs in the Nyquist plot progressively shrink and new features appear progressively. The change is not much at low temperatures, where it

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leads to a reduction in the size of the arc, and a drop in the resistance as has been reported so far [15]. However, it becomes more and more pronounced with a rise in temperature as can be seen from and the effects can be seen at progressively lower bias values.

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To better understand the different stages in which bias affects the sample, even shorter bias intervals were used. Figure 6 shows a plot with detailed effects of bias, and all the involved steps. It is interesting to note that at lower bias values the response

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moves towards higher impedance, and only after a certain point it starts moving towards

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lower impedance values as the applied bias is increased. These can be treated as two different regimes in the impedance response change with bias.

Figure 6. Nyquist plot showing every bias step used for investigating the evolution of the impedance of a 10 mol% gadolinia doped ceria thin film under bias at 130
C.

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4. Discussion Figure 7. Frequency explicit plots showing the magnitude of impedance |Z| and the

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phase angle θ as a function of different DC bias values for a 10 GDC, 267 nm thin film.

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It is prudent to look at the impedance data in the frequency explicit format and in terms of the other immittance formalisms, as they often provide further insight into the

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possible mechanisms at play [36,37]. Figure 7 shows the frequency explicit plots of the magnitude of impedance (|Z|) and phase angle (θ) for Figure 6. There is a big change in the impedance at low frequencies (<104 Hz), where the impedance progressively decreases and then around 2.2 V bias, it starts increasing again, and eventually

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stabilizes around 3 V. It is interesting to note that in the high frequency range, there is no switch in the trend of impedance magnitude with bias; it steadily decreases with increasing bias. Similarly, there is a very large decrease in phase shift with increasing

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bias and it subsequently becomes negative. Such behavior can only be explained by introduction and subsequent increase of an inductive response in the low frequency

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range. This is further bolstered by results from leakage current measurements (not shown here), where at lower bias values, the leakage current decreases from a higher starting value as it stabilizes, indicating classic capacitive behavior. However, for higher applied fields, the leakage current increases from the starting value as it stabilizes, like an inductor would. In either case, it takes about 30-50 seconds for the leakage current to stabilize, which corresponds well with the time for stabilization of the impedance behavior.

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There is also a change in both the real and imaginary parts of impedance, as can be seen in Figure 8. In the low frequency range, the change in the imaginary part is larger than that in the real part, indicating that although both resistive and reactive

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components are changing substantially, the change in the reactive contribution (capacitance or inductance) is higher. On the contrary, in the high frequency range, the behavior is reversed, with the resistive change being more dominant than the reactive

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change, although the change itself is relatively small (enlarged inset).

Figure 8. Frequency explicit plots showing the real and imaginary parts of impedance (Z’ and -Z” respectively) as a function of applied DC bias for a 10GDC 267 nm thin film.

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Figure 9 shows the frequency explicit plots for the real part of permittivity ( ε′ ) with a flip in the trend around 50 kHz (inset).

At high frequencies the capacitive

response of the sample is more dominant, whereas in the low frequency range the

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inductive response is dominant. A similar behavior is seen in the imaginary part of

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admittance as expected (not shown here).

Figure 9. Frequency explicit plot showing the real permittivity for different bias values for a 10GDC 267 nm film. Inset shows the same plot zoomed in to the frequency range of 104-106 Hz.

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The inductive behavior becomes more and more dominant as the bias applied is ε′ increased, which leads to the plots crossing into the negative at lower and lower frequencies, giving us one more evidence of the fact. This information gained from the

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spectroscopic plots and leakage current was used to determine the equivalent circuits for fitting.

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4.1. Equivalent Circuit Fitting

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Figure 10. Nyquist plot showing characteristic steps in the evolution of the impedance response of a 10GDC thin film under increasing bias. Individual plots are labelled A through H and later correlated with equivalent circuits.

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From Figure 6, and based on the data for different films at different temperatures (included in supplementary information), five major steps can be identified in the change of behavior with bias. These steps are characteristic of the response of GDC thin films

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to DC bias and are summarized in Figure 10 for a 10 GDC thin film sample 267 nm thick at 130ºC. Each of these data sets was then fit to equivalent circuits as per the protocol

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in described in prior work [36–39]. The arc ascribed to grain or bulk contribution does not change much with increasing bias. The arc due to grain boundaries first becomes bigger and then shrinks as grain boundary resistance decreases, in progression from (A)-(C). At some intermediate bias values (E), a third new arc appears. This is similar to the effect of temperature (included in supplementary information), where new additional arcs appear at higher and higher temperatures as more relaxation mechanisms come under the experimental range [15]. A pigtail like feature is also

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always observed at the intermediate stage (F). Most interestingly, at higher bias values, the plot enters the third, and even fourth quadrant in some cases as can be seen from plots (G) and (H) respectively.

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Such evolution of behavior has rarely been seen for ceramics, let alone studied. Traditional interpretation of similar data has included inductive elements related to reversible storage of electric kinetic energy. One example is the poisoning of Pt anode

observed below 3 Hz [40].

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in polymer electrolyte fuel cells (PEFCs), where a pseudo-inductive behavior is Another example is that of Faradaic coupled reactions

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dependent on potential and surface coverage, where an inductive loop is observed under high potential [41]. Only the very recent work by Masó and West [15] and the work by Taibl et al. [42] bears a resemblance to the phenomena observed here. Hence, their template for fitting was used as a starting point.

Multiple possible equivalent

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circuits were proposed based on prior knowledge from literature. The circuits were tested for fitting and the most probable circuit was identified from amongst them. The equivalent circuit proposed in this case contains parallel pairs of R and CPE in series

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with each other, for each of the arcs in the complex impedance plots. Additionally, based on the spectroscopic plots, there needs to be an inductance in parallel, with a

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resistance for the branch. The equivalent circuit proposed is depicted in Figure 11. Depending on the shape of the individual plots, elements were added or removed from this circuit.

Figure 11. Proposed equivalent circuit based on visual analysis and the circuits used to fit impedance data shown in Figure 10 along with the respective bias

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values.

As shown in Figure 10, at 0 V bias the complex impedance plot shows two arcs,

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common for such thin films. This data can be fit with an equivalent circuit consisting of two parallel R-CPE pairs in series as shown in Figure 11, and as is commonly done for doped ceria. With increase in bias, the value of R2 first increases and then starts

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decreasing (as can be seen in figure for 0.5 V, 1 V and 1.5 V bias). In addition, a resistance R3 appears parallel to the previous elements. The equivalent circuit is shown

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in Figure 11. At around 1.7 V bias, a third arc appears, barely visible as a curve in the second arc. This arc is further enhanced at 1.9 V. Both data sets can be fit using the equivalent circuit shown in Figure 11. An additional element CPE3 is needed in series here to properly fit the data. This element is possibly due to an electrode effect. With

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further increase in bias, the third arc gets depressed and twists on itself creating a pigtail like shape. At this point, an inductor must be introduced into the circuit to be able to fit the data as shown in Figure 11. With further increase in bias, the pig tail opens up

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and the arc crosses into the third quadrant of the Nyquist plot and then also eventually into the fourth quadrant. The equivalent circuit remains the same although the values of

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the circuit elements do change.

Table 1. The values for equivalent circuit parameters obtained after fitting of the impedance data shown in Figure 10 with all errors being less than 10%.

Element/Bias

0V

1V

1.5 V

1.7 V

1.9 V

2V

2.1 V

2.8 V

R1 (Ω)

35301

36294

32666

33435

36247

31659

30226

12230

CPE1-T

1.7x10

-10

2.1x10

-10

1.3x10

-10

1x10

-10

1.1x10

-10

9.4x10

-11

8.2x10

-11

1.6x10

-10

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0.80

0.83

14

1.3x10

-9

2.6x10

0.85

0.85

0.86

0.87

0.87

14

403840

356740

275010

166380

28632

-8

3.1x10

15

6x10

-9

1x10

R2 (Ω)

1.2x10

CPE2-T

6.8x10

CPE2-P

0.76

0.84

0.72

CPE3-T

--

--

--

7.9x10

CPE3-P

--

--

--

0.86

R3 (Ω)

--

L (H)

--

14

2.5x10

5.8x10

0.63

13

2.1x10

--

--

1.8x10

-8

3.3x10

0.66 -9

11

2.1x10

-8

4x10

0.6 -9

-8

0.58 -10

1.1x10

7.2x10

1.8x10

-9

0.77 -10

1.4x10

-7

1.27

1.54

1.85

3.65

511730

833310

156810

23567

--

523.4

245.2

8.42

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--

-8

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CPE1-P

The values of the different circuit elements obtained using fitting for the various

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characteristic plots shown in Figure 10 are shown in Table 1. With increasing bias, the values of R1, R2, R3, and L show an overall decrease. The value of R1 does not show much change until at very high biases, and even then, the change is very small compared to the changes in R2 and R3. R2 increases slightly at low biases followed by

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an abrupt drop. Around the same bias value as R2, R3 also shows a drastic drop in value. CPE1 (T and P) does not change much. CPE2-T similar to R2 increases at low bias and then decreases at higher values. CPE3-T decreases with increasing bias, and

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then as the plots enter the fourth quadrant, it increases. Traditionally the three arcs as seen for 1.7 V bias, are usually ascribed to grain, grain boundary and electrode effects

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in doped ceria systems [1,43]. With increase in bias, there is a general decrease in the values of circuit elements as would be expected. With increasing bias, the electrode arc collapses first, followed by the grain boundary arc, whereas the arc representing bulk conductivity remains the same although at higher bias values, its corresponding resistance value is considerably lower.

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4.2. Proposed Mechanism Based on the prior work in literature, visual analysis of data, the values of circuit

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elements obtained from fitting with equivalent circuits, and trends therein, a mechanism is proposed. The various phenomena observed are divided into three regimes, based on the three equivalent circuits and the bias values used.

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4.3.1. Low Bias

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At zero bias, the impedance behavior of the films is as expected. The two arcs, small and large, can be attributed to the grain and the grain boundary relaxation respectively. The electrode contribution is not visible in this case as it is beyond the measurable frequency range, as is common with thin films.

As a small bias is applied, the grain boundary resistance increases, with the

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grain resistance being almost constant as shown in Table 1. The small bias leads to the accumulation of positively charged oxygen vacancies at the grain boundaries and the electrode. This exacerbates the already blocking nature of the grain boundaries further

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and leads to a rise in resistance of the grain boundaries as recorded in Table 1. The

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accumulation of vacancies at the cathode due to the bias leads to reducing conditions, which as per the Brouwer defect diagram for doped ceria should lead to a higher concentration of electrons [44]. The small bias causes electrons to move into the sample from the cathode

interface. Grain boundaries being good conductors of electrons, these electrons travel through grain boundaries parallel to the direction of applied field, to the opposite electrode, thus establishing a parallel pathway for electronic conduction.

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4.3.2. Medium Bias Platinum forms a Schottky barrier with rare earth doped ceria. As the applied

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bias is increased further, and platinum being a blocking electrode for oxygen vacancies, more and more vacancies segregate at the cathode. At the same time, more and more electrons accumulate at the interface from the side of the electrode. With increasing With

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field, an increasing number of electrons can now jump across the barrier.

increasing bias, the current along grain boundaries increases and correspondingly, the

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value of the resistance R3 decreases. With the electrons moving across the electrodes in the voltage range, the electrode interface becomes visible in the impedance response within the measured frequency range. This is represented by the new CPE addition in the equivalent circuit, which decreases with increasing bias in the medium range. Thus, there are three arcs instead of two from the previous regime. As the bias is further

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increased, the arcs tend to become smaller. This indicates that the grain boundaries and electrode interface become more and more conductive. They also tend to become more circular and bend towards the real axis, indicating a change from capacitive

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towards resistive behavior, caused due to conduction of electrons.

Figure 12. Schematic band diagrams showing the cathode and anode interface under bias.

The process happening at the electrodes can be better understood from the schematic band diagram of the electrode interfaces under bias shown in Figure 12.

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With increasing bias, the barrier height at the cathode is reduced and more electronic charge is injection from the Pt electrode into GDC, whereas at the anode, the electrons

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injected at the cathode easily flow back into the Pt electrode and the external circuit. 4.3.3. High Bias

At further higher bias values, above 2 V, electronic charge injection across the

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electrodes and conduction through the parallel grain boundaries becomes more pronounced, leading to the collapse of first the electrode arc followed by the grain

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boundary arc. The material starts exhibiting inductive behavior. This results in the arc twisting up on itself although it stays in the first quadrant. With increasing bias, the electrode and subsequently grain boundary arc moves into the fourth quadrant. The inductive loops can be explained by following the line of reasoning used by Taibl et al.

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[42] who have shown similar behavior in Fe-doped SrTiO3 thin films, and have supported the vacancy migration theory and stoichiometry variations under bias using characteristic inductive loops in the impedance spectra. The existence of inductive

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loops was explained on the basis of the time required for oxygen vacancies to redistribute after a voltage change, and hence they were attributed to ion motion across

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the width of the film. The model proposed requires the assumption that the electronic current is much higher than the ionic current, which mostly holds true in this case. With increasing bias, despite the low contribution of ions to conduction, due to ion flux the vacancy segregation becomes even more concentrated at the cathode after a steady state is achieved. The AC voltage stimulus causes these vacancies to redistribute. However, their response depends on their mobility. At high frequencies, there is almost no change in the distribution, as the vacancies cannot oscillate with the AC voltage. At

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lower frequencies however, there is enough time for the redistribution of oxygen vacancies within a half cycle of the sinusoidal voltage signal. Thus, every half cycle, as long as the ions can respond, a new vacancy distribution is formed. This migration of

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ions is in series to the electronic current and causes a negative phase shift, thus showing up as an inductive loop [42]. With increasing bias, there is even more vacancy accumulation, which accentuates the inductive loops. Throughout the different bias

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regimes, the arc representing grain contribution does not change much, except at very high bias values where it starts shrinking. It is only under very high biases, that the

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grain interior is also reduced, such that electronic conduction takes place. Additionally, to verify the reasoning for the inductive loops, DC I-V measurements were performed at various sweep speeds. This measurement was based on the work by Taibl et al. to explain the change in vacancy distribution on the length scale of the

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sample [42]. The sweep speeds were varied to match the frequencies of the points where the complex impedance plot crosses the real axis. It was found that when the sweep speed matches the frequency of the point at which the complex impedance

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intersects the real axis, the resistance obtained from the slope of the I-V plot matches the value obtained for electronic resistance (R3) obtained from equivalent circuit fitting

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of the data. The corresponding data are shown in supplementary information.

5. Conclusions

It was found that the application of a DC bias leads to an increase in the

conductivity of GDC thin films. Owing to the use of thin film samples, the electric field values afforded here were much higher than any previous studies. Careful analysis of the evolution in the features of complex impedance behavior with increasing bias

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reveals that the increase of conductivity is due to increased electronic conductivity when under bias. Equivalent circuit fitting shows that the application of a bias causes first, an increase in grain boundary resistance attributed to vacancy segregation, and then, the

at higher fields, eventually showing inductive behavior.

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opening of a parallel path for conduction of electrons, which becomes more pronounced First the grain boundaries

become electronically conductive followed by the grains. Both bias and temperature

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affect this phenomenon, with the effect of bias becoming more pronounced at higher temperatures. This behavior has been found to be reversible and independent of the

as reversible mixed ionic conductors.

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6. Acknowledgement

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polarity of the applied field and is significant for application of doped ceria compounds

This work was supported by the National Science Foundation under Grant No. DMR1207293. The authors would also like to thank Hiraku Maruyama for his assistance

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with the SEM and XRD measurements.

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