Effect of energy management circuitry on optimum energy harvesting source configuration for small form-factor autonomous sensing applications

Accepted Manuscript

Effect of Energy Management Circuitry on Optimum Energy Harvesting Source Configuration for Small Form-Factor Autonomous Sensing Applications D. Newell , R. Twohig , M. Duffy PII: DOI: Reference:

S2452-414X(16)30096-6 10.1016/j.jii.2017.04.002 JII 33

To appear in:

Journal of Industrial Information Integration

Received date: Revised date: Accepted date:

4 November 2016 14 March 2017 12 April 2017

Please cite this article as: D. Newell , R. Twohig , M. Duffy , Effect of Energy Management Circuitry on Optimum Energy Harvesting Source Configuration for Small Form-Factor Autonomous Sensing Applications, Journal of Industrial Information Integration (2017), doi: 10.1016/j.jii.2017.04.002

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Effect of Energy Management Circuitry on Optimum Energy Harvesting Source Configuration for Small Form-Factor Autonomous Sensing Applications D. Newella,*, R. Twohigb, M. Duffya a

Power Electronics Research Centre (PERC), Eletrical & Electronic Engineering, NUIG, Galway, Ireland. SolarPrint Ltd., Dublin, Ireland.

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Email: [email protected] and [email protected] Phone: +353 91 493270 Fax: +353 91 494511

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Abstract-- The purpose of this paper is to investigate methods for improving power delivery from low-voltage, lowpower energy harvesting sources, such as small form-factor dye-sensitised solar cells (DSSCs) as used in autonomous wireless sensing applications in buildings and homes. Energy harvesting powered wireless sensors enable existing and new structures to comply with Industry 4.0 and become smart buildings. Due to the size constraints of wireless sensor systems and the inherently low-power levels generated by energy harvesting sources, available power is limited and therefore the efficiency of power conversion and energy management circuitry connected between the source and output load has a significant impact on output power delivery. Most research to date focuses on improving the efficiency of individual components of such systems, without considering the impact of one stage on the others. In this paper, the potential of varying energy harvesting source configuration in combination with power converter operation to improve overall power delivery is investigated, where it is shown that by connecting sections of a DSSC in series rather than as a single cell, higher power conversion efficiency and therefore power delivery is achieved. Limitations to varying cell configurations and low-power DC-DC topologies are illustrated in order to demonstrate the scope of solutions available for small-sized, low-power, energy harvesting sources. It is shown that 8% improvement in overall power delivery is achieved for series vs. single cell connections within a fixed module area. This will translate into increased wireless sensor functionality and range, thereby furthering the development of the Industrial Internet of Things in buildings and homes.

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Index Terms— Dye-sensitised solar cells (DSSC), energy harvesting, ultra-low power conversion, boost converter.

1. INTRODUCTION

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In partnership with the Industrial Internet of Things and Industry 4.0, wireless sensors provide an essential solution to the development of automated buildings and homes towards becoming autonomous and smart. In the case of smart homes, wireless sensors can be utilised for a wide range of applications aimed at improving occupant comfort such as remotely or autonomously operated temperature control, household appliances, security systems, etc., while also facilitating increased building energy efficiency [1]. Similarly, wireless sensors can be used in industrial building settings to enable autonomous control of important operating conditions such as temperature, CO2 and humidity, or to optimise overall building efficiency. However, the main issue with wireless sensors in autonomous buildings and homes is the need for a separate and reliable power source for each of the individual sensors, where for example a machine diagnostic application may require up to 300 sensor nodes over an industrial production area of 25 m2 [2]. Energy harvesting powered sensors have the ability to be fitted and operate autonomously in a wide range of locations without the need for access to mains power or battery maintenance, which means that autonomous building

ACCEPTED MANUSCRIPT management systems (BMS) can be retro-fitted to existing buildings in both industrial and domestic settings. This allows smart homes and factories to be created with relative ease and minimal maintenance when compared with battery and AC mains powered solutions.

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These advantages of maintenance-free operation and long lifetime provided by energy harvesting sources in enabling autonomous sensor applications such as required in building automation (commercial and residential) are well recognised [3]. However, due to restrictions on the physical size and therefore output power levels of energy harvesting sources, there are limitations to the range of sensor functionalities and data rates that can be supported [2]. Part of the issue is that developments in each of the individual components of an energy harvesting system require different specialist expertise: material science for energy harvesting sources and sensor devices; power electronics for energy management; and embedded systems and wireless communications for lowpower wireless sensor operation. Therefore, while significant progress has been made on improving the efficiency of individual energy harvesting system blocks, e.g. [4], little focus has been directed on synergies to be achieved in optimising the performance of several combined blocks. In this work, the potential for maximising output power from an energy management circuit connected to different configurations of an energy harvesting source is investigated, where it is shown that over 8% higher power is achieved by considering the source and energy management blocks together rather than as individual components [5]. In addition, limitations in system performance are identified that help direct future developments in energy harvesting source and power conversion blocks.

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For building and home environments, dye-sensitised solar cells (DSSC’s), [6], provide a very sustainable solution to a wide range of BMS sensors due to the ready availability of light being delivered from artificial lighting as well as ambient sunlight. DSSC’s are considered as the energy harvesting source in this work, where they have evolved to the point that they can compete comfortably with more established photovoltaic technologies, particularly under indoor lighting conditions [7], [8]. As with many small form factor energy harvesters, DC-DC conversion is required to increase the source voltage to a standard value used in analogue and digital sensor interface circuitry; e.g. 3 V, 5 V. However, a significant limitation to efficient DC-DC conversion is the very low source voltage levels of energy harvesting sources that result in high voltage step-up ratios. For example, with a single-cell DSSC module having an active area of 21 cm2 and 0.4 V output, 77% power conversion efficiency was achieved in stepping the voltage up to 3.3 V using a commercial boost converter [9]. In a bid to increase this efficiency and therefore output power delivery, the impact of changing DSSC configuration so as to increase output voltage is investigated, in combination with associated improvements in DC-DC converter performance. Equivalent circuit models that account for DSSC configuration are combined with detailed loss models of a DC-DC converter under low-power energy management modes, to identify optimum combinations for different small form-factor DSSC module sizes. In this way, the potential for maximising energy delivery from DSSCs to support autonomous sensor operation is demonstrated, where the increased power can be applied to enable increased accuracy of the sensor data or increased frequency of the data being transmitted, both which will enhance the performance of applications such as BMSs. The structure of the paper is as follows: Section 2 discusses materials and methods, where the energy harvesting source featured in this work is a small form-factor DSSC developed by SolarPrint for wireless sensor applications [10]. A commercial DC-DC converter that implements state-of-art energy management functions for low-voltage, low-power sources is applied to increase the DSSC

ACCEPTED MANUSCRIPT generated voltage to that required by wireless sensors. Section 3 details methods to vary the DSSC electrical (voltage-current) characteristics through reconfiguring of its structure, and presents models for predicting DC-DC converter losses as a function of DSSC voltage and current levels under low-power energy management modes. A trade-off between reduced active DSSC area and increased power conversion efficiency is found, and an optimum configuration for different DSSC module areas is identified. Section 0 presents efficiency measurements performed for a range of cell sizes and lux levels, which verify model predictions, and discusses the impact of the results.

2. METHODS & MATERIALS Dye-Sensitised Solar Cells

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2.1.1 DSSC Structure

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As with many small form-factor energy harvesting sources (e.g. photovoltaic, thermoelectric, microbial fuel cells), DSSC generated voltages are limited to relatively low values of approximately 0.5 V open-circuit per cell. Therefore, there is a need to increase the voltage to standard values used in analogue and digital sensor interface circuitry, e.g. 3 V, 5 V. For large area sources, individual cells may be connected together in series to provide a workable voltage [11]. However in applications where space is limited (as in wireless sensor loads), normally one standard cell–size is applied and therefore additional step-up power conversion circuitry is needed to increase the generated voltage [12], [13]. When compared with similarly sized silicon PV cells, it is found that the main problem in producing series connected DSSC elements is the low resolution of processes for producing interconnects which results in a significant reduction in active area; typical cell-cell spacing widths are 0.6 - 2 mm for DSSC’s [14], [15] while micron scale separations are possible with silicon PV [16]. Developments in manufacturing processes for DSSC interconnects are on-going, [17], including those targeting optimisation of cell size for maximum module efficiency [18]. However, within the space available for wireless sensor applications, the scope to optimise cell geometry is limited, and therefore voltage step-up power conversion circuitry is generally required. Module sizes ranging from 10 – 100 cm2 are considered in this paper, corresponding to power levels of 0.14 – 1.94 mW under indoor lighting levels of up to 700 lux.

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DSSC’s have a relatively simple and quick manufacturing process by comparison with silicon based photovoltaic (PV) cells. Whereas silicon based cells require a layer of crystalline silicon which can be expensive and time consuming to produce, DSSC’s are produced using readily available materials in a low cost printable process [6]. Figure 1 (a) shows completed cells with active areas of 21, 12 and 6.7 cm2 respectively, (b) shows the DSSC equivalent circuit model and (c) shows a cross sectional view of the DSSC makeup. WE TCO Porous TiO2 Compact Layer S e a l a n t

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Figure 1: (a) Completed DSSCs, (b) DSSC equivalent circuit model and (c) schematic DSSC cross sectional view.

2.1.2 DSSC Electrical Characteristics

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The working (WE) and counter electrodes (CE) are glass panels each with a layer of transparent conducting oxide (TCO, labelled 1 in Figure 1 (c)) applied to one side of the glass. This material is transparent, while also being electrically conductive which is imperative for solar cell electrodes. A thin layer of titanium dioxide (TiO2, labelled 2) is applied to the TCO on the WE. A mesoporous layer of titanium dioxide (TiO2, labelled 3), which interacts with the electrolyte, is also applied. A dye is applied to this TiO2 layer which gives the cell active area its hue, as seen in Figure 1 (a). The dye allows absorption of the light spectrum, so by changing the dye colour different parts of the light spectrum can be absorbed. This allows DSSCs to be optimised for different lighting conditions. The DSSCs used in this work are optimised to have a high performance under fluorescent light sources in an indoor environment. For the CE a thin layer of platinum (labelled 4) is applied to act as a catalyst and to allow the electrons to flow between the CE and the electrolyte. The next step is to apply electrolyte (labelled 5) to complete the internal circuit by allowing the electrons to flow from the CE back to their original state. The cell is then completed by adding a sealant layer around the electrolyte.

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The equivalent circuit model of a DSSC shown in Figure 1 (b) may be related to its structure (Figure 1 (c)) by examining the flow of electrons through the circuit. After exposure, electrons are mobilised from the dyed TiO2 and are available to conduct current through a load connected to the cell, where they encounter the following impedances:  From the dye to the TiO2: represented by D in parallel with C2 in the equivalent circuit model.  From the TiO2 to the working electrode TCO layer: zero impedance assumed.  From the working electrode through the load resistance, Rload, to the counter electrode: electrode sheet resistance is represented by Rh for each electrode.  From the counter electrode to the electrolyte: represented by R2 in parallel with C2. R2 represents the resistance between the electrolyte and the CE, which is inversely proportional to the electrolyte-electrode interface area.  Finally from the electrolyte back to the original state in the dye: represented by R3 in parallel with C3. R3 represents the resistance of the path provided through the electrolyte and is therefore proportional to the electrolyte layer thickness, while being inversely proportional to the active cell area. The impact of internal resistances in different cell configurations is discussed further in Section 3.3. An additional shunt resistor, Rshunt, is shown in Figure 1 (b) which represents the open-circuit resistance of the system. If this value is low, it represents a possible short-circuit which allows electrons to flow directly between the CE and WE. In a fully functional cell, the shunt resistance is substantially higher than the other cell resistances and can usually be neglected. The model seen in Figure 1 (b) aligns well with other DSSC equivalent circuits proposed in [19], [20] and [21]. Clearly, DSSC output power depends on the value of load resistance, Rload, relative to the internal cell impedances. Under steady state conditions, capacitances C1 and C2 can be neglected and power generated depends more sepcifically on internal cell resistances. Some methods to reduce internal resistance have been investigated [21], [23], but the issue of low cell voltage in comparison to the required load voltage still limits performance. Practically the effect of internal cell resistance can be best seen from the plots of current versus voltage under varying light conditions. Measurement

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results of the IV curve for a cell with an active area of 22 cm2 across a lux range can be seen in Figure 2, where the lighting level was controlled by varying a compact fluorescent light bulb. It can be seen that the maximum power point (MPP) for the module is approximately 0.225 mW at a voltage of 0.4 V for a 700 lux input. It should be noted that 700 lux is slightly higher than indoor office lighting with no external sunlight, but with the effects of ambient sunlight included, it may be taken as a good approximation to the average value in an office environment.

Figure 2: DSSC IV and PV curves for different lux for a DSSC with an active area of approximately 22 cm2.

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It is seen that the MPP voltage remains close to 0.4 V regardless of the input lux level. Due to this limited value, some form of DC-DC conversion is required to increase the voltage to a higher, useable level. Many wireless sensors operate at 3.3 V, but if the device will be operating during light restricted times (e.g. overnight), an energy storage element, e.g. a lithium based battery, will also be required. This will generally require a voltage higher than 3.3 V to charge. In this work an output load voltage of up to 4.1 V has been selected as suitable to charge a lithium based battery, which corresponds to a voltage step-up ratio of up to 10 for the single-cell DSSC being investigated.

DC-DC Converters for Energy Harvesting Sources

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There are many possible low power DC-DC converter topologies that could be utilised to increase the output voltage of a DSSC source, 0.4 V, to a more usable 3.3 V, although a significant limitation to their efficiency is the low-voltage generated. Available circuit topologies that provide a voltage step-up function for low-voltage, low-power energy harvesting sources, include switched capacitor circuits [24], inductor based boost converters [25], and others which have been developed specifically for microbial fuel cells (MFC) [26], piezoelectric (PZ) generators [27] and human powered harvesters [28]. A significant limitation to efficient power conversion is low source voltage levels that result in high voltage step-up ratios. For example, with a single-cell DSSC module having an active area of 21 cm2 and 0.4 V output, 77% power conversion efficiency was achieved in stepping the voltage up to 3.3 V using a commercial boost converter [9], with a further improvement of up to 85% reported with two series connected cells having approximately the same module area and 0.8 V output [5]. Table 1: Commercially available low-voltage, low-power DC-DC converters.

Circuit

Topology

Start-up Voltage (V)

Vout (V)

Efficiency for DSSC input (%)

Texas Instruments BQ-25504 [9]

Unregulated boost startup, inductor based switching converter

0.13 - 3

1.8 – 5.5

76 - 82

Linear Technology LTC-3108 [29]

Coupled inductor based switching converter

0.02 - 0.5

2.5, 3, 3.7, 4.5

22

Seiko S-882Z [30]

Charge pump

0.2 – 0.5

1.8, 2, 2.2, 2.4

20 (Peak)

ACCEPTED MANUSCRIPT Suitable topologies for this work include transformer [31], switched capacitor [24], and a boost converter [25] whose efficiencies range from 40% for the transformer based converter to 65% for the switched capacitor and the highest of 77% being delivered by the boost converter. Table 1Error! Reference source not found. compares different commercially available implementations of the above topologies in terms of steady-state efficiency for a single-cell DSSC source and a 3.3 V load. Similar to the literature it is clear that the most efficient solution is the inductor based switching converter, which includes an unregulated boost start-up stage to overcome the low-voltage.

2.2.1 Low-voltage, Low-power Boost Converter Operation

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A typical boost converter circuit schematic is shown in Error! Reference source not found.. It is a switching converter in which the NMOS and PMOS (n-channel and p-channel Metal-Oxide Semiconductor, respectively) devices are switched alternately; when the NMOS is on (and PMOS off), energy is stored in the inductor, L, and this energy is then released to the output when the PMOS is on (and NMOS off). By maintaining an equal rate of current ripple during each of the switching intervals, a voltage boosting function is achieved with the relationship between input and output voltages, Vin and Vout respectively, given as: ( ) (1) where D is the duty cycle of the NMOS switch. L

PMOS

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Figure 3: Boost converter topology.

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When compared with higher power applications where DC-DC converters are operated on a more or less continual basis with pulsed width modulation (PWM) applied to control voltage/current levels, DC-DC converters in low power energy harvesting applications are more often operated under burst mode with pulsed frequency modulation (PFM) control [32], [33]. Under burst mode, a converter similar to that of Figure 3 is enabled periodically in short pulses of time, while it remains disabled for the remaining time. In this way, active boost converter losses, i.e. inductor and MOSFET conduction losses and MOSFET switching losses, associated with the converter operation are reduced. For the case of a DSSC source, input voltage control may be applied to control the time for which the converter is enabled in order to maintain operation around the maximum power point of the DSSC; i.e. operation is enabled once the voltage on the input capacitor, Cin, is charged to a certain percentage above the maximum power point (MPP) voltage, VMPP+, and the DSSC power is then provided through the converter to a load device. The converter becomes disabled after the voltage reduces to a defined percentage below the MPP voltage, VMPP-, so that energy from the DSSC source can be applied to recharge Cin, and this cycle repeats [34]. A representative waveform of the voltage on Cin during such operation is shown in Figure 4 (a) for illustration.

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Figure 4: (a) Input capacitor and (b) circuit operating waveforms.

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When enabled, further loss reduction of the boost converter may be achieved by applying PFM instead of PWM control, because PFM operating frequencies and therefore switching losses are generally lower as they become dominant over conduction losses at low power levels. Finally, whether operating in PFM or PWM, the converter can be designed to operate in discontinuous conduction mode (DCM), where the inductor reduces to zero in every cycle to eliminate either turnon or turn-off switching losses. This is shown in the detailed circuit waveforms for a boost converter operating under burst mode with PFM control and DCM in Figure 4 (b). During the boost operating time, current mode control may be applied to set the on-duration of the NMOS switch, while its off duration is set equal to the discharge time of the inductor current.

3. SYSTEM MODELLING

DSSC Model

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Models for predicting the combined performance of a DSSC connected in series with a DC-DC boost converter under different operating conditions are described in this section, where the DSSC model accounts for the variable voltage-current characteristic provided by different numbers of series connected DSSC elements. Loss models for the DC-DC converter account for discontinuous and pulsed mode operation, as implemented in energy management schemes for low-power applications. The models are then combined and applied to determine optimum DSSC configurations that provide maximum output power for different sized modules. It is shown that the optimum number of series connected cells varies with module area, with over 15% improvement in power conversion efficiency and 8% improvement in output power delivery achieved for the largest area of 100 cm2.

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The output voltage and current levels of a DSSC source can be manipulated by splitting the available area into smaller cell sections and connecting them together in series. Figure 5Error! Reference source not found. shows how a single cell area is best divided into multiple smaller strip cells within the same physical area, where the strips have a width equal to the original single-cell width. Stripped designs are applied because they reduce the resistance to electron transport of each individual cell to the counter electrode, R2, when excited by the light source, as discussed in [13].

Sealant Layer 0.1615 cm

Active Area

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Figure 5: Physical area, light blue, versus active area, red, for DSSC.

ACCEPTED MANUSCRIPT However, as shown in Figure 5Error! Reference source not found., a sealant layer is required between each cell to separate the cells, and because of this the overall active, power-generating area of the module is reduced. Therefore, while the DSSC source voltage and resulting power conversion efficiency is increased, the extent to which power generated is reduced must be considered in order to determine the optimum number of cells to ensure that the combined performance of the module and power conversion circuitry isn’t compromised by the increased number of cells.

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It should also be noted that while a series connection provides an increased output voltage, as the area is divided into smaller cells, the resistance values in the equivalent circuit model of Figure 1 (b) are altered. Resistances R1 and R3 for each strip increase due to the decreased active area. Therefore, for example in Figure 5 Error! Reference source not found.(d), with 9 cells in a series connection, the resistance per strip will be approximately 9 times the resistance of a single large strip as shown in Figure 5 Error! Reference source not found.(a). The total resistance will then be increased by a factor of approximately 81 due to the series connection of 9 strips. However, this increased resistance does not limit the overall power produced; as shown in the measurement results of Figure 6Error! Reference source not found. with two series connected cells, the output voltage is doubled while the output current is halved to provide the same overall output power. These measurements were taken at 700 lux for two DSSC modules, each with an active area of 12 cm2 when connected in series and then in parallel to represent one large cell with an overall active area of 24 cm2. The difference is seen in terms of DSSC matching load resistance at which the maximum power is achieved; i.e. a factor of approximately four in this case with 250 Ω found for the two parallel cells vs. 1.15 kΩ for two series connected cells.

Figure 6: Series and parallel IV curve for 2 DSSCs with an overall active area of 22 cm2.

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In order to connect multiple cells in series within a fixed module area, part of the module area needs to be allocated to sealant and interconnect regions between cells. Two common methods are used: Z–type and W-type connections [15]-[18] where the Z-type is manufactured using much the same processing flow as described for a single cell in Section II, except that it requires a conductive connection to be made from the CE of one cell to the WE of the following cell. The need for this conductive material, e.g. silver [15], requires a slightly larger sealant area to allow the TCO layers on the neighbouring WE and CE to overlap. The main benefit of the W-type connection is that cell series connections can be made directly on the TCO layers. However, this is offset by increased manufacturing complexity, where the order of applied material layers is inverted for each alternate cell. Furthermore the inverted cells are required to be slightly larger than the non-inverted cells to compensate for absorption of some of the light striking the inverted cells by the CE and electrolyte

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prior to reaching the dye-sensitised material [18]. If all cells were the same size, the inverted cells would limit the current output of the module. For the purposes of simplicity, a Z-type connection is assumed for producing series connected cells in this work. Figure 7Error! Reference source not found. shows calculated values of MPP voltage and output power for a 25 cm2 DSSC module area versus number of series connected cells. These results are based on measurements of current and voltage taken for several different sized DSSCs investigated in this work, where similar to the work outlined in [35], the power per active area value was found to be approximately constant at 22 µW/cm2 active area. Using this power density the voltage and power values were calculated for a varying number of cells connected in series within a module area of 25 cm2 according to Figure 5Error! Reference source not found.. An interconnect width of 1.615 mm was assumed between individual cells and 0.6 cm was selected as the border of the module on each side. Up to 7 series connected cells are considered in this case, because beyond this the input DSSC voltage would be approximately the same as the required output voltage of 3.3 V and therefore no DC/DC boost converter would be needed.

Figure 7: DSSC voltage and maximum output power vs. number of cells for a 25 cm2 module area for 700 lux.

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As expected, the voltage increases linearly with increasing number of cells, however the power reduces due to the loss in active area needed for interconnects when more than 1-cell is featured. Within the relatively small module area of 25 cm2 considered, it is found that the power generated reduces by 3.7% with every cell division. The extent to which this decrease in generated power offsets the increase in power conversion efficiency is investigated for different module areas in Section 3.3.

DC-DC Converter Loss Modelling & Analysis

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To better understand limitations to the efficiency of energy management solutions for low-voltage, low-power sources, a detailed investigation of energy conversion losses is presented for a 25 cm2 DSSC source operated under typical conditions when configured for an increasing number of series connections. Energy conversion losses include conduction losses in the inductor and semiconductor switches, semiconductor switching losses, gate-drive losses along with biasing and operational losses in controller circuitry [36]. As described above, the boost converter and its load are disabled while the input capacitor, Cin, is charged by the DSSC source. During this time, the main source of losses is the capacitor ESR (Equivalent Series Resistance). When the voltage reaches a pre-set value above the MPP voltage, VMPP+, the capacitor stops charging and starts discharging into the load through the boost converter as it becomes enabled. The time taken to charge the capacitor is defined by:

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(2)

where IDSSC is the DSSC source current. Once the boost converter is turned on, Cin continues to discharge until a predetermined minimum value, VMPP-, is reached. These pre-set values are chosen to ensure the input voltage stays around the MPP of the energy harvesting source. As shown, due to the low level of current available from the DSSC relative to the current supplied to the load, the capacitor charging time is usually much longer than its discharging time.

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The majority of circuit losses are incurred during the boost converter on-time when Cin discharges to the load. Error! Reference source not found.(b) shows the waveforms of key parameters of the boost converter under current mode control (CMC) [34] during this time. The inductor charges to a pre-set peak current value, Ipeak, after which the NMOS turns off and the inductor then discharges to zero to supply the load through the high-side PMOS switch. This cycle repeats until the input boost capacitor voltage reduces to the lower threshold, VMPP-, as described above, with the ratio of voltages at the input and output of the converter determining the duty cycle of the MOS switches, D (1). The time for which the boost converter operates may be estimated from the average capacitor discharge current, Ipeak/2, as: (3)

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Note that due to the low power available from the DSSC source, an energy storage component such as a capacitor or battery is usually used at the output of the boost circuit to supply a continuous low level power to the load when the boost converter is disabled. Under standard boost converter operation, conduction losses in the inductor and MOSFETs may be calculated as: (4) (

(5)

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respectively, where expressions for RMS (Root Mean Square) currents in all components account for the discontinuous nature of current waveforms under burst mode, PFM operation. Noting ON conduction times for the NMOS and PMOS switches as:

respectively, the frequency of the inductor current as shown in Error! Reference source not found. (b) can be calculated as:

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Combining this frequency with the peak current amplitude, Ipeak, standard expressions for the RMS of a triangular waveform can be applied to calculate power losses in the inductor when the boost converter is operating [37]. Similarly, expressions for MOSFET ON times in (6) and (7) can be applied to calculate RMS currents for each sawtooth current waveforms flowing in the NMOS and PMOS. For all components, in order to account for burst mode operation of the boost converter, RMS currents calculated for continuous converter operation need to be scaled by the factor, √

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Clearly, for a fixed peak current, Ipeak, the value of Dboost and therefore all conduction losses decrease with decreasing DSSC source current.

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where FSW is the switching frequency as given by (8), and tsw,on and tsw,off are the MOSFET turn-on and turn-off times respectively. In this case, both values of tsw,on and tsw,off were assumed as 1% [38] and 5% [39] of the maximum switching period of 1 MHz for the low-side and high-side respectively. Note that (10) includes both turn-on and turn-off losses, and it applies to each of the NMOS and PMOS devices as they take over conduction of the inductor current during switching transitions. As discussed above, DCM can be utilised to reduce switching losses by allowing the inductor current to fully discharge before switching. This means that losses in switching-on of the NMOS and switchingoff of the PMOS are both negligible. Interestingly, on substituting for FSW from (8) for discontinuous operation, it is found that Psw becomes independent of Ipeak, but depends more on the ratio of Vin and Vout. Again, to account for the discontinuous nature of the boost operation, Psw must be scaled by Dboost (9), with lower losses predicted for lower DSSC current, IDSSC.

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Finally, losses associated with the controller circuitry also need to be accounted for. In addition to comparator and voltage/current reference circuit losses, these include MOSFET output capacitor charging and gate drive losses, given respectively as: ) )

(11) (12)

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where values for the MOSFET output capacitance, Coss, and gate charge, Qg, were taken from the datasheets [38], [39]. To reduce losses encountered by the system for gate driving, Pg, generally there is some form of gate charge recovery; e.g. [40], [41]. For the case of this work, losses were predicted as being 15% of conventional gate driver losses, similar to loss levels reported in [42].

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The breakdown in losses encountered by the converter for different cell configurations within a fixed module area of 25 cm2 is compared in Figure 8 for a range of DSSC voltage and current values corresponding to 1 to 7 series cell connections (corresponding to a DSSC module voltage of up to 2.8 V). It is seen that predominant losses are related to switching losses and MOSFET conduction, and there is an obvious reduction in total losses when the input voltage/cell numbers to the boost circuit are increased. It is found that the most significant effect is a reduction in conduction losses in the MOSFETs and inductor. This is explained by a reduction of input DSSC current, IDSSC, and therefore Dboost (9) as the corresponding input capacitor charging time, Tcharge is increased (2). The MOSFET switching losses are also reduced but not at the same rate as conduction losses; this is due to the offset in a Dboost reduction with an increase in FSW as given by (6) – (8).

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Switching Losses Pcoss Inductor Conduction

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MOSFET Conduction Pg Efficiency

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Losses (µW)

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Efficiency (%)

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Figure 8: Boost converter loss breakdown and efficiency vs. series connected cells for a 25 cm2 DSSC module area.

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Clearly, there are significant gains in efficiency achievable by implementing series connected DSSCs, with over 15% improvement predicted for seven series connected cells over one larger cell fitted within the same module area. The overall improvement in output power delivery for the same module area is investigated in Section 3.3 where the results of Figure 8 are combined with results of DSSC generated power presented in Figure 7, as is the performance of other DSSC module sizes with series connected cells.

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As examined above, by increasing the number of multiple series connected DSSCs in a single module the power conversion losses can be reduced. However, Figure 7Error! Reference source not found. shows that by increasing the number of cells the VMPP voltage increases but due to the additional sealant layers reducing the active area, the DSSC generated power is reduced. This reduction in power must be factored with the boost converter efficiency to understand how the overall delivered power to the load will be affected and to determine an optimum combination of DSSC configuration and DC/DC converter for a given module size.

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In order to investigate these effects for a range of DSSC module sizes that would be compatible with wireless sensor load applications, results of DSSC generated power (per module area) and power converter energy efficiency are plotted in Figure 9 for an increasing number of series connected cells. As observed for a 25 cm2 module earlier, it is clear to see that the general trends are a decrease in generated power per unit area and an increase in boost converter efficiency with increasing in series connected cells. Due to a higher percentage reduction in active area, the rate of decrease in generated power with increasing series connections is higher for smaller modules, while lower DSSC current impacts on power conversion efficiency achieved with smaller modules.

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Figure 9: (a) DSSC generated power per module area and (b) DC-DC converter efficiency vs. number of cells for different DSSC module areas.

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The combination of input DSSC power and DC/DC converter efficiency to predict output power delivery per module area for the same range of module designs is shown in Figure 10, with maximum power delivery values circled for each module area.

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It is interesting to see that despite the increasing trend of the converter efficiency, due to the loss in DSSC active area, delivered power does not always increase with number of series connected cells. Therefore there are different optimum designs for each module area. Below 50 cm2 there are quite definitive peak power points at 2 series connected cells for 10 and 25 cm 2, where the reduction in active area is more significant. Above this area the effect of increasing DC/DC converter efficiency is extended to a higher number of series connected cells to produce optimum designs at 3, 4 and 5cells for 50, 75 and 100 cm2 modules respectively. Nonetheless, there are significant gains in overall power delivery achieved by replacing one large cell area with multiple series connected cells for all module sizes, with up to 8% improvement achieved with the largest area considered. Clearly, this would translate directly into longer operating times or increased functionality of wireless sensor load devices. The steps taken to optimise output power delivery at a given voltage level from a DSSC source are summarised in Figure 11, where equations are generalised to enable their application for other ranges of source voltage and power levels (at the maximum power point), other circuit operating conditions and other load power profiles. In this way, this approach can be utilised for a wide range of energy harvesting sources, e.g. solar cells, thermoelectric and microbial fuel cells and power conversion topologies, to obtain the optimum system level solution to achieve maximum power delivery. Specifications - Maximised - VOUT (e.g. 3.3 V wireless sensor) Source Parameters

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Figure 11: Design procedure for optimised energy harvesting source.

4. RESULTS & DISCUSSION In order to verify the scale of improvement predicted for series connected cells, measurements of overall system efficiency and output power were performed on different combinations of available DSSC modules feeding into a boost converter [9]. The tests were performed using a light box with a

ACCEPTED MANUSCRIPT variable source connected to a compact fluorescent light bulb and a lux meter. The converter was connected to an equivalent resistive load which acted like a storage element at a fixed voltage. Results were produced for two voltages: 3.3 and 4.1 V to cover both scenarios of the converter powering the load or battery, respectively. Three different DSSC modules were available: module A with active area of 5.5 cm2, module B, active area of 12 cm2, and module C, active area of 21.8 cm2, as seen in Figure 1 (a). The modules were connected in different manners to replicate larger single modules to prove the concept of cells connected in series.

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Figure 12(a) compares the boost converter efficiency for a single cell and two series connected cells versus overall physical area of the DSSC modules at a lux level of 400. Note that for the series connections, equal sized cells from the same manufactured batch were applied in all cases. Clearly, higher efficiency per DSSC area is achieved for series connected vs. single cells, with up to 8% improvement typical over the range of areas considered. This is comparable to predictions in Section IV for smaller sized modules.

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Figure 12: (a) Converter efficiency versus DSSC physical area at 400 lux and (b) versus lux for an active area of 12 cm2.

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The next step was to measure the effect that increased lux has on DC-DC converter performance. For the same overall DSSC area, a comparison of efficiency produced with two smaller series connected cells is performed versus a larger single cell across a range of lux in Figure 12 (b). As expected, there is a significant increase in converter efficiency for an increase in lux. The increased DC-DC converter efficiency observed previously for series connected vs. single cells is verified across the indoor range of lux, with an increase of at least 6% confirmed from 200 – 700 lux.

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Corresponding results of output power delivery for an input light level of 400 lux are presented in Figure 13, where due to reduced cell active area required for connecting cells in series, the level of power improvement is approximately 6%. Again, this is in line with predicted levels of power in Figure 10 for similar module areas, and therefore confirms that larger improvements may be expected for larger modules.

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Figure 13: Power output of converter versus physical area at 400 lux.

5. CONCLUSIONS

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Optimisation of an energy harvesting system that consists of a low-voltage, low-power energy harvesting source connected to a step-up DC-DC converter has been demonstrated, where it has been shown that design procedures for maximum output power need to account for the combined effects of the electrical characteristics of the source and the DC-DC converter. This work focussed on small-sized DSSC modules, where it has been found that the there is an optimum number of series connected cells at which the output power is maximised for different module areas. Furthermore, the optimum number of cells varies with module area, where the effects of increasing DC/DC converter efficiency are offset to varying degrees by a reduced percentage DSSC active area. Up to 15% improvement in DC/DC converter efficiency is predicted with a corresponding increase in output power delivery by 8% for a 100 cm2 module, while measurements on module areas up to 21.8 cm2 confirm predictions for smaller modules. These results are very useful for system designers of DSSC powered wireless sensors because once the available DSSC area and load voltage requirements are defined, an optimum cell configuration can be determined prior to fabrication.

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While the focus is on DSSC’s in this paper, a similar methodology, as outlined in Figure 11, may be applied to identify optimum overall system performance for other low-voltage energy harvesting sources (e.g. thermoelectric and microbial fuel-cells), where the potential for varying the energy harvester elemental configuration to increase its maximum power point voltage will be considered in combination with power conversion losses so that the overall system efficiency and power delivery is maximised. Such optimisation will allow sensors such as required in BMS applications to operate more autonomously or for more data to be sensed. In addition, results of the breakdown in power converter losses may be applied to assess new methods for power conversion efficiency under low-voltage, low-power conditions.

6. ACKNOWLEDGMENT

This work is funded by the Irish Research Council (IRC) and SolarPrint under the Enterprise Partnership scheme.

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