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Si Infrared Detector
Available online at www.sciencedirect.com
ScienceDirect Procedia Engineering 140 (2016) 203 – 208
MRS Singapore – ICMAT Symposia Proceedings 8th International Conference on Materials for Advanced Technologies
Effect of Interface Trap States on Optical Barrier Height of NiSi/Si Infrared Detector Sandipta Roya,b, Siddartha P. Duttaguptab,c,*, Ramakrishnan Desikand a b
Centre for Nanotechnology and Science, Indian Institute of Technology Bombay, Mumbai-400076, India Centre of Excellence in Nanoelectronics, Indian Institute of Technology Bombay, Mumbai 400076, India c Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai-400076, India d Department of Earth Science, Indian Institute of Technology Bombay, Mumbai-400076, India
Abstract In this paper, influence of interface trap states on barrier height of NiSi/Si Schottky diode is presented. The proposed study is important in view of its application potential as an infrared detector. This involves preparation of silicide by depositing 10 nm thick nickel on n-Si, followed by rapid thermal annealing at 500 0C in argon ambience. The thickness of the silicide was measured by cross-sectional HRTEM and found to be 24 nm. The zero bias barrier heights were measured by current-voltage and optical techniques, and were found to be 0.62 eV and 0.54 eV respectively. This discrepancy in barrier height is attributed to the presence of acceptor like interface trap state which was identified by DLTS technique. © by Elsevier Ltd. by This is an open © 2016 2015Published The Authors. Published Elsevier Ltd.access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Selection and/or peer-review under responsibility of the scientific committee of Symposium 2015 ICMAT. Selection and/or peer-review under responsibility of the scientific committee of Symposium 2015 ICMAT Keywords: Infrared sensor; Nickel silicide; Interface trap states; DLTS
1. Introduction Fabrication of integrated photodetector is one of the critical aspects of developing silicon (Si) based infra-red detector. One possible solution is to grow germanium (Ge) on Si; as Ge has a band gap of 0.8 eV1. However, the
* Corresponding author. Tel.: +91-257-67866. E-mail address: [email protected]
1877-7058 © 2016 Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/). Selection and/or peer-review under responsibility of the scientific committee of Symposium 2015 ICMAT
doi:10.1016/j.proeng.2016.07.346
204
Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
epitaxial growth of Ge on Si pose a tremendous challenge due to possibility of occurrence of large defect states on account of lattice mismatch. Further, it also demands a high thermal budget. The alternative is to create interband trap states, which could be made by several technique such as doping, radiation treatment etc2, 3. However, these processes are not suitable for standard Si-CMOS technology due to their process complexity. Therefore, the silicide based Schottky barrier photo diode is the most promising solution inspite of its low quantum efficiency (~10-3 A/W). Here, the light detection is based on the photoexcitation of charge carriers at silicide and transfer of them across the silicide and silicon interface, where the cut-off wavelength ( ) is determined by barrier height ( ) of the Schottky diode.
(1)
Among the possible silicides, PtSi has been widely used as an infrared detector for mid infrared region (3-5 um). Further, IrSi is used even for longer wavelength regions (8-10 um)4. Recently, NiSi/n-Si Schottky diode was reported for near infrared (NIR) (1.3-1.8 um) detection5. However in case of NiSi/n-Si Schottky diode, it was observed that cut-off wavelength is longer than expected for a given barrier height. This behavior is mainly due to the presence of acceptor like interface trap states. These trap states capture optically exited electron from valence band even at lower (lower than ) energy region. In this work, we have demonstrated the presence of acceptor like trap states at the NiSi and Si interface using Deep Level Transient Spectroscopy (DLTS) technique. 2. Experiment details The NiSi/n-Si Schottky diode was fabricated by using n-Si substrate. NiSi Schottky contact on Si was formed by deposition of 10 nm Ni by RF sputter system and sequential annealing at 500°C for 60 sec. The details of the fabrication steps is described in Roy et.al5. High Resolution Transmission Electron Microscopy (HRTEM) imaging was done by using Jeol JEM 2100 F. X-ray Photo Electron Spectroscopy (XPS) analysis was performed by HI5000VersaProbe-II system. The I–V and C–V characterization was done by using Agilent B 1500. The optical properties of the device was measured by using Keithley 2400, the infrared illumination was done by Ultra Violet Visible near Infrared (UV-VIS-NIR) measurement setup. DLTS measurement was performed by Sula technologies system. The offset bias and pulse voltage was kept at -1 V and 0 V respectively. The measurement was done using rate window 5 and 50 ms. 3. Results and discussion
Figure 1:cross-sectional HRTEM image of NiSi/n-Si structure
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Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
The thickness of the silicide plays an important role in IR detection. It should be less than the mean free path of the photo exited hot electron to avoid cold electron scattering6. Reduction in the silicide thickness will enhance the detection performance as more photo-exited electron can reach to the interface. However, very thin silicide will increase the dark current. As a result, the photo current to dark current ratio reduces. The typical mean free path of hot electron is reported to be ~20 nm. Hence, in this study, the thickness of the silicide is maintained at 24 nm (shown in Figure 1) which is closely suitable for optical detection.The Ni2p XPS spectra of the thin film is shown in Figure 2. The spectrum correction was performed by C1s position (284.5 eV) to nullify the charge accumulation effect. The peaks at 853.7 eV and 871 eV corresponds to Ni2p3/2 and Ni2p1/2 respectively, which indicates that the developed silicide phase is NiSi. However, a small peak at 854.2 eV of Ni2p3/2 points to formation of fractional presence (~15%) of NiSi2 phase also. The doublet peak separation is 17.3 eV indicating the presence of metallic nature of silicide.
Figure 2: XPS spectra of Ni2p; inset shows the fitted peak of Ni2p3/2
The current-voltage (I–V) characteristics of the device is shown in the inset of Figure 3. The rectification ratio of the device has been observed to be 105. The diode I–V relationship of the device can be expressed as:
(2)
Where , are the leakage current density, Boltzmann constant and the measurement temperature (in Kelvin) respectively. Further can be expressed as follows:
(3)
Where and A* are the barrier height, Richardson constant of Si respectively. It is evident from the vs 1/kT plot (Richardson plot, Figure 3) that the barrier height of the device is 0.62 eV, and the calculated ideality factor is 1.3. Therefore, the cut-off wavelength of the device can be determined by using equation 1, which is found to be 2.0 µm. The optical response (R) of the device at different wavelengths was investigated to determine the optical barrier height of the SBD. The optical energy () vs photo response was plotted and shown in Figure 4. The responsivity was measured under zero bias condition. Based on the relationship of R and the optical barrier height was calculated by using Fowler equation5, 6.
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Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
where K is a proportionality constant.
(4)
Figure 3: Richardson plot of the device; inset shows the I-V characteristics of the device
Figure 4: Fowler plot of the device to calculate the optical barrier height.
The is determined to be 0.54 eV. This barrier height is lower than that determined by Richardson plot. This deviation in the estimates is attributed to the presence of acceptor like interface trap state5,7. These trap states capture photo generated electrons by absorbing photons less than the barrier height (generated the electron hole pair at valence band, when the irradiation energy ). As a result, the interface traps become negatively charged and contribute to the Fermi level carrier concentration at the interface between NiSi and Si. In addition occurrence of band bending also contributes to reduction of effective barrier height. The schematic diagram of the trapping of photo-generated electron is shown in the inset of Figure 5. To get more understanding on the type of interface traps, DLTS analysis was performed (shown in Figure 5). And it was observed that the transient change of capacitance is –ve, which eventually indicates that the trap states are acceptor like8. The DLTS was performed at an offset voltage of -1 V and the pulse voltage was 0 V. The rate window was kept as (t1 and t2) 5 and 50 ms respectively.
Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
207
The interface trap charge density (Nss) was found to be 6e12 eV-1 cm-2 which was calculated by capacitancefrequency method9 (shown in the figure 7). It can be observe form the figure that Nss decreases from the bottom of conduction band to mid gap. This characteristics probably attributes to the increase in series resistance with forward bias.
Figure 5: DLTS of the device to find out the type of trap states; inset shows the band diagram of the device.
Figure 7: The trap density distribution of the device calculated by C-V method
4. Conclusion It is evident from this study that for the fabricated NiSi/n-Si SBD device, the barrier height measured by electrical and optical techniques varied and was 0.62 and 0.54 eV respectively. The difference in barrier heights is mainly attributed to the presence of acceptor like interface trap-states. The relatively low estimates of optical barrier height is due to the capture of the photo-generated electron from valence band when irradiation energy is higher than
208
Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
( ). The presence of acceptor like interface trap states was verified by DLTS; and the trap density was 6e12 eV-1cm-2.These observations point to the potential of the developed sensor in NIR detection related applications. Acknowledgement The authors would like to thanks Sudipta Das, Centre for Nanotechnology and Science, IIT Bombay and Pankaj Upadhya, Department of Electrical Engineering, IIT Bombay for their fruitful discussion in DLTS analysis. References [1] [2] [3] [4] [5] [6] [7] [8] [9]
S. J. Koester; J. D. Schaub; G. Dehilinger; IEEE J. Sel. Topics Quantum Electron.12 (2006) 1489-1502. P. K. Kik; A. Ploman; S. Libertino; S. Coffa; J. Lightwave Technol. 20 (2002) 834-839. J. B. D. Bradley; P. E. Jessop; A. P. Knight; Appl. Phys. Lett. 86 (2005) 241103. B. Y. Tsaur; M. M. Weeks; P. W. Pellegrini; IEEE Electron Device Lett. 9 (1988) 100-103. S. Roy; K. Midya; S. P. Duttagupta; D. Ramakrishnan; J Appl. Phys. 116 (2014) 124507. P Niedermann; L Quattropani; Phys. Rev. B. 48 (1993) 8833-8839. B. K. Li; C. Wang; I. K. Sou; W. K. Ge, J. N. Wang; Appl. Phys. Lett. 91 (2007) 172104. D. K. Schroder; Semiconductor material and device characterization. John Wiley & Sons, 2006. K. Yamasaki, M. Yoshida, T. Sugano; J. J. Appl. Phys. 18 (1979) 113-122.
ScienceDirect Procedia Engineering 140 (2016) 203 – 208
MRS Singapore – ICMAT Symposia Proceedings 8th International Conference on Materials for Advanced Technologies
Effect of Interface Trap States on Optical Barrier Height of NiSi/Si Infrared Detector Sandipta Roya,b, Siddartha P. Duttaguptab,c,*, Ramakrishnan Desikand a b
Centre for Nanotechnology and Science, Indian Institute of Technology Bombay, Mumbai-400076, India Centre of Excellence in Nanoelectronics, Indian Institute of Technology Bombay, Mumbai 400076, India c Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai-400076, India d Department of Earth Science, Indian Institute of Technology Bombay, Mumbai-400076, India
Abstract In this paper, influence of interface trap states on barrier height of NiSi/Si Schottky diode is presented. The proposed study is important in view of its application potential as an infrared detector. This involves preparation of silicide by depositing 10 nm thick nickel on n-Si, followed by rapid thermal annealing at 500 0C in argon ambience. The thickness of the silicide was measured by cross-sectional HRTEM and found to be 24 nm. The zero bias barrier heights were measured by current-voltage and optical techniques, and were found to be 0.62 eV and 0.54 eV respectively. This discrepancy in barrier height is attributed to the presence of acceptor like interface trap state which was identified by DLTS technique. © by Elsevier Ltd. by This is an open © 2016 2015Published The Authors. Published Elsevier Ltd.access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Selection and/or peer-review under responsibility of the scientific committee of Symposium 2015 ICMAT. Selection and/or peer-review under responsibility of the scientific committee of Symposium 2015 ICMAT Keywords: Infrared sensor; Nickel silicide; Interface trap states; DLTS
1. Introduction Fabrication of integrated photodetector is one of the critical aspects of developing silicon (Si) based infra-red detector. One possible solution is to grow germanium (Ge) on Si; as Ge has a band gap of 0.8 eV1. However, the
* Corresponding author. Tel.: +91-257-67866. E-mail address: [email protected]
1877-7058 © 2016 Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/). Selection and/or peer-review under responsibility of the scientific committee of Symposium 2015 ICMAT
doi:10.1016/j.proeng.2016.07.346
204
Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
epitaxial growth of Ge on Si pose a tremendous challenge due to possibility of occurrence of large defect states on account of lattice mismatch. Further, it also demands a high thermal budget. The alternative is to create interband trap states, which could be made by several technique such as doping, radiation treatment etc2, 3. However, these processes are not suitable for standard Si-CMOS technology due to their process complexity. Therefore, the silicide based Schottky barrier photo diode is the most promising solution inspite of its low quantum efficiency (~10-3 A/W). Here, the light detection is based on the photoexcitation of charge carriers at silicide and transfer of them across the silicide and silicon interface, where the cut-off wavelength ( ) is determined by barrier height ( ) of the Schottky diode.
(1)
Among the possible silicides, PtSi has been widely used as an infrared detector for mid infrared region (3-5 um). Further, IrSi is used even for longer wavelength regions (8-10 um)4. Recently, NiSi/n-Si Schottky diode was reported for near infrared (NIR) (1.3-1.8 um) detection5. However in case of NiSi/n-Si Schottky diode, it was observed that cut-off wavelength is longer than expected for a given barrier height. This behavior is mainly due to the presence of acceptor like interface trap states. These trap states capture optically exited electron from valence band even at lower (lower than ) energy region. In this work, we have demonstrated the presence of acceptor like trap states at the NiSi and Si interface using Deep Level Transient Spectroscopy (DLTS) technique. 2. Experiment details The NiSi/n-Si Schottky diode was fabricated by using n-Si substrate. NiSi Schottky contact on Si was formed by deposition of 10 nm Ni by RF sputter system and sequential annealing at 500°C for 60 sec. The details of the fabrication steps is described in Roy et.al5. High Resolution Transmission Electron Microscopy (HRTEM) imaging was done by using Jeol JEM 2100 F. X-ray Photo Electron Spectroscopy (XPS) analysis was performed by HI5000VersaProbe-II system. The I–V and C–V characterization was done by using Agilent B 1500. The optical properties of the device was measured by using Keithley 2400, the infrared illumination was done by Ultra Violet Visible near Infrared (UV-VIS-NIR) measurement setup. DLTS measurement was performed by Sula technologies system. The offset bias and pulse voltage was kept at -1 V and 0 V respectively. The measurement was done using rate window 5 and 50 ms. 3. Results and discussion
Figure 1:cross-sectional HRTEM image of NiSi/n-Si structure
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Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
The thickness of the silicide plays an important role in IR detection. It should be less than the mean free path of the photo exited hot electron to avoid cold electron scattering6. Reduction in the silicide thickness will enhance the detection performance as more photo-exited electron can reach to the interface. However, very thin silicide will increase the dark current. As a result, the photo current to dark current ratio reduces. The typical mean free path of hot electron is reported to be ~20 nm. Hence, in this study, the thickness of the silicide is maintained at 24 nm (shown in Figure 1) which is closely suitable for optical detection.The Ni2p XPS spectra of the thin film is shown in Figure 2. The spectrum correction was performed by C1s position (284.5 eV) to nullify the charge accumulation effect. The peaks at 853.7 eV and 871 eV corresponds to Ni2p3/2 and Ni2p1/2 respectively, which indicates that the developed silicide phase is NiSi. However, a small peak at 854.2 eV of Ni2p3/2 points to formation of fractional presence (~15%) of NiSi2 phase also. The doublet peak separation is 17.3 eV indicating the presence of metallic nature of silicide.
Figure 2: XPS spectra of Ni2p; inset shows the fitted peak of Ni2p3/2
The current-voltage (I–V) characteristics of the device is shown in the inset of Figure 3. The rectification ratio of the device has been observed to be 105. The diode I–V relationship of the device can be expressed as:
(2)
Where , are the leakage current density, Boltzmann constant and the measurement temperature (in Kelvin) respectively. Further can be expressed as follows:
(3)
Where and A* are the barrier height, Richardson constant of Si respectively. It is evident from the vs 1/kT plot (Richardson plot, Figure 3) that the barrier height of the device is 0.62 eV, and the calculated ideality factor is 1.3. Therefore, the cut-off wavelength of the device can be determined by using equation 1, which is found to be 2.0 µm. The optical response (R) of the device at different wavelengths was investigated to determine the optical barrier height of the SBD. The optical energy () vs photo response was plotted and shown in Figure 4. The responsivity was measured under zero bias condition. Based on the relationship of R and the optical barrier height was calculated by using Fowler equation5, 6.
206
Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
where K is a proportionality constant.
(4)
Figure 3: Richardson plot of the device; inset shows the I-V characteristics of the device
Figure 4: Fowler plot of the device to calculate the optical barrier height.
The is determined to be 0.54 eV. This barrier height is lower than that determined by Richardson plot. This deviation in the estimates is attributed to the presence of acceptor like interface trap state5,7. These trap states capture photo generated electrons by absorbing photons less than the barrier height (generated the electron hole pair at valence band, when the irradiation energy ). As a result, the interface traps become negatively charged and contribute to the Fermi level carrier concentration at the interface between NiSi and Si. In addition occurrence of band bending also contributes to reduction of effective barrier height. The schematic diagram of the trapping of photo-generated electron is shown in the inset of Figure 5. To get more understanding on the type of interface traps, DLTS analysis was performed (shown in Figure 5). And it was observed that the transient change of capacitance is –ve, which eventually indicates that the trap states are acceptor like8. The DLTS was performed at an offset voltage of -1 V and the pulse voltage was 0 V. The rate window was kept as (t1 and t2) 5 and 50 ms respectively.
Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
207
The interface trap charge density (Nss) was found to be 6e12 eV-1 cm-2 which was calculated by capacitancefrequency method9 (shown in the figure 7). It can be observe form the figure that Nss decreases from the bottom of conduction band to mid gap. This characteristics probably attributes to the increase in series resistance with forward bias.
Figure 5: DLTS of the device to find out the type of trap states; inset shows the band diagram of the device.
Figure 7: The trap density distribution of the device calculated by C-V method
4. Conclusion It is evident from this study that for the fabricated NiSi/n-Si SBD device, the barrier height measured by electrical and optical techniques varied and was 0.62 and 0.54 eV respectively. The difference in barrier heights is mainly attributed to the presence of acceptor like interface trap-states. The relatively low estimates of optical barrier height is due to the capture of the photo-generated electron from valence band when irradiation energy is higher than
208
Sandipta Roy et al. / Procedia Engineering 140 (2016) 203 – 208
( ). The presence of acceptor like interface trap states was verified by DLTS; and the trap density was 6e12 eV-1cm-2.These observations point to the potential of the developed sensor in NIR detection related applications. Acknowledgement The authors would like to thanks Sudipta Das, Centre for Nanotechnology and Science, IIT Bombay and Pankaj Upadhya, Department of Electrical Engineering, IIT Bombay for their fruitful discussion in DLTS analysis. References [1] [2] [3] [4] [5] [6] [7] [8] [9]
S. J. Koester; J. D. Schaub; G. Dehilinger; IEEE J. Sel. Topics Quantum Electron.12 (2006) 1489-1502. P. K. Kik; A. Ploman; S. Libertino; S. Coffa; J. Lightwave Technol. 20 (2002) 834-839. J. B. D. Bradley; P. E. Jessop; A. P. Knight; Appl. Phys. Lett. 86 (2005) 241103. B. Y. Tsaur; M. M. Weeks; P. W. Pellegrini; IEEE Electron Device Lett. 9 (1988) 100-103. S. Roy; K. Midya; S. P. Duttagupta; D. Ramakrishnan; J Appl. Phys. 116 (2014) 124507. P Niedermann; L Quattropani; Phys. Rev. B. 48 (1993) 8833-8839. B. K. Li; C. Wang; I. K. Sou; W. K. Ge, J. N. Wang; Appl. Phys. Lett. 91 (2007) 172104. D. K. Schroder; Semiconductor material and device characterization. John Wiley & Sons, 2006. K. Yamasaki, M. Yoshida, T. Sugano; J. J. Appl. Phys. 18 (1979) 113-122.