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Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronic devices
World Abstracts on Mieroelectronies and Reliability superior to those of a plain surface, resulting in a substantial decrease in both the temperature overshoot and the incipient boiling heat flux. For the enhanced surfaces, subcooling generally resulted in an increase in incipient boiling heat flux when compared with the saturated conditions. Overall, this heat sink surface shows potential for use in the next generation of silicon multichip packaging for integrated microelectronics. Overview of packaging for the IBM enterprise system/9000 based on the glass-ceramic copper/thin film thermal conduction module. RAO R. TUMMALA and SHAKILAHMED. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(4), 426 (1992). The ES/9000 models 820 and 900 high performance mainframe processors have been significantly enhanced with respect to their predecessors. This has been made possible by a number of packaging advances: (1) multilayer glass-ceramic/copper cofired substrate; (2) multilayer polyimide/copper thin film structure; (3) discrete decoupling capacitors; (4) "buried" engineering change conductors; (5) enhanced pistons for very high thermal conduction cooling; and (6) enhanced flip-chip solder connections, This paper will describe some aspects of these advances in an overview fashion. It also summarizes the connectors and printed wiring board technologies used in this family of systems.
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operating temperature is acceptably low. Thermal analysis yields the packing limit of SOl MOSFET devices in terms of the targeted channel-to-substrate thermal conductance. Thermal conduction is microscale if it is significantly reduced by the boundary scattering of heat carriers, phonons in silicon and electrons in aluminum. Microscale effects are negligible above room temperature, but may reduce the packing limit by 44% for a substrate temperature of 77 K. Characterization and modelling of packages by a time-domain reflectometry approach. Luc VAN HAUWERMEIRENet al. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(4), 478 (1992). In this paper, we present an approach offering the possibility of characterizing different types of packages. The types that will be discussed are plastic leadless chip carrier (PLLCC), ceramic leadless chip carrier (CLLCC), pin grid array (PGA), and flat pack; all of which have a high I/O lead count. The characteristics of a signal pin (track inside the package) and the coupling between neighboring pins for different configurations is determined in the time domain by a time-domain reflectometry approach.
Thermal enhancements for a thin film chip carrier. SCOTT D. REYNOLDS, BAHGAT G. SAMMAKIA and TIMOTHY F. CARDEN. IEEE Transactions on ComPackaging technology for the NEC SX-3 Supereomponents, Hybrids, and Manufacturing Technology, puters. HIROSH! MURANO and TOSHIKIKOWATARI. 15(5), 699 (1992). This paper describes the developIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(4), 411 (1992). Since ment effort of a thermal enhancement technique the performance of a computer system is mainly targeted for single chip, thin film carriers. The test related to the machine cycle time, improvement of the package in this paper consisted of a 7.5 mm by logic circuit delay is the key for high-speed oper- 7.5 mm chip bonded to a high lead count organic tape ations. In order to show how to reduce the logic substrate using tape automated bonding (TAB). circuit delay, the characteristics required for LSI Because of high chip power requirements, a thermal chips and packaging technologies are discussed and enhancement consisting of a heat sink bonded to the the technological trends in packaging and their limi- chip with a thermally conductive epoxy was develtations are considered. In the last part, as a typical oped. The objectives of the current paper were to develop application of high performance packaging technolthe appropriate heat sink, thermal adhesive, and ogy, the NEC SX-3 Supercomputer packaging is introduced, featuring 9 inch squared polyimide-cer- assembly process for the heat management system. amic substrates, a microchip carrier flipped TAB The thermal performance of the package was evalucarrier (FTC), high density multichip packaging, ated in both natural and forced convection environhigh-speed coaxial cable interconnections, and a ments. Reliability measurements were taken to ensure the chip to heat sink interface and the overall package water cooling system. withstood the required stresses without significant Effect of microscale thermal conduction on the packing performance deterioration. These stresses included limit of silicon-on-insulator electronic devices. K. E. standard accelerated thermal cycling (ATC), ship GOODSON and M. I. FLIK. IEEE Transactions on shock, mechanical torque and vibration, and chemiComponents, Hybrids, and Manufacturing Technol- cal exposure. ogy, 15(5), 715 (1992). Silicon-on-insulator (SOI) electronic circuits have a buried silicon dioxide Plasma-based dry etching techniques in the silicon layer which inhibits device cooling and reduces integrated circuit technology. G. S. OEHRLEINand J. F. the thermal packing limit, the largest number of REMBETSKI. IBM Journal of Research and Developdevices per unit substrate area for which the device ment, 36(2), 140 (1992). Plasma-based dry etching
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operating temperature is acceptably low. Thermal analysis yields the packing limit of SOl MOSFET devices in terms of the targeted channel-to-substrate thermal conductance. Thermal conduction is microscale if it is significantly reduced by the boundary scattering of heat carriers, phonons in silicon and electrons in aluminum. Microscale effects are negligible above room temperature, but may reduce the packing limit by 44% for a substrate temperature of 77 K. Characterization and modelling of packages by a time-domain reflectometry approach. Luc VAN HAUWERMEIRENet al. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(4), 478 (1992). In this paper, we present an approach offering the possibility of characterizing different types of packages. The types that will be discussed are plastic leadless chip carrier (PLLCC), ceramic leadless chip carrier (CLLCC), pin grid array (PGA), and flat pack; all of which have a high I/O lead count. The characteristics of a signal pin (track inside the package) and the coupling between neighboring pins for different configurations is determined in the time domain by a time-domain reflectometry approach.
Thermal enhancements for a thin film chip carrier. SCOTT D. REYNOLDS, BAHGAT G. SAMMAKIA and TIMOTHY F. CARDEN. IEEE Transactions on ComPackaging technology for the NEC SX-3 Supereomponents, Hybrids, and Manufacturing Technology, puters. HIROSH! MURANO and TOSHIKIKOWATARI. 15(5), 699 (1992). This paper describes the developIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(4), 411 (1992). Since ment effort of a thermal enhancement technique the performance of a computer system is mainly targeted for single chip, thin film carriers. The test related to the machine cycle time, improvement of the package in this paper consisted of a 7.5 mm by logic circuit delay is the key for high-speed oper- 7.5 mm chip bonded to a high lead count organic tape ations. In order to show how to reduce the logic substrate using tape automated bonding (TAB). circuit delay, the characteristics required for LSI Because of high chip power requirements, a thermal chips and packaging technologies are discussed and enhancement consisting of a heat sink bonded to the the technological trends in packaging and their limi- chip with a thermally conductive epoxy was develtations are considered. In the last part, as a typical oped. The objectives of the current paper were to develop application of high performance packaging technolthe appropriate heat sink, thermal adhesive, and ogy, the NEC SX-3 Supercomputer packaging is introduced, featuring 9 inch squared polyimide-cer- assembly process for the heat management system. amic substrates, a microchip carrier flipped TAB The thermal performance of the package was evalucarrier (FTC), high density multichip packaging, ated in both natural and forced convection environhigh-speed coaxial cable interconnections, and a ments. Reliability measurements were taken to ensure the chip to heat sink interface and the overall package water cooling system. withstood the required stresses without significant Effect of microscale thermal conduction on the packing performance deterioration. These stresses included limit of silicon-on-insulator electronic devices. K. E. standard accelerated thermal cycling (ATC), ship GOODSON and M. I. FLIK. IEEE Transactions on shock, mechanical torque and vibration, and chemiComponents, Hybrids, and Manufacturing Technol- cal exposure. ogy, 15(5), 715 (1992). Silicon-on-insulator (SOI) electronic circuits have a buried silicon dioxide Plasma-based dry etching techniques in the silicon layer which inhibits device cooling and reduces integrated circuit technology. G. S. OEHRLEINand J. F. the thermal packing limit, the largest number of REMBETSKI. IBM Journal of Research and Developdevices per unit substrate area for which the device ment, 36(2), 140 (1992). Plasma-based dry etching