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Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget
MR-12583; No of Pages 6 Microelectronics Reliability xxx (2017) xxx–xxx
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Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget Eun-Ki Hong, Won-Ju Cho ⁎ Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 2 February 2017 Received in revised form 11 May 2017 Accepted 17 July 2017 Available online xxxx Keywords: Metal-oxide-semiconductor field-effect-transistor (MOSFET) Microwave irradiation (MWI) Post-metal anneal (PMA) Silicon-on-insulator (SOI)
a b s t r a c t We investigate the effect of microwave irradiation (MWI) on silicon-on-insulator (SOI) based MOSFETs. The MWI technique is used for post-metal annealing (PMA) in air ambient, and compared with conventional thermal annealing in a forming gas ambient. This type of annealing not only constitutes a low cost, short time, low temperature, vacuum-free alternative to conventional post-metal annealing methods, but it also allows much lower thermal budgets, which, in turn, minimizes dopant motion, redistribution, and diffusion. The MWI treated MOSFETs showed superior electrical characteristics in terms of field effect mobility, on-off ratio, subthreshold swing, interface trap density, stability, and hot carrier effect immunity. Therefore, MWI technology is expected to become a promising annealing method for silicon-based processes, with low cost and low thermal budget. © 2017 Published by Elsevier Ltd.
1. Introduction The integration and performance of silicon complimentary metaloxide-semiconductor (Si CMOS) devices have improved considerably, mainly because of the continuous technological scaling down [1–2]. However, device dimensions are approaching the fundamental physical limit of the nanometer regime. In addition, adverse effects such as subthreshold swing (S) degradation, threshold voltage (VTH) variation, drain induced barrier lowering (DIBL) [3], and current leakage resulting from the short-channel effect phenomenon have increasingly hindered further miniaturization of silicon devices [4]. Several solutions to overcome these difficulties have been proposed: new materials [5–7], the inclusion of non-classical device structures [8], and advanced processes [9–10]. In this work, we focus on the low thermal budget post-metal annealing (PMA) of metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on silicon. PMA is an essential process in CMOS fabrication, to enhance the electrical characteristics and stability of MOSFETs by recovering from crystal damage or eliminating the interface trap [11]. Post-metal annealing must be free from chemical or mechanical modifications during the process: it should also be conducted at low temperature, to avoid changes in the source and drain (S/D) junction depth. Additionally, the interface traps have to be effectively removed. To meet these requirements, furnace annealing with a forming gas (H2, N2 or D2, N2 mixed) has been widely used. However, it is an expensive
⁎ Corresponding author. E-mail address: [email protected] (W.-J. Cho).
method, and requires high temperature, in the 400–500 °C range. Consequently, a novel annealing technology with low thermal budget and low process cost is highly desirable. The thermal budget is defined as being the total amount of energy transferred to the wafer during annealing process, and is proportional to the annealing time and temperature. Reducing the thermal budget of the annealing process is a conspicuously important goal in the overall device fabrication process, because such a reduction will directly increase the productivity and create considerable economically benefits. To address this goal, we use microwave irradiation (MWI) in this work, and evaluate its effectiveness as a PMA method for Si CMOS devices. Unlike conventional thermal annealing (CTA) methods, which transfer thermal energy from the sample surface to its interior, microwaves are capable of providing rapid volumetric heating, because they directly interact with individual atoms, causing the rotation of the dipoles within the silicon substrate. Therefore, microwave annealing is a promising approach towards enhancing energy usage efficiency, in comparison to conventional resistance heating furnace. In particular, the many advantages of MWI technology include: thermal uniformity, rapid heating, shortened manufacturing period, low thermal budget, being a vacuum-free process, and suppression of unexpected species diffusion [12]. According to the results of previous studies, there are several reports on the impurity activation using microwave energy, but there is no report applied to the PMA process to improve the performance of SOI MOSFETs [13–20]. Therefore, in this study, we focused on the purpose of improving the electrical characteristics and stability by applying microwave energy to PMA process of SOI MOSFETs. Accordingly, we evaluate the transfer characteristics, output characteristics,
http://dx.doi.org/10.1016/j.microrel.2017.07.070 0026-2714/© 2017 Published by Elsevier Ltd.
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
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E.-K. Hong, W.-J. Cho / Microelectronics Reliability xxx (2017) xxx–xxx
reliability, and hot carrier effect immunity of silicon-on-insulator (SOI) MOSFETs subjected to a PMA process performed with an MWI system. As a result, compared with PMA using CTA, MWI was able to secure not only superior electrical characteristics but also stability by a low temperature and short time heat treatment process.
2. Experiment details The SOI MOSFETs with top gate configuration were fabricated on the p-type (100) SOI substrate with a 100-nm-thick top silicon layer and a 750-nm-thick buried oxide (BOX) layer. First, standard RCA cleaning was carried out, to remove surface contaminations. The active region was then defined by photolithography and dry etching, using a reactive ion etching (RIE) system. A phosphorus doped poly-Si film with a thickness of 150 nm was deposited by low-pressure chemical vapor deposition (LPCVD) at 650 °C, for source/drain (S/D) formation. Subsequently, the phosphorus doped poly-Si film was removed by dry etching (with the exception of the S/D region), and a thinning of the top silicon layer using RIE followed, to obtain a fully depleted silicon channel. The channel thickness (Tch), width (W), and length (L) of the fabricated SOI MOSFETs were 20 nm, 20 μm, and 10 μm, respectively. A 10-nm-thick SiO2 gate insulator was then deposited using RF sputtering (O2/Ar flow of 2/30 sccm, working pressure of 4 mTorr). The contact holes for the S/D electrodes were opened by dry etching, and rapid thermal annealing (RTA) was carried out at 950 °C for 30 s in N2/O2 ambient, for activation of the phosphorus atoms at the S/D regions. The aluminum (Al) gate electrode was formed using RF magnetron sputter, photolithography and a wet etching process. Finally, post-metal annealing (PMA) was conducted, to remove the defects at the gate oxide/Si channel interface, and improve the contact properties between the Si and Al at the S/D regions. In particular, for the PMA process, a microwave with a frequency of 2.45 GHz was used, in air ambient. The effects of microwave irradiation power and irradiation time on device performance were investigated. In addition, counterpart control devices were also fabricated (for comparison with the MWI processed devices) by conventional thermal annealing (CTA) in a furnace at 450 °C, for 30 min, in 5% H2 in N 2 ambient forming gas annealing (FGA). Fig. 1 shows the schematic structure of the fabricated SOI MOSFETs. To confirm the PMA effect, their electrical characteristics-including the transfer and output curves were measured. Furthermore, their reliability was evaluated by performing hot carrier effect immunity and instability tests. All measurements were performed in a dark box to avoid external influences such as light and electrical noise using an Agilent 4156B Precision Semiconductor Parameter Analyzer.
3. Results and discussion Fig. 2 shows the electrical characteristics of the fabricated SOI MOSFETs, after a 2 min irradiation with different values of microwave power, in the 150–1800 W range. As can be clearly seen from the transfer curves of Fig. 2(a) and output curves of Fig. 2(b), the electrical characteristics of the SOI MOSFETs were considerably improved by the PMA MWI process, when compared to the control devices without PMA. Table 1 summarizes the electrical parameters of the SOI MOSFETs for different microwave powers, as extracted from the transfer characteristics. As shown, the electrical characteristics of the SOI MOSFETs saturated when the microwave power exceeded 250 W. It should be noted that the process temperature during the MWI treatment (250 W for 120 s) was 45 °C, as measured by a thermocouple in contact with the sample. Fig. 3 shows the effect of MWI time on the SOI MOSFETs' performance. The microwave irradiation times were maintained in the 30– 120 s range, at a 250 W power. The electrical parameters extracted from the obtained transfer curves are summarized in Table 2. As shown, the electrical characteristics were gradually improved by increasing the duration of microwave irradiation, but then saturated for a value of approximately 90 s. Finally, to investigate the effect of the different PMA methods, we compared the electrical characteristics of the devices processed with the conventional resistance heating furnace (FGA devices), air ambient microwave irradiation (MWI devices), and devices without-PMA processing. Based on the experimental results of Figs. 2 and 3, we used the optimal MWI process conditions for PMA: 250 W, during 2 min. Fig. 4(a) shows the transfer characteristic curves of the SOI MOSFETs for the various annealing methods: without-PMA, FGA and MWI. It was found that the device without-PMA showed poor electrical characteristics: the highest leakage currents, lowest drain currents, and largest subthreshold slopes. It is interesting to note that the MWI devices have shown superior electrical characteristics in spite of the lower processing temperature (45 °C) and shorter processing times (2 min) in air when compared with the FGA devices processed at 450 °C for 30 min in 5% H2 in N2 forming gas. This result implies that the MWI method is not only applicable to PMA processing, but is in fact a strong candidate to replace the conventional FGA method, as a result of the superior electrical characteristics of the processed devices. The field effect mobility (μFE), threshold voltage (VTH), on-off ratio, subthreshold swing (S), and interface trap density (Dit) at the gate oxide/Si channel are summarized in Table 3, for all three cases (without-PMA, FGA and MWI). Among these parameters, one of the most important in determining the resulting transistor performance is the field effect mobility, because it determines the transistor behavior in terms of drive current and frequency response. The field effect mobility μFE of the measured devices
Fig. 1. Schematic structure of the fabricated SOI MOSFETs.
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
E.-K. Hong, W.-J. Cho / Microelectronics Reliability xxx (2017) xxx–xxx
3
Fig. 2. (a) Transfer characteristic curves and (b) output characteristic curves of SOI MOSFETs depending on microwave irradiated power.
Table 1 Field effect mobility (μFE), threshold voltage (VTH), on/off ratio, subthreshold swing (S), interface trap density at channel/insulator (Dit) of the SOI MOSFETs, for various values of MWI power 2 min irradiation. PMA conditions w/o PMA MWI (150 W) MWI (250 W) MWI (600 W) MWI (1000 W) MWI (1400 W) MWI (1800 W)
μFE (cm2/V·s) 82.4 142.4 243.7 257.3 249.5 237.6 242.36
VTH (V)
ION/IOFF 5
−1.54 −0.46 −0.40 −0.22 −0.29 −0.42 −0.40
2.85 × 10 6.74 × 105 3.30 × 106 5.38 × 106 2.14 × 106 1.88 × 106 2.04 × 106
for each PMA variant are 82.4, 184.7, and 243.7 cm2/V·s, for the without-PMA, FGA, and MWI cases, respectively. Therefore, the MWI treated device showed the highest mobility. The field effect mobility can be determined from following equation: μ FE ¼
Lgm ∂ID ; gm ¼ WCox VD ∂VG VD ¼const
ð1Þ
L, W, Cox and gm are the channel length, width, gate oxide capacitance, and transconductance, respectively. As shown in Eq. (1), gm is proportional to the partial derivative of drain current (ID), strongly influencing the μFE of the MOSFETs, given that all measured devices have the same values of W, L, Cox, and VD. Therefore, the enhancement of μFE is mainly attributed to the decrease in channel resistance created by the MWI. It is important to note here that the driving capability of
S (mV/decade)
Dit (cm−2·eV−1)
385 78 73 75 83 78 80
1.4 × 1013 2.8 × 1012 2.7 × 1012 2.7 × 1012 3.0 × 1012 2.8 × 1012 2.9 × 1012
MOSFETs is remarkably improved by MWI, without changing the W/L adjustment and the composition of the oxide materials, and with significantly low processing temperatures and short processing time, when compared with FGA devices. The threshold voltage VTH for each type of annealing were − 1.54, − 0.41, and − 0.40 V for the without-PMA, FGA, and MWI cases, respectively. The threshold voltage (VTH) is defined as the gate voltage necessary to form an inversion channel layer, using the following equation: ID ¼ μ n COX
W ðVG −VTH Þ2 2L
ð2Þ
The on-off ratio is defined as the ratio between the maximum and minimum drain currents in the saturation region of the device operating range. The on-off ratio is affected by the off current and the increase in the gate dielectric current. The on-off ratio values for each of the
Fig. 3. (a) Transfer characteristic curves and (b) output characteristic curves of SOI MOSFETs depending on microwave irradiated time.
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
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Table 2 Field effect mobility (μFE), threshold voltage (VTH), on/off ratio, subthreshold swing (S), interface trap density at channel/insulator (Dit) of the SOI MOSFETs for different irradiation times. The MWI power was fixed at 250 W. PMA conditions
μFE (cm2/V·s)
VTH (V)
ION/IOFF
S (mV/decade)
Dit (cm−2·eV−1)
MWI (30 s) MWI (60 s) MWI (90 s) MWI (120 s)
197.1 257.3 241.2 243.7
−2.61 −1.91 −0.40 −0.40
2.27 × 105 3.98 × 105 2.04 × 106 3.30 × 106
355 294 78 73
1.3 × 1013 1.1 × 1013 2.8 × 1012 2.7 × 1012
Fig. 4. (a) Transfer and (b) output characteristics curves of the SOI MOSFETs, for different annealing method: without-PMA, FGA at 450 °C for 30 min, and MWI at 250 W for 2 min.
measured devices are 2.85 × 105, 1.78 × 106, 3.30 × 106 for the withoutPMA, FGA, and MWI cases, respectively, with the highest value being obtained for the MWI case. The subthreshold swing S is defined as the change in voltage required to increase the drain current by a factor of 10 in the transfer characteristics, it can be obtained using the following equation: S¼
dVGS d logIDS
ð3Þ
The S value is identifiable with the maximum slope value in the transfer characteristic curves. The subthreshold swing S and threshold voltage VTH are very important parameters in the transistor switching behavior, and in reducing power consumption. The subthreshold swing values obtained for the without-PMA, FGA and MWI cases were 385, 77 and 73 mV/decade, respectively, with the lowest swing being obtained for the MWI case. The interface trap density Dit can be extracted from the SOI MOSFETs' S value, using the following equation: Dit ¼
S logðeÞ C −1 i kB T=q q
ð4Þ
q, kB, Ci and T are the electron charge, Boltzmann's constant, gate insulator capacitance per unit area, and absolute temperature, respectively. The magnitude of the extracted Dit for the without-PMA, FGA and MWI cases were 1.4 × 1013, 2.8 × 1012, and 2.7 × 1012 cm−2·eV−1, respectively. This means that the MWI effectively eliminated the defects at the channel/insulator interface [21]. As a summary, we may conclude that, according to results of the measured transfer characteristic curves
and the extracted parameters of the fabricated SOI MOSFETs, the field effect mobility (μFE), on-off ratio, subthreshold swing (S), and interface trap density (Dit) were all improved by MWI processing, in spite of the remarkably low processing temperature (45 °C), and short processing time (2 min) when compared with FGA. Another aspect that requires evaluation is the impact of the longterm use on the degradation of the electrical characteristics of semiconductor devices, such as mobility, swing and VTH shift. We therefore conducted the positive gate bias stress (PBS) and negative gate bias stress (NBS) test to evaluate the effect of the PMA on the stability of the resulting SOI MOSFETs as shown in Fig. 5. The gate bias conditions for the instability test were: ± 2 MV/cm for 1 h, at VD = 1 V. The threshold voltage shifts were measured at (a) 25 °C and (b) 120 °C. Table 4 summarizes the observed variation of the threshold voltage (ΔVTH) for the various PMA conditions and measurement types. In the without-PMA case, a significant degradation was observed, both at room temperature (25 °C) and at high temperature (120 °C). On the contrary, the FGA and MWI treated devices did not deteriorated, neither at room temperature, nor at high temperature. Fig. 6 shows the threshold voltage shift of the SOI MOSFETs induced by hot carrier effect measurement for the three PMA cases: withoutPMA, FGA (450 °C for 30 min), and MWI (250 W for 2 min). The gate bias stress and drain bias stress were fixed at 10 V and 5 V for 1 h, respectively. In the without-PMA case, a considerable degradation was measured, as a result of hot electrons in the channel layer, whereas both the FGA and MWI treated devices did not degrade [22]. In particular, it should be noted that the MWI treated SOI MOSFETs showed good hot carrier immunity, at a level almost comparable to that of the FGA devices.
Table 3 Field effect mobility (μFE), threshold voltage (VTH), on/off ratio, subthreshold swing (S), interface trap density at channel/insulator (Dit) of the SOI MOSFETs for all three cases: withoutPMA, FGA at 450 °C for 30 min, and MWI at 250 W for 2 min. PMA conditions w/o PMA FGA MWI
μFE (cm2/V·s) 82.4 184.7 243.7
VTH (V) −1.54 −0.41 −0.40
ION/IOFF 5
2.85 × 10 1.78 × 106 3.30 × 106
S (mV/decade)
Dit (cm−2·eV−1)
385 77 73
1.4 × 1013 2.8 × 1012 2.7 × 1012
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
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5
Fig. 5. Threshold voltage shifts of the SOI MOSFETs by instability measurement at (a) 25 °C and (b) 120 °C. An induced gate bias stress of ±2 MV/cm was used, during 1 h.
4. Conclusion In summary, a new approach to enhance the electrical characteristics of Si based devices was proposed, by applying MWI as the essential PMA process in CMOS device fabrication. Both MWI and FGA treated SOI MOSFETs were fabricated, and their electrical characteristics were evaluated and compared. The SOI MOSFETs treated by the low thermal budget MWI process (45 °C for 2 min) exhibited excellent transistor characteristics: lower subthreshold swing and interface trap density, and higher field effect mobility and on-off ratio than FGA treated devices. These results can be ascribed to the direct thermal transfer mechanism of microwave irradiation. Additionally, MWI treated SOI MOSFETs showed good long-term stability and hot carrier immunity,
Table 4 ΔVTH of the SOI MOSFFTs for different PMA conditions. The gate bias stress test was performed with 2 MV/cm for 1 h. PMA conditions
NBS (25 °C)
PBS (25 °C)
NBTS (120 °C)
PBTS (120 °C)
w/o PMA FGA MWI
−0.12 V 0V 0V
0.16 V 0V 0V
−0.6 V 0V 0V
0.73 V 0V 0V
Fig. 6. Threshold voltage shift of SOI MOSFETs by hot carrier effect measurement (a) w/o PMA, (b) forming gas annealing at 450 °C for 30 min, (c) microwave irradiation 250 W for 2 min. The gate bias stress and drain bias stress were fixed at 10 V, 5 V for 1 h, respectively.
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
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at a level which is almost comparable to that of FGA devices. Our results indicate that the MWI method is applicable as a next-generation PMA process, replacing the conventional FGA method, because it exhibits higher levels of cost effectiveness and productivity for silicon-based device. Furthermore, the MWI based PMA process constitutes also a promising technique for transparent and flexible electronic display applications. Acknowledgments This study was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Science and Technology (No. 2016R1A2B4008754). References [1] R.R. Schaller, Technological Innovation in the Semiconductor Industry: A Case Study of the International Technology Roadmap for Semiconductors (ITRS)(Diss.) George Mason University, 2004. [2] M. Ieong, B. Doris, J. Kedzierski, K. Rim, M. Yang, Silicon device scaling to the sub-10nm regime, Science 306 (2004) 2057. [3] M.J. Deen, Z.X. Yan, DIBL in short-channel NMOS devices at 77 K, IEEE Trans. Electron Dev. 39 (1992) 908. [4] K.K. Young, Short-channel effect in fully depleted SOI MOSFETs, IEEE Trans. Electron Dev. 36 (1989) 399. [5] A. Pethe, et al., Device Innovation and Material Challenges at the Limits of CMOS Technology, IEDM Tech. Dig. 135, 2005 619. [6] N. Mazure, F. Dayan, D. Roux, E. Berra, C.B. Horn, J. Poussegur, 3 Hypoxia signaling impact on tumor metabolism, cell survival & cell death, Radiother. Oncol. 78 (2006) S1. [7] S.B. Samavedam, L.B. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J. Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H.H. Tseng, P.J. Tobin, D.C. Gilmer, C. Hobbs, W.J. Taylor, J.M. Grant, R.I. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalam, M. Sadd, B.-Y. Nguyen, B. White, Dualmetal Gate CMOS with HfOz Gate Dielectric, IEDM Tech. Dig. 433, 2002. [8] H.-S.P. Wong, D.J. Frank, P.M. Solomon, Device Design Considerations for Doublegate, Ground-plane, and Single-gated Ultra-thin SO1 MOSFET's at the 25 nm Chiannel Length Generation, IEDM Tech. Dig. 407, 1998.
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Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget Eun-Ki Hong, Won-Ju Cho ⁎ Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 2 February 2017 Received in revised form 11 May 2017 Accepted 17 July 2017 Available online xxxx Keywords: Metal-oxide-semiconductor field-effect-transistor (MOSFET) Microwave irradiation (MWI) Post-metal anneal (PMA) Silicon-on-insulator (SOI)
a b s t r a c t We investigate the effect of microwave irradiation (MWI) on silicon-on-insulator (SOI) based MOSFETs. The MWI technique is used for post-metal annealing (PMA) in air ambient, and compared with conventional thermal annealing in a forming gas ambient. This type of annealing not only constitutes a low cost, short time, low temperature, vacuum-free alternative to conventional post-metal annealing methods, but it also allows much lower thermal budgets, which, in turn, minimizes dopant motion, redistribution, and diffusion. The MWI treated MOSFETs showed superior electrical characteristics in terms of field effect mobility, on-off ratio, subthreshold swing, interface trap density, stability, and hot carrier effect immunity. Therefore, MWI technology is expected to become a promising annealing method for silicon-based processes, with low cost and low thermal budget. © 2017 Published by Elsevier Ltd.
1. Introduction The integration and performance of silicon complimentary metaloxide-semiconductor (Si CMOS) devices have improved considerably, mainly because of the continuous technological scaling down [1–2]. However, device dimensions are approaching the fundamental physical limit of the nanometer regime. In addition, adverse effects such as subthreshold swing (S) degradation, threshold voltage (VTH) variation, drain induced barrier lowering (DIBL) [3], and current leakage resulting from the short-channel effect phenomenon have increasingly hindered further miniaturization of silicon devices [4]. Several solutions to overcome these difficulties have been proposed: new materials [5–7], the inclusion of non-classical device structures [8], and advanced processes [9–10]. In this work, we focus on the low thermal budget post-metal annealing (PMA) of metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on silicon. PMA is an essential process in CMOS fabrication, to enhance the electrical characteristics and stability of MOSFETs by recovering from crystal damage or eliminating the interface trap [11]. Post-metal annealing must be free from chemical or mechanical modifications during the process: it should also be conducted at low temperature, to avoid changes in the source and drain (S/D) junction depth. Additionally, the interface traps have to be effectively removed. To meet these requirements, furnace annealing with a forming gas (H2, N2 or D2, N2 mixed) has been widely used. However, it is an expensive
⁎ Corresponding author. E-mail address: [email protected] (W.-J. Cho).
method, and requires high temperature, in the 400–500 °C range. Consequently, a novel annealing technology with low thermal budget and low process cost is highly desirable. The thermal budget is defined as being the total amount of energy transferred to the wafer during annealing process, and is proportional to the annealing time and temperature. Reducing the thermal budget of the annealing process is a conspicuously important goal in the overall device fabrication process, because such a reduction will directly increase the productivity and create considerable economically benefits. To address this goal, we use microwave irradiation (MWI) in this work, and evaluate its effectiveness as a PMA method for Si CMOS devices. Unlike conventional thermal annealing (CTA) methods, which transfer thermal energy from the sample surface to its interior, microwaves are capable of providing rapid volumetric heating, because they directly interact with individual atoms, causing the rotation of the dipoles within the silicon substrate. Therefore, microwave annealing is a promising approach towards enhancing energy usage efficiency, in comparison to conventional resistance heating furnace. In particular, the many advantages of MWI technology include: thermal uniformity, rapid heating, shortened manufacturing period, low thermal budget, being a vacuum-free process, and suppression of unexpected species diffusion [12]. According to the results of previous studies, there are several reports on the impurity activation using microwave energy, but there is no report applied to the PMA process to improve the performance of SOI MOSFETs [13–20]. Therefore, in this study, we focused on the purpose of improving the electrical characteristics and stability by applying microwave energy to PMA process of SOI MOSFETs. Accordingly, we evaluate the transfer characteristics, output characteristics,
http://dx.doi.org/10.1016/j.microrel.2017.07.070 0026-2714/© 2017 Published by Elsevier Ltd.
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
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reliability, and hot carrier effect immunity of silicon-on-insulator (SOI) MOSFETs subjected to a PMA process performed with an MWI system. As a result, compared with PMA using CTA, MWI was able to secure not only superior electrical characteristics but also stability by a low temperature and short time heat treatment process.
2. Experiment details The SOI MOSFETs with top gate configuration were fabricated on the p-type (100) SOI substrate with a 100-nm-thick top silicon layer and a 750-nm-thick buried oxide (BOX) layer. First, standard RCA cleaning was carried out, to remove surface contaminations. The active region was then defined by photolithography and dry etching, using a reactive ion etching (RIE) system. A phosphorus doped poly-Si film with a thickness of 150 nm was deposited by low-pressure chemical vapor deposition (LPCVD) at 650 °C, for source/drain (S/D) formation. Subsequently, the phosphorus doped poly-Si film was removed by dry etching (with the exception of the S/D region), and a thinning of the top silicon layer using RIE followed, to obtain a fully depleted silicon channel. The channel thickness (Tch), width (W), and length (L) of the fabricated SOI MOSFETs were 20 nm, 20 μm, and 10 μm, respectively. A 10-nm-thick SiO2 gate insulator was then deposited using RF sputtering (O2/Ar flow of 2/30 sccm, working pressure of 4 mTorr). The contact holes for the S/D electrodes were opened by dry etching, and rapid thermal annealing (RTA) was carried out at 950 °C for 30 s in N2/O2 ambient, for activation of the phosphorus atoms at the S/D regions. The aluminum (Al) gate electrode was formed using RF magnetron sputter, photolithography and a wet etching process. Finally, post-metal annealing (PMA) was conducted, to remove the defects at the gate oxide/Si channel interface, and improve the contact properties between the Si and Al at the S/D regions. In particular, for the PMA process, a microwave with a frequency of 2.45 GHz was used, in air ambient. The effects of microwave irradiation power and irradiation time on device performance were investigated. In addition, counterpart control devices were also fabricated (for comparison with the MWI processed devices) by conventional thermal annealing (CTA) in a furnace at 450 °C, for 30 min, in 5% H2 in N 2 ambient forming gas annealing (FGA). Fig. 1 shows the schematic structure of the fabricated SOI MOSFETs. To confirm the PMA effect, their electrical characteristics-including the transfer and output curves were measured. Furthermore, their reliability was evaluated by performing hot carrier effect immunity and instability tests. All measurements were performed in a dark box to avoid external influences such as light and electrical noise using an Agilent 4156B Precision Semiconductor Parameter Analyzer.
3. Results and discussion Fig. 2 shows the electrical characteristics of the fabricated SOI MOSFETs, after a 2 min irradiation with different values of microwave power, in the 150–1800 W range. As can be clearly seen from the transfer curves of Fig. 2(a) and output curves of Fig. 2(b), the electrical characteristics of the SOI MOSFETs were considerably improved by the PMA MWI process, when compared to the control devices without PMA. Table 1 summarizes the electrical parameters of the SOI MOSFETs for different microwave powers, as extracted from the transfer characteristics. As shown, the electrical characteristics of the SOI MOSFETs saturated when the microwave power exceeded 250 W. It should be noted that the process temperature during the MWI treatment (250 W for 120 s) was 45 °C, as measured by a thermocouple in contact with the sample. Fig. 3 shows the effect of MWI time on the SOI MOSFETs' performance. The microwave irradiation times were maintained in the 30– 120 s range, at a 250 W power. The electrical parameters extracted from the obtained transfer curves are summarized in Table 2. As shown, the electrical characteristics were gradually improved by increasing the duration of microwave irradiation, but then saturated for a value of approximately 90 s. Finally, to investigate the effect of the different PMA methods, we compared the electrical characteristics of the devices processed with the conventional resistance heating furnace (FGA devices), air ambient microwave irradiation (MWI devices), and devices without-PMA processing. Based on the experimental results of Figs. 2 and 3, we used the optimal MWI process conditions for PMA: 250 W, during 2 min. Fig. 4(a) shows the transfer characteristic curves of the SOI MOSFETs for the various annealing methods: without-PMA, FGA and MWI. It was found that the device without-PMA showed poor electrical characteristics: the highest leakage currents, lowest drain currents, and largest subthreshold slopes. It is interesting to note that the MWI devices have shown superior electrical characteristics in spite of the lower processing temperature (45 °C) and shorter processing times (2 min) in air when compared with the FGA devices processed at 450 °C for 30 min in 5% H2 in N2 forming gas. This result implies that the MWI method is not only applicable to PMA processing, but is in fact a strong candidate to replace the conventional FGA method, as a result of the superior electrical characteristics of the processed devices. The field effect mobility (μFE), threshold voltage (VTH), on-off ratio, subthreshold swing (S), and interface trap density (Dit) at the gate oxide/Si channel are summarized in Table 3, for all three cases (without-PMA, FGA and MWI). Among these parameters, one of the most important in determining the resulting transistor performance is the field effect mobility, because it determines the transistor behavior in terms of drive current and frequency response. The field effect mobility μFE of the measured devices
Fig. 1. Schematic structure of the fabricated SOI MOSFETs.
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
E.-K. Hong, W.-J. Cho / Microelectronics Reliability xxx (2017) xxx–xxx
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Fig. 2. (a) Transfer characteristic curves and (b) output characteristic curves of SOI MOSFETs depending on microwave irradiated power.
Table 1 Field effect mobility (μFE), threshold voltage (VTH), on/off ratio, subthreshold swing (S), interface trap density at channel/insulator (Dit) of the SOI MOSFETs, for various values of MWI power 2 min irradiation. PMA conditions w/o PMA MWI (150 W) MWI (250 W) MWI (600 W) MWI (1000 W) MWI (1400 W) MWI (1800 W)
μFE (cm2/V·s) 82.4 142.4 243.7 257.3 249.5 237.6 242.36
VTH (V)
ION/IOFF 5
−1.54 −0.46 −0.40 −0.22 −0.29 −0.42 −0.40
2.85 × 10 6.74 × 105 3.30 × 106 5.38 × 106 2.14 × 106 1.88 × 106 2.04 × 106
for each PMA variant are 82.4, 184.7, and 243.7 cm2/V·s, for the without-PMA, FGA, and MWI cases, respectively. Therefore, the MWI treated device showed the highest mobility. The field effect mobility can be determined from following equation: μ FE ¼
Lgm ∂ID ; gm ¼ WCox VD ∂VG VD ¼const
ð1Þ
L, W, Cox and gm are the channel length, width, gate oxide capacitance, and transconductance, respectively. As shown in Eq. (1), gm is proportional to the partial derivative of drain current (ID), strongly influencing the μFE of the MOSFETs, given that all measured devices have the same values of W, L, Cox, and VD. Therefore, the enhancement of μFE is mainly attributed to the decrease in channel resistance created by the MWI. It is important to note here that the driving capability of
S (mV/decade)
Dit (cm−2·eV−1)
385 78 73 75 83 78 80
1.4 × 1013 2.8 × 1012 2.7 × 1012 2.7 × 1012 3.0 × 1012 2.8 × 1012 2.9 × 1012
MOSFETs is remarkably improved by MWI, without changing the W/L adjustment and the composition of the oxide materials, and with significantly low processing temperatures and short processing time, when compared with FGA devices. The threshold voltage VTH for each type of annealing were − 1.54, − 0.41, and − 0.40 V for the without-PMA, FGA, and MWI cases, respectively. The threshold voltage (VTH) is defined as the gate voltage necessary to form an inversion channel layer, using the following equation: ID ¼ μ n COX
W ðVG −VTH Þ2 2L
ð2Þ
The on-off ratio is defined as the ratio between the maximum and minimum drain currents in the saturation region of the device operating range. The on-off ratio is affected by the off current and the increase in the gate dielectric current. The on-off ratio values for each of the
Fig. 3. (a) Transfer characteristic curves and (b) output characteristic curves of SOI MOSFETs depending on microwave irradiated time.
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
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Table 2 Field effect mobility (μFE), threshold voltage (VTH), on/off ratio, subthreshold swing (S), interface trap density at channel/insulator (Dit) of the SOI MOSFETs for different irradiation times. The MWI power was fixed at 250 W. PMA conditions
μFE (cm2/V·s)
VTH (V)
ION/IOFF
S (mV/decade)
Dit (cm−2·eV−1)
MWI (30 s) MWI (60 s) MWI (90 s) MWI (120 s)
197.1 257.3 241.2 243.7
−2.61 −1.91 −0.40 −0.40
2.27 × 105 3.98 × 105 2.04 × 106 3.30 × 106
355 294 78 73
1.3 × 1013 1.1 × 1013 2.8 × 1012 2.7 × 1012
Fig. 4. (a) Transfer and (b) output characteristics curves of the SOI MOSFETs, for different annealing method: without-PMA, FGA at 450 °C for 30 min, and MWI at 250 W for 2 min.
measured devices are 2.85 × 105, 1.78 × 106, 3.30 × 106 for the withoutPMA, FGA, and MWI cases, respectively, with the highest value being obtained for the MWI case. The subthreshold swing S is defined as the change in voltage required to increase the drain current by a factor of 10 in the transfer characteristics, it can be obtained using the following equation: S¼
dVGS d logIDS
ð3Þ
The S value is identifiable with the maximum slope value in the transfer characteristic curves. The subthreshold swing S and threshold voltage VTH are very important parameters in the transistor switching behavior, and in reducing power consumption. The subthreshold swing values obtained for the without-PMA, FGA and MWI cases were 385, 77 and 73 mV/decade, respectively, with the lowest swing being obtained for the MWI case. The interface trap density Dit can be extracted from the SOI MOSFETs' S value, using the following equation: Dit ¼
S logðeÞ C −1 i kB T=q q
ð4Þ
q, kB, Ci and T are the electron charge, Boltzmann's constant, gate insulator capacitance per unit area, and absolute temperature, respectively. The magnitude of the extracted Dit for the without-PMA, FGA and MWI cases were 1.4 × 1013, 2.8 × 1012, and 2.7 × 1012 cm−2·eV−1, respectively. This means that the MWI effectively eliminated the defects at the channel/insulator interface [21]. As a summary, we may conclude that, according to results of the measured transfer characteristic curves
and the extracted parameters of the fabricated SOI MOSFETs, the field effect mobility (μFE), on-off ratio, subthreshold swing (S), and interface trap density (Dit) were all improved by MWI processing, in spite of the remarkably low processing temperature (45 °C), and short processing time (2 min) when compared with FGA. Another aspect that requires evaluation is the impact of the longterm use on the degradation of the electrical characteristics of semiconductor devices, such as mobility, swing and VTH shift. We therefore conducted the positive gate bias stress (PBS) and negative gate bias stress (NBS) test to evaluate the effect of the PMA on the stability of the resulting SOI MOSFETs as shown in Fig. 5. The gate bias conditions for the instability test were: ± 2 MV/cm for 1 h, at VD = 1 V. The threshold voltage shifts were measured at (a) 25 °C and (b) 120 °C. Table 4 summarizes the observed variation of the threshold voltage (ΔVTH) for the various PMA conditions and measurement types. In the without-PMA case, a significant degradation was observed, both at room temperature (25 °C) and at high temperature (120 °C). On the contrary, the FGA and MWI treated devices did not deteriorated, neither at room temperature, nor at high temperature. Fig. 6 shows the threshold voltage shift of the SOI MOSFETs induced by hot carrier effect measurement for the three PMA cases: withoutPMA, FGA (450 °C for 30 min), and MWI (250 W for 2 min). The gate bias stress and drain bias stress were fixed at 10 V and 5 V for 1 h, respectively. In the without-PMA case, a considerable degradation was measured, as a result of hot electrons in the channel layer, whereas both the FGA and MWI treated devices did not degrade [22]. In particular, it should be noted that the MWI treated SOI MOSFETs showed good hot carrier immunity, at a level almost comparable to that of the FGA devices.
Table 3 Field effect mobility (μFE), threshold voltage (VTH), on/off ratio, subthreshold swing (S), interface trap density at channel/insulator (Dit) of the SOI MOSFETs for all three cases: withoutPMA, FGA at 450 °C for 30 min, and MWI at 250 W for 2 min. PMA conditions w/o PMA FGA MWI
μFE (cm2/V·s) 82.4 184.7 243.7
VTH (V) −1.54 −0.41 −0.40
ION/IOFF 5
2.85 × 10 1.78 × 106 3.30 × 106
S (mV/decade)
Dit (cm−2·eV−1)
385 77 73
1.4 × 1013 2.8 × 1012 2.7 × 1012
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
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Fig. 5. Threshold voltage shifts of the SOI MOSFETs by instability measurement at (a) 25 °C and (b) 120 °C. An induced gate bias stress of ±2 MV/cm was used, during 1 h.
4. Conclusion In summary, a new approach to enhance the electrical characteristics of Si based devices was proposed, by applying MWI as the essential PMA process in CMOS device fabrication. Both MWI and FGA treated SOI MOSFETs were fabricated, and their electrical characteristics were evaluated and compared. The SOI MOSFETs treated by the low thermal budget MWI process (45 °C for 2 min) exhibited excellent transistor characteristics: lower subthreshold swing and interface trap density, and higher field effect mobility and on-off ratio than FGA treated devices. These results can be ascribed to the direct thermal transfer mechanism of microwave irradiation. Additionally, MWI treated SOI MOSFETs showed good long-term stability and hot carrier immunity,
Table 4 ΔVTH of the SOI MOSFFTs for different PMA conditions. The gate bias stress test was performed with 2 MV/cm for 1 h. PMA conditions
NBS (25 °C)
PBS (25 °C)
NBTS (120 °C)
PBTS (120 °C)
w/o PMA FGA MWI
−0.12 V 0V 0V
0.16 V 0V 0V
−0.6 V 0V 0V
0.73 V 0V 0V
Fig. 6. Threshold voltage shift of SOI MOSFETs by hot carrier effect measurement (a) w/o PMA, (b) forming gas annealing at 450 °C for 30 min, (c) microwave irradiation 250 W for 2 min. The gate bias stress and drain bias stress were fixed at 10 V, 5 V for 1 h, respectively.
Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070
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at a level which is almost comparable to that of FGA devices. Our results indicate that the MWI method is applicable as a next-generation PMA process, replacing the conventional FGA method, because it exhibits higher levels of cost effectiveness and productivity for silicon-based device. Furthermore, the MWI based PMA process constitutes also a promising technique for transparent and flexible electronic display applications. Acknowledgments This study was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Science and Technology (No. 2016R1A2B4008754). References [1] R.R. Schaller, Technological Innovation in the Semiconductor Industry: A Case Study of the International Technology Roadmap for Semiconductors (ITRS)(Diss.) George Mason University, 2004. [2] M. Ieong, B. Doris, J. Kedzierski, K. Rim, M. Yang, Silicon device scaling to the sub-10nm regime, Science 306 (2004) 2057. [3] M.J. Deen, Z.X. Yan, DIBL in short-channel NMOS devices at 77 K, IEEE Trans. Electron Dev. 39 (1992) 908. [4] K.K. Young, Short-channel effect in fully depleted SOI MOSFETs, IEEE Trans. Electron Dev. 36 (1989) 399. [5] A. Pethe, et al., Device Innovation and Material Challenges at the Limits of CMOS Technology, IEDM Tech. Dig. 135, 2005 619. [6] N. Mazure, F. Dayan, D. Roux, E. Berra, C.B. Horn, J. Poussegur, 3 Hypoxia signaling impact on tumor metabolism, cell survival & cell death, Radiother. Oncol. 78 (2006) S1. [7] S.B. Samavedam, L.B. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J. Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H.H. Tseng, P.J. Tobin, D.C. Gilmer, C. Hobbs, W.J. Taylor, J.M. Grant, R.I. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalam, M. Sadd, B.-Y. Nguyen, B. White, Dualmetal Gate CMOS with HfOz Gate Dielectric, IEDM Tech. Dig. 433, 2002. [8] H.-S.P. Wong, D.J. Frank, P.M. Solomon, Device Design Considerations for Doublegate, Ground-plane, and Single-gated Ultra-thin SO1 MOSFET's at the 25 nm Chiannel Length Generation, IEDM Tech. Dig. 407, 1998.
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Please cite this article as: E.-K. Hong, W.-J. Cho, Effect of microwave annealing on SOI MOSFETs: Post-metal annealing with low thermal budget, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.07.070