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Effect of series resistance on the performance of high resistivity silicon Schottky diode
Applied Surface Science 218 (2003) 336–342
Effect of series resistance on the performance of high resistivity silicon Schottky diode A. Keffousa,*, M. Siadb, S. Mammab, Y. Belkacema, C. Lakhdar Chaouchb, H. Menaria, A. Dahmania, W. Cherguia a
Unit de Dveloppement de la Technologie du Silicium, Bd Frantz Fanon, B.P. 399 Alger-Gare, Algeria b Centre de Recherche Nuclaire d’Alger 02, Bd Frantz Fanon, B.P. 399 Alger-Gare, Algeria Received 30 March 2003; received in revised form 26 April 2003; accepted 26 April 2003
Abstract The series resistance is an important parameter on the electrical characteristics of silicon Schottky barrier diodes. This parameter is influenced by the presence of the interface layer between the metal and the semiconductor and leads to non-ideal forward bias current–voltage (IV). The aim of this work is to investigate the effect of series resistance on the non-ideal silicon Schottky diode (SSD) in our process fabrication. Two types of diodes: Al/n-Si and Au/n-Si, with high resistivity silicon bulk have been prepared. The parameter Rs, the ideality factor n and the barrier height fBo are determined by performing different plots from the forward IV. # 2003 Elsevier Science B.V. All rights reserved. Keywords: Schottky barrier; Series resistance; Ohmic contact; Silicon
1. Introduction The metal–semiconductor (M–S) contact system has drawn considerable interest because of its large impact on the formation and behaviour of Schottky barrier. The parameters which characterise such a contact depend on the method used. It is well known that, unless specially fabricated, a silicon Schottky diode (SSD) posses a thin interfacial oxide layer between the metal and the semiconductor. The semiconductor is covered with thin oxide layer, either during sample preparation (chemical treatment), metal evaporation, when carried out in conventional *
Corresponding author. Tel.: þ213-2143-4444 (P-235); fax: þ213-2143-3511. E-mail address: [email protected] (A. Keffous).
vacuum system, and thermal annealing. This interface oxide layer may have a strong influence on the diodes characteristics and leads to increase the series resistance of the diode. This is clearly observed in the nonlinearity regime of the forward IV curve. The existence of a thin interfacial layer (oxide layer) between the metal and the semiconductor play an important role in the determination of the Schottky barrier height (fBo ). The first studies on the interface layer in Schottky diodes were made by Cowley and Sze [1], who obtained their estimates from an analysis of barrier heights with different metallization as a function of the metal work function. Card and Rhoderick [2] examined the effects of the interface layer on the ideality factor of the forward bias IV characteristics. Tseng and Wu [3] analysed the effect of the presence of an interfacial layer on the behaviour
0169-4332/$ – see front matter # 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S0169-4332(03)00642-1
A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
of Schottky contacts. Independent of their work, Horvath [4] extended the analysis of Card and Rhoderick to the reverse IV characteristics. He showed that from the forward and reverse IV characteristics, both the interface state energy distribution and the interface layer thickness may be evaluated. In this work, we investigate the effect of the interface oxide layer in the contact Au/n-Si and Al/n-Si, through the calculation of series resistance, by using the forward bias current–voltage (IV) characteristics.
2. Experimental procedure The Schottky diodes were fabricated using n-type FZ silicon wafers, with (1 1 1) orientation, 2 kO cm resistivity and 300 mm of thickness. The samples, cut into slices of 12 mm diameter, were lapped with alumina powder of grain size of 5–3 mm and thoroughly cleaned with an ultra-sonic washer to remove organic contaminants. The surface of the samples were chemically cleaned using a mixture of acids (CP4: 1HF:2HNO3 :1CH3 In this work, we consider two types of diodes, that one notes: Al/n-Si/AuSb and Au/n-Si/Li. We have fabricated 10 diodes for each type: In the first type, a low resistivity ohmic contact is formed by evaporation of an alloy film of AuSb (99%, 1%) followed by an annealing at the eutectic temperature of the Au–Si system (370 8C/30 min). The heavily doped layer formed with silicon (nþ n) avoids the extension of the space charge until the metallic contact and limits the injection of carriers in this region. This is beneficial for reducing the reverse current. In the second one, the ohmic contact is obtained by deposition of high purity lithium, followed by a diffusion of lithium at 350 8C/2 min, in a secondary vacuum system. After formation of the ohmic contacts, the slices are dipped for few seconds into concentrated HF (40%), followed by a rinse in deionised water. This operation is repeated with concentrated HNO3 (69%) for 30 min and a drying in nitrogen gas. We have measured, by ˚ for the oxide ellipsometry, a thickness around 30 A layer. Before this treatment, the ohmic contact was protected by picein, which is removed by thrichloroethane and acetone at the end of the procedure. To minimise
337
the surface contamination, the slices are immediately placed into deposition chamber to evaporate a film of aluminum (99.99% purity) for the diode n-Si/AuSb and Au for the diodes n-Si/Li, with 5 mm of diameter for both diodes [5].
3. Results and discussions The diode parameters are determined from the forward current–voltage (IV) characteristics, which is usually described within the thermionic emission theory [6–8]: qV I ¼ Io exp (1) nkT where the saturation current Io is expressed as: qfBo Io ¼ aA T 2 exp kT
(2)
where q is the electron charge, V the applied voltage, A the effective Richardson constant and equals to 112 A cm2 K2 for n-type Si [6,9], a the effective diode area, T the absolute temperature, k the Boltzmann constant, n the ideality factor of a Schottky barrier diode, and fBo is the zero bias barrier height. For values of V greater than nkT=q, the ideality factor from Eq. (1) can be written as: n¼
q DV kT D ln I
(3)
The experimental semi-log forward bias characteristics of the Schottky diodes studied are shown in Figs. 1 and 2. We have chosen two diodes for each type and compared the results obtained by different methods. The effect of the series resistance is usually modelled with series combination of a diode and a resistor Rs . The voltage Vd across the diode can be expressed in terms of the total voltage drop V across the diode and the resistance Rs . Thus, Vd ¼ V IRs and the Eq. (1) can be expressed as: qðV IRs Þ I ¼ Io exp (4) nkT Several methods to extract the series resistance Rs of Schottky diode have been suggested [10–12]. In our case, we have applied the methods developed by Cheung and Cheung [12] and Lien et al. [13].
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A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
Fig. 1. Experimental forward current characteristics of the diodes Al/n-Si.
The Cheung’s method is achieved by using the functions:
where HðIÞ can be written as:
dV nkT ¼ IRs dðln IÞ q nkT I HðIÞ ¼ V ln q aA T 2
Eq. (5) should give a straight line for the data of the downward curvature region of the forward bias IV characteristics. Thus, the slope and y-axis intercept of a plot of dV/d(lnðIÞ) versus I will give Rs and nkT=q, respectively.
(5) (6)
HðIÞ ¼ IRs þ nfBo
Fig. 2. Experimental forward current characteristics of the diodes Au/n-Si.
(7)
A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
339
Fig. 3. Experimental dV/d(lnðIÞ) vs. I plots for the diodes Al/n-Si.
The plots associated with these functions are given in Figs. 3 and 4. Using the n value determined from Eq. (5) and the data of the downward curvature region in Eq. (6); plot of HðIÞ versus I according to Eq. (7) (Figs. 5 and 6) will also give a straight line with the y-axis intercept equal to nfBo . The slope of this plot also provides a second determination of Rs which
can be used to check the consistency of Cheung’s approach. The values of Rs obtained are given in Table 1. From HðIÞ–I plots, the values of Rs are approximately equal to those obtained from ðdV=d ln IÞ I plots. This case shows the consistency of the Cheung’s approach. Before proceeding to discuss the barrier
Fig. 4. Experimental dV/d(lnðIÞ) vs. I plots for the diodes Au/n-Si.
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A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
Fig. 5. Experimental HðIÞ vs. I plots for the diodes Al/n-Si.
height shift we must consider some properties of the interfacial layer between the metal and the semiconductor. It is more important to know how the barrier height varies with the applied voltage in the forward bias condition. Because of the potential drop across the interfacial layer, the zero bias barrier height is lower than is expected in an ideal diode, and similarly the potential across the interfacial layer varies with
bias because of the electrical field present in the semiconductor and the change in the interface. The second method [13] is based on plotting several functions defined by: V kT I GðV; IÞ ¼ ln (8) g q aA T 2 where g is an arbitrary parameter, greater than n.
Fig. 6. Experimental HðIÞ vs. I plots for the diodes Au/n-Si.
A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
341
Table 1 Values of series resistance for different diode (Au/n-Si, Al/n-Si) obtained by Lien et al.’s method and Cheung’s method. Sample
nðIVÞ qfBo (eV) (IV) Rs (kO) Lien et al. method Rs (kO) Cheung method dV/d(lnðIÞ I) Rs (kO) Cheung method HðIÞ I
Bds3:Al/n-Si
Bds6:Al/n-Si
Phd4:Au/n-Si
Phd6:Au/n-Si
1.182 0.802 20.72 20.47 18.29
1.310 0.798 29.08 30.37 29.76
1.120 0.806 18.98 14.77 14.53
1.062 0.827 1.08 0.94 1.06
Plots of Gg ðV; IÞ versus I show a minimum for Iog ¼ kT=qRs ðg nÞ. The plot of Iog versus g is a straight line whose slope leads to the value of the series resistance Rs . A linear regression can be performed to calculate Rs which raises the accuracy of the results. The values obtained for Rs are given in Table 1 and compared to those obtained by the Cheung’s method. From the values of Gg ðVo ; Io Þ and the corresponding voltage Vo at the minimum, the barrier height can be calculated. The diode Phd6 has an almost ideal IV characteristic due to the ideality factor value of 1.062, the values of the others diodes show that the device is a metal-interface-silicon (MIS) configuration. In view of these results, one notes that when the ideality factor n 1, Rs is in the order of the bulk resistivity, but when n > 1, the series resistance takes values 20 in 30 magnitude order of resistivity. Turut and co-workers [14] have obtained a value of Rs 20 O when they used a bulk resistivity of 5 O cm in Au/n-Si Shottky diodes. We can conclude a correlation between the interface layer in the contact metal–silicon and the series resistance effect. The oxide interface layer reduces the barrier height and consequently the series resistance increases. Table 2 Electrical parameters of Au/n-Si and Al/n-Si diodes Sample
Bds3:Al/n-Si Bds6:Al/n-Si Phd4:Au/n-Si Phd6:Au/n-Si
IV method
Lien et al. method
Cheung method
n
qfBo
n
qfBo
n
qfBo
1.182 1.310 1.120 1.062
0.802 0.798 0.806 0.827
1.268 1.414 1.119 1.510
0.850 0.860 0.798 0.806
– – – –
0.992 0.805 0.886 1.022
The values of n and fBo calculated from the linear region of the (IV) curve are slightly different than the calculated ones, from the Cheung and Lien methods (Table 2).
4. Conclusion It is well known that the downward concave curvature of the forward bias IV plots at sufficiently large voltages is caused by the presence of the effect of Rs , apart from the interface states which are in equilibrium with the semiconductor. Therefore, the concavity of the forward bias IV characteristics increases with increasing series resistance value. Thus, as can be seen from the above results, in order to make an accurate determination of diode’s parameters and interface state density distribution from the forward bias IV characteristics, the series resistance value should be taken into account. References [1] A.M. Cowley, S.M. Sze, J. Appl. Phys. 36 (1965) 3212. [2] J.C. Card, E.H. Rhoderick, J. Phys. D 4 (1971) 1589. [3] H.H. Tseng, C.Y. Wu, Solid State Electron. 30 (1987) 383. [4] Z.S. Horvath, J. Appl. Phys. 63 (1988) 976. [5] H. Rahab, A. Keffous, H. Menari, W. Chergui, M. Siad, N. Boussaa, Nucl. Instrum. Meth. Phys. Res. A 459 (2001) 200. [6] S.M. Sze, Physics of Semiconductor Devices, 2nd Edition, Wiley, New York, 1981. [7] E.H. Rhoderick, R.H. Williams, Metal–Semiconductor Contacts, Clarendon, Oxford 1998. [8] P. Cova, A. Singh, A. Medina, R.A. Masut, Solid State Electron. 42 (1998) 477. [9] J.H. Warner, U. Rau, in: J.F. Luy, et al. (Eds.), Springer Series in Electronics and Photonics, vol. 32, 1994.
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A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
[10] H. Norde, J. Appl. Phys. 50 (1979) 5052. [11] K.E. Bohlin, J. Appl. Phys. 60 (1986) 3. [12] S.K. Cheung, N.W. Cheung, Appl. Phys. Lett. 49 (1986) 85.
[13] C.-D. Lien, F.C.T. So, M.-A. Nicolet, IEEE Trans. Electron Devices ED-31 (1984) 1502. [14] E. Ayyildiz, C. Temirci, B. Bati, A. Turut, Int. J. Electron. 88 (6) (2001) 625.
Effect of series resistance on the performance of high resistivity silicon Schottky diode A. Keffousa,*, M. Siadb, S. Mammab, Y. Belkacema, C. Lakhdar Chaouchb, H. Menaria, A. Dahmania, W. Cherguia a
Unit de Dveloppement de la Technologie du Silicium, Bd Frantz Fanon, B.P. 399 Alger-Gare, Algeria b Centre de Recherche Nuclaire d’Alger 02, Bd Frantz Fanon, B.P. 399 Alger-Gare, Algeria Received 30 March 2003; received in revised form 26 April 2003; accepted 26 April 2003
Abstract The series resistance is an important parameter on the electrical characteristics of silicon Schottky barrier diodes. This parameter is influenced by the presence of the interface layer between the metal and the semiconductor and leads to non-ideal forward bias current–voltage (IV). The aim of this work is to investigate the effect of series resistance on the non-ideal silicon Schottky diode (SSD) in our process fabrication. Two types of diodes: Al/n-Si and Au/n-Si, with high resistivity silicon bulk have been prepared. The parameter Rs, the ideality factor n and the barrier height fBo are determined by performing different plots from the forward IV. # 2003 Elsevier Science B.V. All rights reserved. Keywords: Schottky barrier; Series resistance; Ohmic contact; Silicon
1. Introduction The metal–semiconductor (M–S) contact system has drawn considerable interest because of its large impact on the formation and behaviour of Schottky barrier. The parameters which characterise such a contact depend on the method used. It is well known that, unless specially fabricated, a silicon Schottky diode (SSD) posses a thin interfacial oxide layer between the metal and the semiconductor. The semiconductor is covered with thin oxide layer, either during sample preparation (chemical treatment), metal evaporation, when carried out in conventional *
Corresponding author. Tel.: þ213-2143-4444 (P-235); fax: þ213-2143-3511. E-mail address: [email protected] (A. Keffous).
vacuum system, and thermal annealing. This interface oxide layer may have a strong influence on the diodes characteristics and leads to increase the series resistance of the diode. This is clearly observed in the nonlinearity regime of the forward IV curve. The existence of a thin interfacial layer (oxide layer) between the metal and the semiconductor play an important role in the determination of the Schottky barrier height (fBo ). The first studies on the interface layer in Schottky diodes were made by Cowley and Sze [1], who obtained their estimates from an analysis of barrier heights with different metallization as a function of the metal work function. Card and Rhoderick [2] examined the effects of the interface layer on the ideality factor of the forward bias IV characteristics. Tseng and Wu [3] analysed the effect of the presence of an interfacial layer on the behaviour
0169-4332/$ – see front matter # 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S0169-4332(03)00642-1
A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
of Schottky contacts. Independent of their work, Horvath [4] extended the analysis of Card and Rhoderick to the reverse IV characteristics. He showed that from the forward and reverse IV characteristics, both the interface state energy distribution and the interface layer thickness may be evaluated. In this work, we investigate the effect of the interface oxide layer in the contact Au/n-Si and Al/n-Si, through the calculation of series resistance, by using the forward bias current–voltage (IV) characteristics.
2. Experimental procedure The Schottky diodes were fabricated using n-type FZ silicon wafers, with (1 1 1) orientation, 2 kO cm resistivity and 300 mm of thickness. The samples, cut into slices of 12 mm diameter, were lapped with alumina powder of grain size of 5–3 mm and thoroughly cleaned with an ultra-sonic washer to remove organic contaminants. The surface of the samples were chemically cleaned using a mixture of acids (CP4: 1HF:2HNO3 :1CH3 In this work, we consider two types of diodes, that one notes: Al/n-Si/AuSb and Au/n-Si/Li. We have fabricated 10 diodes for each type: In the first type, a low resistivity ohmic contact is formed by evaporation of an alloy film of AuSb (99%, 1%) followed by an annealing at the eutectic temperature of the Au–Si system (370 8C/30 min). The heavily doped layer formed with silicon (nþ n) avoids the extension of the space charge until the metallic contact and limits the injection of carriers in this region. This is beneficial for reducing the reverse current. In the second one, the ohmic contact is obtained by deposition of high purity lithium, followed by a diffusion of lithium at 350 8C/2 min, in a secondary vacuum system. After formation of the ohmic contacts, the slices are dipped for few seconds into concentrated HF (40%), followed by a rinse in deionised water. This operation is repeated with concentrated HNO3 (69%) for 30 min and a drying in nitrogen gas. We have measured, by ˚ for the oxide ellipsometry, a thickness around 30 A layer. Before this treatment, the ohmic contact was protected by picein, which is removed by thrichloroethane and acetone at the end of the procedure. To minimise
337
the surface contamination, the slices are immediately placed into deposition chamber to evaporate a film of aluminum (99.99% purity) for the diode n-Si/AuSb and Au for the diodes n-Si/Li, with 5 mm of diameter for both diodes [5].
3. Results and discussions The diode parameters are determined from the forward current–voltage (IV) characteristics, which is usually described within the thermionic emission theory [6–8]: qV I ¼ Io exp (1) nkT where the saturation current Io is expressed as: qfBo Io ¼ aA T 2 exp kT
(2)
where q is the electron charge, V the applied voltage, A the effective Richardson constant and equals to 112 A cm2 K2 for n-type Si [6,9], a the effective diode area, T the absolute temperature, k the Boltzmann constant, n the ideality factor of a Schottky barrier diode, and fBo is the zero bias barrier height. For values of V greater than nkT=q, the ideality factor from Eq. (1) can be written as: n¼
q DV kT D ln I
(3)
The experimental semi-log forward bias characteristics of the Schottky diodes studied are shown in Figs. 1 and 2. We have chosen two diodes for each type and compared the results obtained by different methods. The effect of the series resistance is usually modelled with series combination of a diode and a resistor Rs . The voltage Vd across the diode can be expressed in terms of the total voltage drop V across the diode and the resistance Rs . Thus, Vd ¼ V IRs and the Eq. (1) can be expressed as: qðV IRs Þ I ¼ Io exp (4) nkT Several methods to extract the series resistance Rs of Schottky diode have been suggested [10–12]. In our case, we have applied the methods developed by Cheung and Cheung [12] and Lien et al. [13].
338
A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
Fig. 1. Experimental forward current characteristics of the diodes Al/n-Si.
The Cheung’s method is achieved by using the functions:
where HðIÞ can be written as:
dV nkT ¼ IRs dðln IÞ q nkT I HðIÞ ¼ V ln q aA T 2
Eq. (5) should give a straight line for the data of the downward curvature region of the forward bias IV characteristics. Thus, the slope and y-axis intercept of a plot of dV/d(lnðIÞ) versus I will give Rs and nkT=q, respectively.
(5) (6)
HðIÞ ¼ IRs þ nfBo
Fig. 2. Experimental forward current characteristics of the diodes Au/n-Si.
(7)
A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
339
Fig. 3. Experimental dV/d(lnðIÞ) vs. I plots for the diodes Al/n-Si.
The plots associated with these functions are given in Figs. 3 and 4. Using the n value determined from Eq. (5) and the data of the downward curvature region in Eq. (6); plot of HðIÞ versus I according to Eq. (7) (Figs. 5 and 6) will also give a straight line with the y-axis intercept equal to nfBo . The slope of this plot also provides a second determination of Rs which
can be used to check the consistency of Cheung’s approach. The values of Rs obtained are given in Table 1. From HðIÞ–I plots, the values of Rs are approximately equal to those obtained from ðdV=d ln IÞ I plots. This case shows the consistency of the Cheung’s approach. Before proceeding to discuss the barrier
Fig. 4. Experimental dV/d(lnðIÞ) vs. I plots for the diodes Au/n-Si.
340
A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
Fig. 5. Experimental HðIÞ vs. I plots for the diodes Al/n-Si.
height shift we must consider some properties of the interfacial layer between the metal and the semiconductor. It is more important to know how the barrier height varies with the applied voltage in the forward bias condition. Because of the potential drop across the interfacial layer, the zero bias barrier height is lower than is expected in an ideal diode, and similarly the potential across the interfacial layer varies with
bias because of the electrical field present in the semiconductor and the change in the interface. The second method [13] is based on plotting several functions defined by: V kT I GðV; IÞ ¼ ln (8) g q aA T 2 where g is an arbitrary parameter, greater than n.
Fig. 6. Experimental HðIÞ vs. I plots for the diodes Au/n-Si.
A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
341
Table 1 Values of series resistance for different diode (Au/n-Si, Al/n-Si) obtained by Lien et al.’s method and Cheung’s method. Sample
nðIVÞ qfBo (eV) (IV) Rs (kO) Lien et al. method Rs (kO) Cheung method dV/d(lnðIÞ I) Rs (kO) Cheung method HðIÞ I
Bds3:Al/n-Si
Bds6:Al/n-Si
Phd4:Au/n-Si
Phd6:Au/n-Si
1.182 0.802 20.72 20.47 18.29
1.310 0.798 29.08 30.37 29.76
1.120 0.806 18.98 14.77 14.53
1.062 0.827 1.08 0.94 1.06
Plots of Gg ðV; IÞ versus I show a minimum for Iog ¼ kT=qRs ðg nÞ. The plot of Iog versus g is a straight line whose slope leads to the value of the series resistance Rs . A linear regression can be performed to calculate Rs which raises the accuracy of the results. The values obtained for Rs are given in Table 1 and compared to those obtained by the Cheung’s method. From the values of Gg ðVo ; Io Þ and the corresponding voltage Vo at the minimum, the barrier height can be calculated. The diode Phd6 has an almost ideal IV characteristic due to the ideality factor value of 1.062, the values of the others diodes show that the device is a metal-interface-silicon (MIS) configuration. In view of these results, one notes that when the ideality factor n 1, Rs is in the order of the bulk resistivity, but when n > 1, the series resistance takes values 20 in 30 magnitude order of resistivity. Turut and co-workers [14] have obtained a value of Rs 20 O when they used a bulk resistivity of 5 O cm in Au/n-Si Shottky diodes. We can conclude a correlation between the interface layer in the contact metal–silicon and the series resistance effect. The oxide interface layer reduces the barrier height and consequently the series resistance increases. Table 2 Electrical parameters of Au/n-Si and Al/n-Si diodes Sample
Bds3:Al/n-Si Bds6:Al/n-Si Phd4:Au/n-Si Phd6:Au/n-Si
IV method
Lien et al. method
Cheung method
n
qfBo
n
qfBo
n
qfBo
1.182 1.310 1.120 1.062
0.802 0.798 0.806 0.827
1.268 1.414 1.119 1.510
0.850 0.860 0.798 0.806
– – – –
0.992 0.805 0.886 1.022
The values of n and fBo calculated from the linear region of the (IV) curve are slightly different than the calculated ones, from the Cheung and Lien methods (Table 2).
4. Conclusion It is well known that the downward concave curvature of the forward bias IV plots at sufficiently large voltages is caused by the presence of the effect of Rs , apart from the interface states which are in equilibrium with the semiconductor. Therefore, the concavity of the forward bias IV characteristics increases with increasing series resistance value. Thus, as can be seen from the above results, in order to make an accurate determination of diode’s parameters and interface state density distribution from the forward bias IV characteristics, the series resistance value should be taken into account. References [1] A.M. Cowley, S.M. Sze, J. Appl. Phys. 36 (1965) 3212. [2] J.C. Card, E.H. Rhoderick, J. Phys. D 4 (1971) 1589. [3] H.H. Tseng, C.Y. Wu, Solid State Electron. 30 (1987) 383. [4] Z.S. Horvath, J. Appl. Phys. 63 (1988) 976. [5] H. Rahab, A. Keffous, H. Menari, W. Chergui, M. Siad, N. Boussaa, Nucl. Instrum. Meth. Phys. Res. A 459 (2001) 200. [6] S.M. Sze, Physics of Semiconductor Devices, 2nd Edition, Wiley, New York, 1981. [7] E.H. Rhoderick, R.H. Williams, Metal–Semiconductor Contacts, Clarendon, Oxford 1998. [8] P. Cova, A. Singh, A. Medina, R.A. Masut, Solid State Electron. 42 (1998) 477. [9] J.H. Warner, U. Rau, in: J.F. Luy, et al. (Eds.), Springer Series in Electronics and Photonics, vol. 32, 1994.
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A. Keffous et al. / Applied Surface Science 218 (2003) 336–342
[10] H. Norde, J. Appl. Phys. 50 (1979) 5052. [11] K.E. Bohlin, J. Appl. Phys. 60 (1986) 3. [12] S.K. Cheung, N.W. Cheung, Appl. Phys. Lett. 49 (1986) 85.
[13] C.-D. Lien, F.C.T. So, M.-A. Nicolet, IEEE Trans. Electron Devices ED-31 (1984) 1502. [14] E. Ayyildiz, C. Temirci, B. Bati, A. Turut, Int. J. Electron. 88 (6) (2001) 625.