Effects of device aging on microelectronics radiation response and reliability

Microelectronics Reliability 47 (2007) 1075–1085 www.elsevier.com/locate/microrel

Introductory Invited Paper

Effects of device aging on microelectronics radiation response and reliability q D.M. Fleetwood a

a,*

, M.P. Rodgers a, L. Tsetseris b, X.J. Zhou a, I. Batyrev b, S. Wang b, R.D. Schrimpf a, S.T. Pantelides b

Electrical Engineering and Computer Science Department, VU Station B #351824, 2301 Vanderbilt Place, Nashville, TN 37235, USA b Physics Department, VU Station B #351807, 2301 Vanderbilt Place, Nashville, TN 37235, USA Received 16 February 2006 Available online 21 August 2006

Abstract We review recent work that shows that, for several kinds of devices built by several different manufacturers, MOS and bipolar device radiation response can change significantly with pre-irradiation elevated temperature stress and/or with aging time after device fabrication or packaging. The primary effects that have been observed are related to changes in interface-trap charge buildup, but some effects are also noted for charge trapped in the oxide. On the basis of a wide array of experimental data and first-principles calculations, these changes are attributed to the motion and reactions of hydrogenous species, e.g., protons and water. Similar reactions with hydrogen can also affect the reliability of MOS devices and integrated circuits, as illustrated here for the case of negative bias-temperature instability for high-j alternative gate dielectrics. Heating the device accelerates some kinds of aging effects, but reverses the effects of others. These observations are consistent with a dual role for hydrogen in improving or degrading device performance, depending on its particular incorporation in the device and subsequent motion and reactions. These results emphasize that measurements used to provide estimates of MOS radiation response and long-term reliability can vary significantly with time. In some cases, typical margins built into radiation response and reliability tests may be inadequate to account for aging-related changes in device performance.  2006 Elsevier Ltd. All rights reserved.

1. Introduction It is usually assumed at least implicitly that the ionizing radiation response and long-term reliability of microelectronic devices and integrated circuits (ICs) do not change significantly during the time between when devices are manufactured and/or packaged and when they are tested or used. This assumption is based upon the rational (but incorrect in many cases) belief that the defects and impurities that affect radiation response and reliability are dominated by the higher temperatures (400–1000 C) of device processing, and not affected significantly by the lower temq

An earlier version of this paper was published in the Proceedings of the 25th International Conference on Microelectronics, Belgrade, 14–17 May 2006, pp. 89–96. * Corresponding author. Fax: +1 615 343 6702. E-mail address: dan.fl[email protected] (D.M. Fleetwood). 0026-2714/$ - see front matter  2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2006.06.009

peratures of packaging and storage (0–300 C). After packaging, the highest temperatures to which devices typically are exposed is 125–150 C; the higher temperatures in this range typically are encountered if devices are burned-in before being incorporated into systems of interest. In this paper, in Section 2 we review evidence that shows that, for many types of devices, the radiation response of MOS and bipolar devices can be quite sensitive to postprocessing or post-packaging elevated temperature stress. In Section 3 it is shown that some types of devices exhibit significant changes in irradiation and/or post-irradiation annealing response with long-term storage. These changes tend to be larger if the devices are stored in a non-hermetic environment, but significant changes are also observed for some kinds of fully processed and passivated devices that are packaged and stored hermetically. These effects are attributed primarily to the effects of hydrogenous species that are either incorporated into the chip materials during

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processing, or absorbed during device storage. The energetics of H2O in SiO2 are discussed in Section 4. Because similar kinds of defects affect MOS radiation response and long-term reliability, these results suggest that estimates of MOS reliability also may depend strongly on the timetemperature history of a device after fabrication and/or packaging, as illustrated for the case of bias-temperature instability in Section 5. More complex interactions of hydrogen with dangling bonds and interface-trap precursors are discussed in Section 6, as are the combined effects of irradiation and bias-temperature stress, for high-j alternative dielectrics to SiO2. Finally, Section 7 briefly summarizes other types of microelectronic devices and materials sensitive to these kinds of effects, illustrating the generality and significance of these phenomena in a broad range of applications.

ages. Effects of burn-in on radiation response also have been reported for power MOSFETs [3]. Thus, manufacturing and packaging processes can play significant roles in determining the burn-in sensitivity of several types of MOS devices built by different manufacturers. The effects of electric field (Fig. 2) and temperature (Fig. 3) during elevated-temperature reliability screens were assessed by Shaneyfelt et al. for devices built in a 2-lm technology at Sandia National Laboratories [4]. Based on the devices of Fig. 3, an effective activation energy of 0.38 eV was estimated for the observed increase in postirradiation field-oxide leakage for this technology. This activation energy is similar to that of the diffusion of molecular hydrogen in SiO2 [4]. Consistent with the possibility that hydrogen diffusion might be associated with the changes in device radiation response, Shaneyfelt et al. also

Fig. 1. Threshold-voltage shifts due to interface traps and oxide trap charge for 2 · 16 lm nMOS transistors with 32 nm oxides fabricated at Sandia National Laboratories. The devices were irradiated with 10-keV Xrays at a dose rate of 167 rad(SiO2)/s and a gate bias of 5 V (after [1]).

Fig. 2. Current as a function of gate voltage and pre-irradiation elevatedtemperature stress bias (applied for one week at 150 C) for field oxide transistors with 800 nm oxides fabricated in a 2 lm technology at Sandia National Laboratories. The devices were irradiated with 10-keV X-rays at a dose rate of 1670 rad(SiO2)/s and 5 V bias (after [4]).

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In 1994, Shaneyfelt et al. showed that burn-in can significantly affect the ionizing radiation response of MOS devices [1]. Changes in radiation response were observed in gate and field oxides of devices manufactured and packaged at Sandia National Laboratories, with a reduction in interface (but not oxide) traps observed in burned-in devices, as illustrated in Fig. 1. This leads to a more negative threshold voltage shift for the burned-in devices, and therefore an increase in post-irradiation leakage current for burned-in ICs, compared to those that were not burned in. No significant changes were observed in pre-irradiation characteristics of the devices [1]. The results of Shaneyfelt et al. were confirmed and extended by Clark and co-workers using devices manufactured by National Semiconductor [2]. The post-irradiation leakage currents for the National parts in [2] were higher for burned-in devices than nonburned-in devices, especially for devices in plastic pack-

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2. Pre-irradiation elevated temperature stress effects

Fig. 3. Current as a function of gate voltage and pre-irradiation elevated temperature stress (one week at 5 V) for field oxide transistors with 800 nm oxides fabricated in a 2 lm technology at Sandia National Laboratories. The devices were irradiated with 10-keV X-rays at a dose rate of 1670 rad(SiO2)/s and a 5 V gate bias. The dotted line indicates the current at the device threshold voltage (after [4]).

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found that the changes in MOS radiation response observed in these field oxides were independent of bias, at least for the range (5 V to 20 V) examined in Fig. 2 [4]. These results were extended to full static random access memories (SRAMs) by Shaneyfelt et al. in [5], which evaluated the effects of pre-irradiation elevated temperature stress (PETS) on devices manufactured by Paradigm and by Cypress Semiconductor. Burn-in or other PETS treatments were observed to affect both the leakage currents

and the doses to functional failure for these technologies. Failure doses dropped by 40% for Paradigm SRAMs that were burned-in for 802 h (Fig. 4), as compared to failure doses of devices that received no burn-in. Shaneyfelt et al. hypothesized that the mechanisms responsible for changes in radiation response with burn-in were similar to effects that might occur during long-term use or storage, and proposed a test methodology (Fig. 5) that attempts to use high-temperature bakes to identify parts that may show significant aging effects [5]. This assumption is most directly applicable for Arrhenius processes with single, effective activation energies. However, no aging data were presented in [5], and later work (below) shows that aging effects in microelectronics can be more complex than this test sequence can emulate. Bipolar linear microcircuits were also identified as sensitive to PETS by Pease et al. for LT1014 and LM111 devices [6]. It was suggested that a reduction in interface-trap density and an increase in oxide-trap charge density were responsible for the effects observed in these devices. An extreme sensitivity to PETS effects was observed by Shaneyfelt et al. in linear bipolar ICs that also exhibited enhanced low-dose-rate sensitivity (ELDRS) associated with enhanced interface-trap formation during low-dose-rate irradiation, relative to higher-rate irradiation [7]. Remarkably, baking devices at modest temperatures (100–200 C) was found to almost entirely remove ELDRS for LM111

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Fig. 4. Dose to first functional failure versus pre-irradiation elevatedtemperature stress time for 3.3 V Paradigm static random access memories (after [5]).

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Fig. 5. Proposed test method to identify devices potentially sensitive to aging effects (after [5]).

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3. Aging effects in MOS devices

Fig. 6. Input bias current as a function of dose and pre-irradiation elevated temperature stress (PETS) time for LM111 devices from National Semiconductor irradiated at 0 V at a dose rate of 0.1 rad(SiO2)/s. Increasing the duration of the PETS treatment reduces the enhancement of damage at low dose rate in these devices (after [7]).

The first study of the effects of long-term storage on MOS ionizing radiation response was performed by Karmarkar et al. in 2001 [10]. In this work the measured radiation response of MOS capacitors in 2001 was compared to the radiation response of capacitors from the same wafer that had been irradiated in 1986 [11]. These devices had no passivating overlayers, and were stored in room ambient conditions. For Al-gate devices, a significant decrease was observed after aging in the rate of buildup of radiation-induced oxide-trap charge (Fig. 8), with much less change seen for devices with poly-crystalline Si gates in [10]. Baking the devices of Fig. 8 at 205 C for 18 h restored the original radiation response (Fig. 9). These effects were attributed to moisture absorption in the SiO2 during storage, leading to passivation of oxide-trap precursors; this process is reversed with a pre-irradiation bake

0.4

ΔNot(1012cm-2)

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400

600

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1000 1200

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Fig. 8. Oxide-trap charge densities for Al-gate capacitors with 33 nm nonradiation-hardened oxides irradiated in 1986 [10] and 2001. Devices were irradiated with 10-keV X-rays at a bias of 5 V (after [9]).

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devices manufactured by National Semiconductor (Fig. 6). It was suggested that the interrelation between PETS and ELDRS might be attributable to a mutual dependency of the two phenomena on hydrogen in the thick, low-quality oxides that passivate base-emitter junctions [7]. Baking devices at 450 C for 200 s was found, in remarkable contrast, to increase the radiation sensitivity of the same LM111 devices (Fig. 7) at higher dose rates. These results suggest a complex interaction can occur between hydrogen species and precursor defects to radiation damage. These defects include oxygen vacancies in SiO2 that are trappedhole precursors and dangling bonds at the Si/SiO2 interface, which typically are passivated by hydrogen prior to radiation exposure or high-field stress, that are interface-trap precursors [8]. This illustrates the so-called ‘‘dual role’’ for hydrogen – it is beneficial to device response when it acts to passivate defects, but it can degrade device response when it reacts to create new defects [9].

0

ΔNot (1012cm-2)

Fig. 7. Input bias current as a function of dose and pre-irradiation stress for LM111 devices from National Semiconductor irradiated at 0 V at a dose rate of 50 rad(SiO2)/s (after [7]).

0

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Fig. 9. Oxide-trap charge densities for Al-gate capacitors with 33 nm nonradiation-hardened oxides irradiated in 1986 [10] and 2001. The baked devices were heated to 205 C for 18 h at 0 V bias. Devices were irradiated with 10-keV X-rays at a bias of 5 V (after [9]).

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when devices are exposed to hydrogen [9,15,16], suggesting that hydrogenous species may also play an important role in the aging results of Figs. 10 and 11 [12], as we discuss further below. The combinations of aging and PETS effects illustrated in Figs. 10 and 11 may lead to significant complications in evaluations of dose-rate and temperature effects in MOS and linear bipolar devices. As one potential past example, Winokur et al. reported a larger increase in the enhancement of interface-trap buildup at low dose rates in [17] for MOS transistors from different processing and

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[10]. Effects of aging on interface traps were not assessed in [10], owing to limitations of the availability of data from 1986 [11]. The aging results of Figs. 8 and 9 were obtained on simple capacitors that did not experience full CMOS processing. Experiments have also been performed on fully processed MOS devices with P-glass (3% P-doped SiO2) passivation layers [12]. Devices tested for aging effects in [12] include nMOS transistors processed at Sandia National Laboratories in 1984, with poly-crystalline Si gates and oxide thicknesses of 32 nm or 60 nm. All irradiations were performed with a 10-keV X-ray irradiator at room temperature at 6 V bias. Some devices were baked before irradiation. Devices were annealed at room temperature and then 100 C at 6 V bias. Fig. 10(a) compares threshold voltage shifts for nMOS transistors for 32 nm oxide parts irradiated in 1988 [13] and in 2005 [12]; the latter exposures were performed with and without exposure to PETS. The threshold-voltage rebound for parts irradiated in 2005 is much larger than for parts irradiated in 1988 (Fig. 10(a)). Fig. 10(b) shows the estimated threshold-voltage shifts due to interface-trap charge DVit for the 32 nm parts. By the end of the post-irradiation room-temperature anneal, the values of DVit for parts not exposed to PETS are 67% greater than the maximum DVit experienced by these parts in 1988. However, when parts are exposed to PETS prior to irradiation, these shifts in magnitude decrease substantially, but are still greater than the 1988 values [12,13]. Fig. 10(c) shows the shifts in threshold voltage due to oxide-trap charge DVot for the 32 nm gate oxide transistors. Much less change during irradiation and annealing is observed for DVot with aging or baking than for DVit. Also tested in [12] were 60 nm gate oxide transistors stored in hermetically sealed packages since 1987. These parts were irradiated to 100 krad(SiO2); results are plotted in Fig. 11. Fig. 11(a) shows DVth for nMOS transistors. The parts not exposed to PETS show an increase in magnitude of DVth of 0.2 V during the post-irradiation biased anneal, as compared to the 1988 results [12,13]. The magnitude of this increased shift during annealing is reduced by approximately 50% when parts are baked prior to irradiation. Fig. 11(b) shows DVit for the 60 nm gate oxide transistors. Less change is observed with aging than for the non-hermetically sealed devices of Fig. 10(b). Fig. 11(c) shows the values of DVot. To within experimental uncertainty, there is little difference in oxide-trap charge among the devices irradiated in 2005, with or without PETS, compared to the 1988 values [12,13]. The results of [12] show that the time and temperature history of a device can affect its postirradiation response significantly. Similar changes to those observed in Figs. 10 and 11 were observed by Kohler et al. on a shorter time scale for devices packaged in sealed hermetic packages containing up to 0.6% of hydrogen gas, and/or irradiated in hydrogen ambient conditions [14]. Enhanced interface-trap formation also has been observed after radiation exposure

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Fig. 10. DVth (a), DVit (b), and DVot (c) for 32 nm gate oxide nMOS transistors stored since 1987 in a non-hermetic environment vs. postirradiation anneal time for exposures to a dose of 500 krad(SiO2). The irradiation and anneal bias was 6 V. The 1988 data are from [13] (after [12]).

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Fig. 12. Threshold voltage shifts due to interface traps as a function of radiation dose rate for 3 lm · 16 lm transistors with radiation-hardened 45 nm oxides that were fabricated, packaged, and tested at Sandia National Laboratories in 1987. Interface-trap buildup with 0 V gate bias is observed to be strongly enhanced at low dose rates, consistent with enhanced low-dose-rate sensitivity and/or potential aging effects in these devices (after [17]).

effects during a low-dose-rate radiation exposure. Moreover, the complex interactions between aging and PETS effects observed in Figs. 6, 7 and 10, 11 may account at least in part for difficulties in applying elevated temperature irradiation as a hardness assurance test for enhanced low-dose-rate sensitivity in linear bipolar devices and ICs [18], as emphasized by Shaneyfelt et al. [7]. In radiation hardness assurance testing, all of these effects must be accounted for, preferably by testing as close to system use conditions as possible [1,7,18,19].

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4. Theory of H2O in SiO2

Fig. 11. DVth (a), DVit (b), and DVot (c) for 60 nm gate oxide nMOS transistors stored hermetically since 1987 vs. postirradiation anneal time for exposures to 100 krad(SiO2). The irradiation and anneal bias was 6 V. The 1988 data are from [13] (after [12]).

packaging lots than in follow-on work reported in [13]. The enhancement in interface-trap density was especially large at zero bias (Fig. 12). While factors related to dosimetry were identified in [13] that may account for some of the differences in results between [13] and [17], the work reported in [12] suggests that differences in aging responses of the two different types of devices in [13] and [17] (processed differently, and packaged at different times, relative to their respective irradiation and annealing tests) may also have contributed to the observed differences in apparent doserate dependence of interface-trap buildup. Thus, it can be difficult to distinguish true or apparent dose rate effects from changes in device radiation response due to aging

Especially for parts stored in a non-hermetic environment, it is likely that water and/or other hydrogenous species are associated with the observed effects of aging on radiation response [10,12]. Calculations reported in [12] show it is energetically favorable for water molecules to be absorbed in SiO2 as interstitials. The energy gain is 0.3– 0.5 eV per molecule, depending on topology. Bakos et al. [20] showed an interstitial water molecule in amorphous SiO2 can break into two bonded SiOH (silanol) groups (Fig. 13(a)), but the resulting complex is 0.3–0.7 eV higher in energy; the range is due to different local topologies in the amorphous network. Recently [12], a lower-energy configuration has been found, as shown in Fig. 13(b). The key difference between the structures is that Fig. 13(a) entails a broken ring in the SiO2 network [20], whereas in Fig. 13(b) there are no broken rings [12]. The energy is 0.3 eV lower than for free interstitial H2O in SiO2 (some variation with topology is expected). This complex can release hydrogen during subsequent irradiation or high-field stress, thus leading to enhanced interface-trap buildup. Other hydrogen-related reactions also are important. Our preliminary calculation results suggest O vacancies in SiO2 can efficiently crack H2O. The O atom eliminates the O vacancy, while H2 is released. H2 molecules diffuse randomly in the SiO2 network without reacting in the

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5. Bias-temperature instabilities

Fig. 13. Schematic diagrams of (a) a water complex consisting of two SiOH (silanol) groups and a broken ring [energy = +(0.3–0.7) eV]; (b) a water complex consisting of two SiOH groups and no broken ring [energy = 0.3 eV]. The large dark circles denote O atoms, the gray circles are Si atoms and the white circles are H atoms in SiO2.

SiO2 (in the absence of defects or impurities that can serve as cracking sites [15]), and are available to contribute to the passivation of dangling bonds at the Si–SiO2 interface. These and other [10,12] results suggest strongly that water molecules and other hydrogenous species in SiO2 cause many of the observed changes in radiation response with aging. Because MOS long-term reliability is also known to be quite sensitive to hydrogen [9,21], it is likely that many long-term reliability issues in MOS devices and ICs are affected similarly – for example, bias-temperature instabilities, as we now discuss.

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Recently NBTI has been compared in SiO2 and HfO2 gate dielectrics; in the work reported in [22] the HfO2 capacitors also have a thin oxynitride layer at the Si interface. The physical thickness of the high-j layer was 6.8 nm; the interfacial oxynitride layer was 1.0 nm. Oxide and interface-trap charge densities, DNot and DNit, are shown as functions of NBTI stress temperature in Fig. 14. For SiO2, the effective activation energy in Fig. 14(a) for DNot is 0.27 ± 0.03 eV, and for DNit is 0.31 ± 0.04 eV. Fig. 14(b) shows that, for SiOxNy/HfO2 devices, the effective activation energy for DNot is 0.35 ± 0.04 eV, and for DNit is 0.22 ± 0.03 eV [22]. These results are comparable to the range of effective activation energies that have been reported in the literature for thermal SiO2 [21], and are also consistent with recent work on HfO2 by Houssa et al. [23]. The direct dissociation of the Si–H bond at the Si/SiO2 interface has been suggested as a mechanism for generation of traps during NBTI, for example, in the presence of holes at the interface [24,25]. Density functional theory (DFT) calculations have been performed to evaluate this and other potential processes that may lead to negative-bias

Fig. 14. Oxide- and interface-trap charge densities vs. stress temperature for (a: upper) SiO2 capacitors stressed for 20 min at an electric field of – 1.54 MV/cm; and (b: lower) SiOxNy/HfO2 capacitors stressed for 20 min at 1.15 MV/cm (after [22]).

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temperature instabilities (NBTI) [26]. Our calculations show that the removal of the H atom from the Si–H bond to a remote Si–Si bond raises the energy of the system by about 1.9 eV. When this value is added to the associated migration barrier, which is 0.5 eV, the result leads to a dissociation activation energy Ea of 2.4 eV, in close agreement with experimental measurements of the dissociation of the Si–H bond at the Si/SiO2 interface (2.6 eV) [27– 30]. When holes are present, as is the case for NBTI in pMOS transistors, the energy required to remove the H from a Si–H bond decreases to 1.6 eV, and Ea decreases to 2.1 eV [26]. These values are well above those expected to affect NBTI, at least in the absence of high electric fields (e.g., those associated with a high oxide-trap charge density near the interface, which can be much higher locally than the average applied field across the oxide [31]), and/or the existence of additional nearby defects. Hence, during the normal operation of commercial-grade MOS devices, one would not expect significant Si–H bond breaking to occur via a direct dissociation mechanism. Given that direct depassivation of Si–H bonds is not the most likely cause for NBTI for typical experiments at low electric fields, a possible alternative is the depassivation reaction [26,32,33] Si–H + Hþ ! Siþ + H2

ð1Þ

First-principles DFT calculations find the reaction energy and barrier for reaction (1) to be 0.5 eV and 0.95 eV, for n-type Si in inversion [26]. Hence, this process is energetically preferred to direct dissociation of Si–H bonds. Excess hydrogen on the Si side of the interface above and beyond levels required to passivate fully the dangling bonds at the Si/SiO2 interface is a likely origin of this reliability problem. For example, in n-type Si (i.e., pMOS transistors), H primarily binds to P dopant atoms [26]. The energy to move H from a P–H bonding site to a remote position in Si is 0.6 eV, which is much lower than the value of 1.9 eV required to remove H thermally from a Si–H bond. The plausibility of the P–H center as a source for the protons leading to NBTI in pMOS transistors is established in [26], and shown to be consistent with previous work [26,34–36]. Hydrogen that arrives or is released from P–H complexes in the inversion layer becomes positively charged (H+) by trapping a hole under negative bias during NBTI; this H+ is swept to the interface by the negative bias. A similar mechanism may contribute to enhanced low-dose-rate sensitivity in linear bipolar devices, as discussed by Tsetseris et al. in [37]. Other mechanisms may be significant for NBTI and/or PBTI in nMOS devices [26], which typically are not as significant of problems as NBTI in pMOS transistors [38,39]. Moreover, several different types of materials (metals, semiconductors, and insulators) used in a semiconductor device may store hydrogen metastably, and then release it during storage or device use, especially if the device temperature increases significantly during operation [40]. Hence, on-chip but non-local sources of hydrogen are also a potential concern [41].

Protons that reach the interface from the Si side encounter a barrier of 1 eV to enter the SiO2 [42]. In contrast, the barrier against lateral migration is only 0.3 eV [43]. Thus, protons can migrate rapidly along the interface. Because both transporting protons and interface traps are positively charged at negative bias, reactions of H+ with Si+ are not likely due to simple electrostatics, so these protons cannot passivate pre-existing interface traps. In addition, the energy for H+ at the center of a Si–Si bond next to a Si– H entity is lower by 0.2 eV with respect to other sites for H+ in Si. Therefore, hydrogen can easily find Si–H bonds and activate reaction (1), leading to interface-trap formation. At 100–200 C, this reaction reaches quasi-equilibrium quickly. The dynamic balance of interface-trap formation and passivation is controlled by the diffusion of the product H2. In the diffusion-limited regime, Ea is given by [44,45] Ea ¼ 1=2DE þ 1=4DD

ð2Þ

where DE is the reaction energy of H2 with a pre-existing interface trap, and DD is the diffusion barrier of the migrating species. Using the value for DE  0.5 eV, and DD = 0.45 eV [46] for H2 diffusion in SiO2, it is found that Ea  0.36 eV [22], in very good agreement with the low effective activation energies reported in many NBTI experiments [9,22,23]. Protons that arrive at the interface can also eventually migrate into the oxide where they contribute to the buildup of oxide trapped charge. Significantly, oxide-trap charge in the form of a proton is much more difficult to neutralize via electron tunneling than trapped holes, leading to the relative stability of trapped H+ in SiO2 under NBTI stress conditions [22,32]. DFT calculations suggest Ea = 0.2–0.3 eV for the increase of oxide trapped charge [26], in agreement with measured values [9,22,23]. As for interface traps, the small Ea observed in experimental studies is only an apparent activation energy, observed in the large stress time limit, after the migration of H+ from Si to SiO2 reaches quasi-equilibrium. 6. Combined effects An interesting and potentially significant effect that has been observed in high-j gate dielectric stacks with high interface-trap densities is illustrated in Fig. 15 [47]. Here, Felix et al. report a decrease in interface-trap density with radiation exposure of MOS capacitors with alumina/oxynitride dielectrics. The observed decrease in interface-trap density is larger for positive-bias irradiation than for negative-bias irradiation. This decrease is in remarkable contrast to the typically observed case that interface traps tend to build up efficiently under positive bias in MOS devices [9]. The decrease in interface-trap density in Fig. 15 at positive bias is attributed to the passivation of negatively charged Si dangling bonds by a proton arriving at the interface after its release on the oxide side of the interface. For the case of a relatively high initial inter-

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Fig. 16. (a) DVot and (b) DVit induced by negative-bias irradiation (Vg = 0.3 V), zero-bias irradiation, and positive-bias irradiation (Vg = 0.3 V; Eox = 2.4 MV/cm), followed by negative bias-temperature stressing at 1 Mrad(SiO2) as a function of temperature for Al/HfO2 + SiOxNy/Si pMOS capacitors. The bias applied for NBTS is 0.3 V. The total dose is 1 Mrad(SiO2), and the stress time was 600 s at each temperature (after [54]).

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face-trap density, the transporting proton is more likely in these devices to encounter and passivate an existing interface trap than to depassivate a Si–H bond [47]. One might expect that interface-trap neutralization at negative bias in Fig. 15 would in turn be associated with the release of hydrogen in the Si, as inferred for interface-trap buildup under similar bias conditions [26,37]. However, at negative bias, dangling bonds are positively charged, so reactions with protons are inhibited. Thus, reactions involving neutral or negatively charged hydrogenous species may be more likely to lead to the observed interface-trap passivation in this case. Note that the interface-trap reduction rate is lower in Fig. 15 than the reduction rate under positive bias. This may reflect a relatively higher concentration of protons in the near-interfacial SiO2 and/or a relatively more favorable passivation reaction involving protons and negatively charged dangling bonds than positively charged dangling bonds and neutral or negatively charged hydrogenous species. Reversibility in interface-trap growth and annealing has also been observed for irradiated SiO2 in [48]. Similar mechanisms to those described above may also play a role in other examples of interface-trap annealing at relatively low temperatures noted in the literature [49–53], typically for cases in which significant densities of trapped positive charge and hydrogenous species are simultaneously present in MOS and linear bipolar devices. The passivation of interface traps by molecular hydrogen also likely plays a significant role in these cases [51]. These results illustrate the competition that can occur between interface-trap buildup and passivation in devices with moderate to high interface-trap densities during irradiation and/or postirradiation annealing. The process that dominates is determined by the initial defect densities, concentrations of hydrogenous species, bias, time, dose, temperature, etc. [47–53]. Combined irradiation and bias-temperature effects can be even more complex, especially in high-j gate dielectrics

 IEEE 2003 Fig. 15. Interface-trap densities as estimated via charge pumping as a function of dose for 100 lm · 100 lm nMOS transistors with 20 nm Al2O3 on 0.7 nm SiOxNy gate dielectrics irradiated with 10-keV X-rays at a dose rate of 1000 rad(SiO2)/s (after [47]).

[54]. In Fig. 16, Al gate capacitors with a 6.8 nm HfO2 over 1 nm nitrided oxide gate dielectric are subjected to negative bias-temperate stress (NBTS) after positive bias, zero bias, and negative bias irradiation to 1.0 Mrad(SiO2). Values of DVot and DVit with and without prior irradiation exposure are compared. The combined irradiation and NBTS lead to significant enhancements of degradation over irradiation or NBTS alone. The worst-case degradation here is caused by positive-bias irradiation followed by NBTS, with zero bias irradiation and NBTS causing the next worst case degradation. The enhanced responses in this case involve not only the kinds of hydrogen transport and reactions we have discussed, but also electron and hole trapping and de-trapping in the gate dielectric layer [37,48,54–58]. The resulting threshold voltage shifts can be much larger in the combined environment than one would infer from a linear combination of the separate NBTS and radiation responses, further emphasizing the need to understand how MOS device

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response changes with time, temperature, and aging, and incorporating this understanding into reliability assessment plans [54]. 7. Aging and hydrogen effects in other systems The crucial roles of protons, water, and other hydrogenous species are by no means unique to silicon-based microelectronics. Similar degradation effects are observed in other types of microelectronic materials and devices. For example, hydrogen-related reliability degradation and aging effects have been reported in systems as diverse as GaN and InGaN based light-emitted diodes [59,60], AlGaInP lasers [61], InP photodiodes [62], GaAs [63] and InGaP/GaAs [64] heterojunction bipolar transistors, optical fibers [65], ferroelectric capacitors [66], and many others. This emphasizes the importance of hydrogen to the reliability and aging response of most kinds of microelectronic materials and devices. 8. Conclusion Oxide and interface traps in MOS devices are affected strongly by hydrogenous species. These species can migrate and react during device storage or use, especially when hermeticity is not maintained, or when a high partial pressure of hydrogen gas exists in the device package. As a result, the radiation response and long-term reliability of MOS and bipolar devices can change significantly with time. Hence, measurements performed early in a device lifetime may not be able to easily predict the significant consequences of these processes, which naturally occur over a wide range of effective activation energies. The results we have reviewed show that the radiation response of MOS devices can be affected significantly by aging, and the inferred device reliability also likely varies significantly with aging time, owing to the similarities of the defects and impurities that control each type of response. For devices that are sensitive to these kinds of aging effects, additional margins against failure are required. Especially in a low-dose-rate radiation environment where one may experience combined radiation, aging, and bias-temperature stress effects, device response may be much worse than expected, if one has not accounted properly for these effects in part selection and screening. Acknowledgments This work was supported in part by the US Navy, the Air Force Office of Scientific Research through a Multidisciplinary University Research Initiative, and by the McMinn endowment at Vanderbilt University. This paper is based on a presentation at the 25th International Conference on Microelectronics, Belgrade, Serbia and Montenegro, May 14–17, 2006. We thank N. Stojadinovic for stimulating discussions.

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