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Si metal–oxide–semiconductor structure
Thin Solid Films 483 (2005) 232 – 238 www.elsevier.com/locate/tsf
Effects of fluorine and chlorine on the gate oxide integrity of W/TiN/SiO2/Si metal–oxide–semiconductor structure Dae-Gyu Park*, Tae-Kyun Kim Advanced Process Team, Memory R&D Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon, Kyoungki-do 467-701, Korea Received 28 November 2003; accepted in revised form 1 December 2004 Available online 8 March 2005
Abstract We investigate the effects of fluorine (F) and chorine (Cl) on the gate oxide integrity of W/TiN/SiO2 (3 nm)/Si metal–oxide– semiconductor (MOS) structure as a function of W deposition method and post-metal anneal (PMA) process. TiN films were prepared by chemical vapor deposition (CVD) using TiCl4 and NH3, while tungsten (W) electrodes were prepared by CVD using a WF6 precursor and by physical vapor deposition (PVD) using a W target. The amount of fluorine ([F]) prepared by CVD-W was two orders of magnitude higher than that prepared by PVD-W. The interface trap density (D it) of MOS capacitor was lower with CVD-W than the one with PVD-W by a factor of two after PMA of 950 8C, resulting in the D it in the mid-1010/eV cm 2 range. The higher D it, fixed charges, and oxide trap charges were observed with PVD-W deposition on top of 30 nm-thick CVD-TiN, strongly suggesting damages at the SiO2/Si interface and SiO2 even after the rapid thermal anneal at 950 8C and following forming gas anneal. However, a noticeable degradation of gate oxide quality was observed with CVD-W by means of smaller breakdown field, charge to breakdown, and shorter lifetime. The reliability degradation was partially attributed to the Cl from the TiCl4 source, while more severe deterioration was assigned to the F from WF6 source after the PMA at 650 8C and above. D 2004 Elsevier B.V. All rights reserved. PACS: 73.40.Q Keywords: Metal–oxide–semiconductor structure (MOS); Surface and interface states; Chlorine; Fluorine
1. Introduction With scaling complementary metal–oxide–semiconductor (CMOS) devices to the sub-90 nm technology node, gate depletion and high gate leakage current have become a significant problem for polycrystalline-Si (poly-Si) gate on ultrathin gate oxide [1–3]. The poly-Si gate depletion in conjunction with boron penetration is especially troublesome for p-type poly-Si on thin SiO2 (b3 nm). One of the approaches to overcome these problems is to use a metal gate electrode directly deposited on the gate dielectrics [2–14]. A series of advanced researches on direct metal gates were carried out using W [4], Mo [5], WN [6,7], TiNx
* Corresponding author. E-mail address: [email protected] (D.-G. Park). 0040-6090/$ - see front matter D 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2004.12.003
[2,9–12], and other metals on SiO2 [8,13,14]. On one hand, Buchanan et al. [4] reported W midgap metal gate compatible with thin dielectric (~3 nm) and demonstrated symmetric flatband voltages for n- and p-type substrate with a barrier height of 3.70 eV. On the other hand, some interesting results such as generation of interface traps and reliability degradation of MOS devices due to metal penetration and ion damage during the physical vapor deposition (PVD) process were presented [4,5,10–12]. To anneal the aforementioned defects, the MOS structures gated with direct metals were subjected to a post metal anneal (PMA) at high temperatures or in a forming gas anneal (FGA) ambient [4,5,11,12]. Most recently, the feasibility of W/TiN gate stack has been evaluated for conventional 130 nm CMOS technology and beyond [3,9–12]. W/TiN stack is of technological importance because of its midgap work function, low
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In this paper, we studied the effects of fluorine (F) and chlorine (Cl) on the characteristics of the W/TiN/SiO2/Si MOS capacitors by comparing two different W metal electrodes prepared by CVD and PVD. This paper focuses on the evolution of defect charges such as interface traps and various defect charges, and evaluates the gate oxide integrity (GOI) during metal gate formation and PMA on controlled SiO2 (3 nm). We found that CVD method reduced the generation of defect charges over PVD-W, whereas it degraded the GOI characteristics due to the flourine introduced during CVD process and following PMA.
2. Experimental Fig. 1. SIMS profile of F in the TiN/SiO2/Si stack with two different W depositions. The amount of F is ~31020 atoms/cm3 for the CVD-W and b41018 for the PVD-W.
resistivity and good diffusion barrier properties [7,9]. While PVD-TiN films sputtered at high temperature showed better electrical properties than those prepared at room temperature [3], chemical vapor deposition (CVD)-TiN prepared by TiCl4 and NH3 demonstrated lower gate leakage and better flat band voltage uniformity than PVD-TiN [10,11]. While the use of CVD-TiN may control the quality of MOS characteristics, the role of upper electrode has not been studied comprehensively. In general, the top electrodes need to have good thermal stability and low resistance. Good step coverage is also required when considering a damascene or replacement gate structure. So far, many of the W/TiN stack evaluations were performed by the PVD-W on various TiN films. However, we selected two different W deposition methods such as CVD-W and PVD-W on the CVD-TiN to evaluate the top electrode effects on the MOS device characteristics for a given PMA. WF6 is one of the most known precursor materials for CVD-W and has been used in deep contact application because of good step coverage properties, while the fluorine in WF6 can negatively affect the MOS device performance.
The substrates were 8-in., (100) oriented p-type silicon wafers with a resistivity of 8–10 V cm. After field oxidation for device isolation, a standard pre-gate cleaning step was employed using a diluted-HF final cleaning and deionized water rinse prior to gate oxidation. Controlled gate oxides, SiO2 (3 nm), were grown in a wet oxidation ambient at 700– 800 8C in a resistively heated vertical furnace. As an electrode of metal gate, chemical vapor deposition (CVD)TiN film (~30 nm) was prepared by thermal reaction of TiCl4 and NH3 at 550–650 8C. To examine the effect of F on the gate oxide quality of MOS capacitors, W electrodes (~60 nm) were prepared by CVD using a WF6 precursor at 400 8C with a SiH4 soaking to enhance the nucleation of W at the initial stage of deposition. In comparison, a sputtering of a W target was also prepared by a DC magnetron sputtering at 200 8C using a plasma power density of 1–2 W/cm2 as a reference for fluorine-free source. This was followed by photolithography and reactive ion etching to form 410 4 cm2 square electrodes. To investigate the effects of PMA on MOS characteristics, the MOS structure was exposed to rapid thermal anneal (RTA) at 650–950 8C in nitrogen for 20 s, followed by a forming gas anneal at 450 8C in 10% H2/ 90% N2 for 30 min. Electrical characterization of the W/TiN/SiO2/Si MOS capacitor was carried out in a light free probe station. In
Fig. 2. The high frequency (100 kHz) C–V hysteresis characteristics of the W/CVD-TiN/SiO2 (~3 nm)/p-Si MOS structures as a function of PMA; (a) PVD-W and (b) CVD-W. The C–V hysteresis traced from inversion to accumulation (+3 VY 3 V) and back to inversion (+3 V).
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Fig. 3. Variation of capacitance equivalent thickness (CET) and C–V hysteresis as a function of PMA and W deposition method. The detailed conditions for thermal split are as follows; A: as-patterned, B: FGA (450 8C for 30 min), C: RTA 650 8C+FGA, D: RTA 800 8C+FGA, E: RTA 950 8C+FGA.
order to examine the level of interface traps and bulk defects as a function of W deposition method and PMA, capacitance–voltage (C–V) and conductance measurements were performed using a HP4284A LCR meter [15–18]. The capacitance equivalent thickness (CET) was defined as the thickness calculated from the accumulation capacitance at 3 V for SiO2 (~3 nm) without correction for the quantum mechanical effect. The fluorine and chlorine contents in W/ TiN/SiO2 were probed by a PHI-6300 secondary ion mass spectrometer (SIMS) using a Cs+ primary ion source of ~3 keV beam energy.
3. Results and discussion Shown in Fig. 1 is a depth profile of F in the as-patterned TiN/SiO2/Si stack after W removal. The amount of F prepared by CVD-W was about two orders of magnitude higher than the one by PVD-W as measured by secondary ion counts. The atomic level of fluorine in TiN/SiO2 with CVD-W is ~31020/cm3, showing that [F] is significantly
higher across the MOS capacitors in case of CVD-W/TiN/ SiO2/Si stack. It is noted that slightly high F level (41018 atoms/cm3) in PVD-W/TiN/SiO2 may be contaminated from the annealing furnace. Fig. 2 exhibits 100 kHz C–V hysteresis characteristics of the W/TiN/SiO2 (3 nm)/p-Si MOS structures as a function of PMA. There are several interesting features. First, a large amount of flat band voltage shift (DV FB) was observed for PVD-W electrode after PMA [Fig. 2(a)], while negligible DV FB was seen for CVD-W [Fig. 2(b)]. The major DV FB ( 0.25 V) corresponds to the positive fixed charged ( Q f) of 1.61012/cm2, which was mainly observed in PVD-W after FGA at 450 8C. This DV FB may be related with the ion damages induced during PVD-W deposition, which will be discussed later in detail. However, the V FB remains almost the same regardless of the PMA done at higher temperature. Second, the CET increase is much more pronounced with CVD-W after RTA at over 800 8C. Fig. 3 describes more comprehensive information on the CET and CV hysteresis variation with PMA. As far as the C–V hysteresis is concerned for the as-patterned MOS capacitor, the PVD-W split showed higher C–V hysteresis compared to the CVDW, indicating the existence of oxide trap charges generated during PVD-W deposition even on the CVD-TiN/SiO2/Si stack. This hysteresis can be significantly reduced by the PMA over 800 8C and FGA. Interestingly, the CET increase is noticeable in case of CVD-W after PMA at over 800 8C, whereas the CET variation with PVD-W is noticed only after PMA at 950 8C. In an earlier report [11], the CET increase was observed with CVD-TiN due to the SiO2 thickness increase as a result of Cl introduced during CVDTiN deposition, which is consistent with present results. Furthermore, the higher CET increase was observed here with CVD-W, probably resulted from the fluorinated SiO2. By the way, the lower CV hystereses or lower oxide trapped charges were attained with CVD-W, which was affected not only by the plasma-free process but also by the higher [F]. Shown in Fig. 4 are depth profiles of F and Cl of CVDW/TiN/SiO2/Si structure as a function of PMA. The SIMS profile in Fig. 4(a) indicates that the [F] in W/TiN stack was increased after FGA and diffused into the SiO2 after a series of PMA. The F diffusion was noticed after the PMA at 650
Fig. 4. SIMS profile of (a) F and (b) Cl in the W/TiN/SiO2/Si stack with CVD-W and PMA.
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8C and then retarded at higher temperature. Fig. 4(b) also shows depth profiles of Cl with PMA, which is similar to the trends of [F]. The amount of [F] and [Cl] in SiO2 and SiO2/Si interface were increased about an order of magnitude at 650 8C and FGA, while the impurity level was the highest after PMA at 950 8C. The CET variation in Fig. 3 is well consistent with impurity behavior as shown in the SIMS profiles and the higher [F] can be responsible for the higher CET observed with CVD-W. For the extraction of the quantitative interface states or trap density (D it) with different W process, the C–V and conductance measurements were performed [15–18]. Shown in Fig. 5 are the C–V and conductance loss ( G m/ x)–gate voltage (V) curves [Fig. 5(a)] and the G m/x–log x [Fig. 5(b)] of the W/TiN/SiO2 (3 nm)/p-Si MOS structures without PMA. One may note that the C–V shift between the two curves is related with two different W processing, which was discussed in Fig. 2. In case of PVD-W, the higher conductance loss peaks are noticed from both G m/x–V curve and G m/x–log x curves. The level of conductance loss value with PVD-W is about 4 times higher than the one with CVD-W, exhibiting that near midgap D it value is four times higher for PVD-W split. It is evident that the PVD-W introduced higher fixed charges ( Q f), oxide trap charges, and interface traps, even though the W electrode was deposited on the 30-nm-thick CVD-TiN films. Fig. 6 summarizes the evolution of D it as determined by G m/x–log x curves with PMA. In brief, the D it level with CVD-W is lower than the one with PVD-W by a factor of two, which can be attributed to the plasma-free process and hydrogen passivation during deposition. The D it trends with PVD-W are easily understood. For example, the D it of aspatterned PVD-W/CVD-TiN is ~31011/eV cm2 and this level has reduced to ~11011/eV cm2 and ~81010/eV cm2 after FGA and PMA (950 8C)+FGA, respectively. It is worthwhile to reciting previous work on the D it results of PVD-W on PVD-TiN and CVD-TiN [11]. The D it level gated with as-patterned PVD-W/PVD-TiN stack is about five times higher than the one with PVD-W/CVD-TiN. The D it value (21012/eV cm2) of as-patterned PVD-W/PVD-
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Fig. 6. The D it level of the W/CVD-TiN/SiO2/p-Si MOS as a function of W deposition and PMA at the given gate voltage as determined by the conductance loss. The detailed conditions for thermal split are as follows; A: as-patterned, B: FGA (450 8C for 30 min), C: RTA 650 8C+FGA, D: RTA 800 8C+FGA, E: RTA 950 8C+FGA.
TiN was reduced to 31011/eV cm2 by the PMA at 450 8C and this was further improved by the combination of high temperature RTP and FGA. This trend is consistent with the present result of PVD-W/CVD-TiN, while the D it level was lower with CVD-TiN by a factor of two. On the other hand, the D it tendency with CVD-W is somewhat different. The lower D it (~51010/eV cm2) was obtained from the as-patterned CVD-W/TiN/SiO2/Si MOS capacitors and the D it increased to ~11011/eV cm2 after FGA. This D it level was further reduced by a series of RTA+FGA toward ~41010/eV cm2, in which the D it trend is similar to PVD-W. The low D it level (~51010/eV cm2) of as-patterned CVD-W is ascribed to plasma-free CVD-W process and hydrogen passivation of Si dangling bond during W and/or TiN deposition, in which hydrogen atoms are produced from SiH4 or NH3. The increased D it level after FGA, however, is not a common behavior and need more speculation for further understanding. The plausible
Fig. 5. (a) The C–V curves and conductance loss (G m/x)–gate voltage (V) of the W/TiN/SiO2 (3 nm)/p-Si MOS structures for a given frequency of 100 kHz and (b) conductance loss (G m/x)–log x of the W/TiN/SiO2 (3 nm)/p-Si MOS structures without anneal. The solid lines are for CVD-W and the dashed ones are for PVD-W. The applied gate voltages or surface potentials are also shown.
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Fig. 7. The J–V curves of the W/CVD-TiN/SiO2 (3 nm)/p-Si MOS structures as a function of PMA temperature; (a) PVD-W and (b) CVD-W.
sources of D it change for CVD-W can be related with impurity ([F], [Cl]) behaviors or stress change of W/TiN structure during thermal cycle, which need to be further clarified. The PMA with FGA done at higher temperature seems to be beneficial to passivate Si dangling bonds as evidenced by D it decrease. Fig. 7 depicts current density ( J)–voltage (V) characteristics of W/TiN/SiO2 (3 nm)/p-Si MOS capacitors as a function of W deposition and PMA temperature. The generic J–V characteristics are very the same for two different W depositions. The leakage current decreases with PMA at lower voltage range (b 1.3 V); however, the leakage current increases with PMA at high voltage range (N 1.3 V). The deteriorated leakage current behavior at high voltage field region (N 1.3 V) was consistent with the earlier work [11,12], at which the Cl-induced trap-sites in SiO2 were responsible. The leakage reduction at low voltage is noticeable after PMA at 800 8C+FGA, where the reduction of leakage current is much more pronounced with CVD-W after 950 8C+FGA. This is plausibly attributed to the increased CET as a result of fluorinated SiO2 as noticed from SIMS profile in Fig. 4(a). Shown in Fig. 8 are J–V characteristics with two different W depositions, showing almost identical J–V characteristics at 650 8C and 800 8C. From the identical J–V characteristics, it is expected that the higher CET value (~0.5 nm) for CVD-W after PMA at 800 8C may be resulted from the fluorinated SiO2 rather than the increased SiO2 thickness. For instance, lower effective permittivity (k) of fluorinated-SiO2 at the similar SiO2
thickness can be resulted in higher CET. It is worthwhile to mentioning that the J–V uniformity within the wafer is bad especially for CVD-W annealed at 950 8C (not shown). Fig. 9 exhibits the breakdown voltage (BV) of W/TiN/SiO2 (3 nm)/Si MOS capacitors as a function of W deposition and PMA. Interestingly, the breakdown voltage and the wear-out current levels are decreased with PMA temperature even with increased CET values regardless of W deposition. The BV of CVD-W after PMA at 950 8C showed non-uniform distribution with ~30% initial failure, which might be related with the poor J–V uniformity. Fig. 10 displays time-to-breakdown (T BD) of W/TiN/ SiO2 (3 nm)/Si MOS capacitor as determined by the constant current stress (CCS) condition of 1.2510 3 A/ cm2. The results showed that the T BD characteristics of the CVD-W samples were slightly degraded compared to those of PVD-W up to 650C (not shown), but those were seriously deteriorated with PMA at over 800 . The T BD characteristics of the MOS structure gated with CVD-W after PMA at 950 8C showed earlier failure and noticeable degradation compared to those of PVD-W samples, that was expected from the non-uniform BV distribution (Fig. 8). These nonuniform J–V and shorter T BD characteristics are plausibly resulted from the F related bulk defects in SiO2 or the Clrelated defect sites as further aggravated by the F incorporation. Moriwaki and Yamada [12] proposed a local defect spot in the SiO2 when used CVD-TiN due to the Clrelated trap-sites, which was observed only for thick SiO2 (5.6 nm) samples annealed at 1000 8C. Unfortunately we
Fig. 8. The J–V curves of the W/CVD-TiN/SiO2 (3 nm)/p-Si MOS structures as a function of W deposition at PMA temperature of (a) 650 8C+FGA and (b) 800 8C+FGA.
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Fig. 9. The breakdown voltage characteristics of the W/CVD-TiN/SiO2 (3 nm)/p-Si MOS structures as a function of W deposition and PMA temperature.
have not observed such a remarkable degradation from PVD-W/CVD-TiN/SiO2/Si stack probably because of the different SiO2 thickness range (~3 nm) experimented. However, as the fluorine has involved by replacing PVDW with CVD-W, a notable reliability worsening was observed by means of abnormal J–V, BV distribution and shorter T BD after PMA at 950 8C. Fig. 11 exhibits the T BD characteristics of W/TiN/SiO2 (3 nm)/Si MOS capacitors exposed to PMA at 800 8C under the constant voltage stress (CVS) condition. The general T BD characteristics are equivalent by means of similar T BD trends with same voltage applied; however, we need to normalize the applied voltage by CET for fair comparison. Shown in Fig. 12 is a projection of 10-year lifetime, i.e., mean time to failure (MTTF) versus applied field (MV/cm). The critical
Fig. 10. Time to breakdown characteristics of W/CVD-TiN/SiO2 (~3 nm)/pSi MOS structures at constant current density of 1.25e 3 A/cm2 as a function of W deposition and PMA temperature.
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Fig. 11. Time to breakdown characteristics of W/CVD-TiN/SiO2 (3 nm)/pSi MOS structures at constant voltage stress as a function of W deposition at a PMA temperature of 800 8C+FGA.
oxide field (E ox, critical) of over 10.1 MV/cm may be used with PVD-W/CVD-TiN electrode combination at room temperature, while the E ox, critical of 8.4 MV/cm can be used for CVD-W/CVD-TiN after PMA at 800 8C. For the low thermal budget devices (b650 8C) such as damascene gate or replacement gate structure, E ox, critical of over 11.3 MV/cm and 9.7 MV/cm may be used for PVD-W and CVD-W, respectively. It is obvious that the applied electric field at 10-year lifetime projection is higher with PVD-W
Fig. 12. 10-year lifetime of W/TiN/SiO2 (3 nm)/p-Si MOS structures with PMA measured at room temperature. Each data point represents mean time to failure (MTTF) of 40 data points on the 8-in. wafers. The critical oxide field, E ox, critical of over 10.1 MV/cm may be used with PVD-W/CVDTiN electrode combination at room temperature, while the E ox, critical of 8.4 MV/cm can be used for CVD-W/CVD-TiN after PMA at 800 8C. For the low thermal budget devices (b650 8C) such as damascene gate or replacement gate structure, E ox, critical of over 11.3 MV/cm and 9.7 MV/ cm may be used for PVD-W and CVD-W, respectively.
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than CVD-W for a given PMA temperature of 650 8C and 800 8C. The root cause of GOI degradation was strongly related with the impurity incorporation such as Cl and F, which should be minimized during deposition process.
4. Conclusion We evaluated the effects of F and Cl on the gate oxide integrity of W/TiN/SiO2 (3 nm)/Si metal–oxide–semiconductor (MOS) structure as a function of two different W deposition and post-metal anneal (PMA). CVD-W process induced higher CET increase with PMA, while lower D it and defect charges were generated. PVD-W generated the higher D it, fixed charges and oxide trap charges resulted from the damages in the SiO2 and at the SiO2/Si interface even on top of 30-nm-thick CVD-TiN. However, a noticeable degradation of gate oxide quality was observed with CVD-W by means of smaller breakdown field, lower charge to breakdown, and shorter lifetime. The reliability degradation was partially attributed to the Cl from the TiCl4 source, while more severe degradation was assigned to the F from WF6 source after the PMA at 650 8C and above. A deposition method to minimize the impurity concentration is necessary.
Acknowledgments The authors would like to thank Jung-Kyu Ko, Jae-Young Kim, Se-Aug Jang, Heung-Jae Cho, Kwan-Yong Lim, and Tae-Ho Cha for SIMS analyses and sample preparation.
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Effects of fluorine and chlorine on the gate oxide integrity of W/TiN/SiO2/Si metal–oxide–semiconductor structure Dae-Gyu Park*, Tae-Kyun Kim Advanced Process Team, Memory R&D Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon, Kyoungki-do 467-701, Korea Received 28 November 2003; accepted in revised form 1 December 2004 Available online 8 March 2005
Abstract We investigate the effects of fluorine (F) and chorine (Cl) on the gate oxide integrity of W/TiN/SiO2 (3 nm)/Si metal–oxide– semiconductor (MOS) structure as a function of W deposition method and post-metal anneal (PMA) process. TiN films were prepared by chemical vapor deposition (CVD) using TiCl4 and NH3, while tungsten (W) electrodes were prepared by CVD using a WF6 precursor and by physical vapor deposition (PVD) using a W target. The amount of fluorine ([F]) prepared by CVD-W was two orders of magnitude higher than that prepared by PVD-W. The interface trap density (D it) of MOS capacitor was lower with CVD-W than the one with PVD-W by a factor of two after PMA of 950 8C, resulting in the D it in the mid-1010/eV cm 2 range. The higher D it, fixed charges, and oxide trap charges were observed with PVD-W deposition on top of 30 nm-thick CVD-TiN, strongly suggesting damages at the SiO2/Si interface and SiO2 even after the rapid thermal anneal at 950 8C and following forming gas anneal. However, a noticeable degradation of gate oxide quality was observed with CVD-W by means of smaller breakdown field, charge to breakdown, and shorter lifetime. The reliability degradation was partially attributed to the Cl from the TiCl4 source, while more severe deterioration was assigned to the F from WF6 source after the PMA at 650 8C and above. D 2004 Elsevier B.V. All rights reserved. PACS: 73.40.Q Keywords: Metal–oxide–semiconductor structure (MOS); Surface and interface states; Chlorine; Fluorine
1. Introduction With scaling complementary metal–oxide–semiconductor (CMOS) devices to the sub-90 nm technology node, gate depletion and high gate leakage current have become a significant problem for polycrystalline-Si (poly-Si) gate on ultrathin gate oxide [1–3]. The poly-Si gate depletion in conjunction with boron penetration is especially troublesome for p-type poly-Si on thin SiO2 (b3 nm). One of the approaches to overcome these problems is to use a metal gate electrode directly deposited on the gate dielectrics [2–14]. A series of advanced researches on direct metal gates were carried out using W [4], Mo [5], WN [6,7], TiNx
* Corresponding author. E-mail address: [email protected] (D.-G. Park). 0040-6090/$ - see front matter D 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2004.12.003
[2,9–12], and other metals on SiO2 [8,13,14]. On one hand, Buchanan et al. [4] reported W midgap metal gate compatible with thin dielectric (~3 nm) and demonstrated symmetric flatband voltages for n- and p-type substrate with a barrier height of 3.70 eV. On the other hand, some interesting results such as generation of interface traps and reliability degradation of MOS devices due to metal penetration and ion damage during the physical vapor deposition (PVD) process were presented [4,5,10–12]. To anneal the aforementioned defects, the MOS structures gated with direct metals were subjected to a post metal anneal (PMA) at high temperatures or in a forming gas anneal (FGA) ambient [4,5,11,12]. Most recently, the feasibility of W/TiN gate stack has been evaluated for conventional 130 nm CMOS technology and beyond [3,9–12]. W/TiN stack is of technological importance because of its midgap work function, low
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233
In this paper, we studied the effects of fluorine (F) and chlorine (Cl) on the characteristics of the W/TiN/SiO2/Si MOS capacitors by comparing two different W metal electrodes prepared by CVD and PVD. This paper focuses on the evolution of defect charges such as interface traps and various defect charges, and evaluates the gate oxide integrity (GOI) during metal gate formation and PMA on controlled SiO2 (3 nm). We found that CVD method reduced the generation of defect charges over PVD-W, whereas it degraded the GOI characteristics due to the flourine introduced during CVD process and following PMA.
2. Experimental Fig. 1. SIMS profile of F in the TiN/SiO2/Si stack with two different W depositions. The amount of F is ~31020 atoms/cm3 for the CVD-W and b41018 for the PVD-W.
resistivity and good diffusion barrier properties [7,9]. While PVD-TiN films sputtered at high temperature showed better electrical properties than those prepared at room temperature [3], chemical vapor deposition (CVD)-TiN prepared by TiCl4 and NH3 demonstrated lower gate leakage and better flat band voltage uniformity than PVD-TiN [10,11]. While the use of CVD-TiN may control the quality of MOS characteristics, the role of upper electrode has not been studied comprehensively. In general, the top electrodes need to have good thermal stability and low resistance. Good step coverage is also required when considering a damascene or replacement gate structure. So far, many of the W/TiN stack evaluations were performed by the PVD-W on various TiN films. However, we selected two different W deposition methods such as CVD-W and PVD-W on the CVD-TiN to evaluate the top electrode effects on the MOS device characteristics for a given PMA. WF6 is one of the most known precursor materials for CVD-W and has been used in deep contact application because of good step coverage properties, while the fluorine in WF6 can negatively affect the MOS device performance.
The substrates were 8-in., (100) oriented p-type silicon wafers with a resistivity of 8–10 V cm. After field oxidation for device isolation, a standard pre-gate cleaning step was employed using a diluted-HF final cleaning and deionized water rinse prior to gate oxidation. Controlled gate oxides, SiO2 (3 nm), were grown in a wet oxidation ambient at 700– 800 8C in a resistively heated vertical furnace. As an electrode of metal gate, chemical vapor deposition (CVD)TiN film (~30 nm) was prepared by thermal reaction of TiCl4 and NH3 at 550–650 8C. To examine the effect of F on the gate oxide quality of MOS capacitors, W electrodes (~60 nm) were prepared by CVD using a WF6 precursor at 400 8C with a SiH4 soaking to enhance the nucleation of W at the initial stage of deposition. In comparison, a sputtering of a W target was also prepared by a DC magnetron sputtering at 200 8C using a plasma power density of 1–2 W/cm2 as a reference for fluorine-free source. This was followed by photolithography and reactive ion etching to form 410 4 cm2 square electrodes. To investigate the effects of PMA on MOS characteristics, the MOS structure was exposed to rapid thermal anneal (RTA) at 650–950 8C in nitrogen for 20 s, followed by a forming gas anneal at 450 8C in 10% H2/ 90% N2 for 30 min. Electrical characterization of the W/TiN/SiO2/Si MOS capacitor was carried out in a light free probe station. In
Fig. 2. The high frequency (100 kHz) C–V hysteresis characteristics of the W/CVD-TiN/SiO2 (~3 nm)/p-Si MOS structures as a function of PMA; (a) PVD-W and (b) CVD-W. The C–V hysteresis traced from inversion to accumulation (+3 VY 3 V) and back to inversion (+3 V).
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Fig. 3. Variation of capacitance equivalent thickness (CET) and C–V hysteresis as a function of PMA and W deposition method. The detailed conditions for thermal split are as follows; A: as-patterned, B: FGA (450 8C for 30 min), C: RTA 650 8C+FGA, D: RTA 800 8C+FGA, E: RTA 950 8C+FGA.
order to examine the level of interface traps and bulk defects as a function of W deposition method and PMA, capacitance–voltage (C–V) and conductance measurements were performed using a HP4284A LCR meter [15–18]. The capacitance equivalent thickness (CET) was defined as the thickness calculated from the accumulation capacitance at 3 V for SiO2 (~3 nm) without correction for the quantum mechanical effect. The fluorine and chlorine contents in W/ TiN/SiO2 were probed by a PHI-6300 secondary ion mass spectrometer (SIMS) using a Cs+ primary ion source of ~3 keV beam energy.
3. Results and discussion Shown in Fig. 1 is a depth profile of F in the as-patterned TiN/SiO2/Si stack after W removal. The amount of F prepared by CVD-W was about two orders of magnitude higher than the one by PVD-W as measured by secondary ion counts. The atomic level of fluorine in TiN/SiO2 with CVD-W is ~31020/cm3, showing that [F] is significantly
higher across the MOS capacitors in case of CVD-W/TiN/ SiO2/Si stack. It is noted that slightly high F level (41018 atoms/cm3) in PVD-W/TiN/SiO2 may be contaminated from the annealing furnace. Fig. 2 exhibits 100 kHz C–V hysteresis characteristics of the W/TiN/SiO2 (3 nm)/p-Si MOS structures as a function of PMA. There are several interesting features. First, a large amount of flat band voltage shift (DV FB) was observed for PVD-W electrode after PMA [Fig. 2(a)], while negligible DV FB was seen for CVD-W [Fig. 2(b)]. The major DV FB ( 0.25 V) corresponds to the positive fixed charged ( Q f) of 1.61012/cm2, which was mainly observed in PVD-W after FGA at 450 8C. This DV FB may be related with the ion damages induced during PVD-W deposition, which will be discussed later in detail. However, the V FB remains almost the same regardless of the PMA done at higher temperature. Second, the CET increase is much more pronounced with CVD-W after RTA at over 800 8C. Fig. 3 describes more comprehensive information on the CET and CV hysteresis variation with PMA. As far as the C–V hysteresis is concerned for the as-patterned MOS capacitor, the PVD-W split showed higher C–V hysteresis compared to the CVDW, indicating the existence of oxide trap charges generated during PVD-W deposition even on the CVD-TiN/SiO2/Si stack. This hysteresis can be significantly reduced by the PMA over 800 8C and FGA. Interestingly, the CET increase is noticeable in case of CVD-W after PMA at over 800 8C, whereas the CET variation with PVD-W is noticed only after PMA at 950 8C. In an earlier report [11], the CET increase was observed with CVD-TiN due to the SiO2 thickness increase as a result of Cl introduced during CVDTiN deposition, which is consistent with present results. Furthermore, the higher CET increase was observed here with CVD-W, probably resulted from the fluorinated SiO2. By the way, the lower CV hystereses or lower oxide trapped charges were attained with CVD-W, which was affected not only by the plasma-free process but also by the higher [F]. Shown in Fig. 4 are depth profiles of F and Cl of CVDW/TiN/SiO2/Si structure as a function of PMA. The SIMS profile in Fig. 4(a) indicates that the [F] in W/TiN stack was increased after FGA and diffused into the SiO2 after a series of PMA. The F diffusion was noticed after the PMA at 650
Fig. 4. SIMS profile of (a) F and (b) Cl in the W/TiN/SiO2/Si stack with CVD-W and PMA.
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8C and then retarded at higher temperature. Fig. 4(b) also shows depth profiles of Cl with PMA, which is similar to the trends of [F]. The amount of [F] and [Cl] in SiO2 and SiO2/Si interface were increased about an order of magnitude at 650 8C and FGA, while the impurity level was the highest after PMA at 950 8C. The CET variation in Fig. 3 is well consistent with impurity behavior as shown in the SIMS profiles and the higher [F] can be responsible for the higher CET observed with CVD-W. For the extraction of the quantitative interface states or trap density (D it) with different W process, the C–V and conductance measurements were performed [15–18]. Shown in Fig. 5 are the C–V and conductance loss ( G m/ x)–gate voltage (V) curves [Fig. 5(a)] and the G m/x–log x [Fig. 5(b)] of the W/TiN/SiO2 (3 nm)/p-Si MOS structures without PMA. One may note that the C–V shift between the two curves is related with two different W processing, which was discussed in Fig. 2. In case of PVD-W, the higher conductance loss peaks are noticed from both G m/x–V curve and G m/x–log x curves. The level of conductance loss value with PVD-W is about 4 times higher than the one with CVD-W, exhibiting that near midgap D it value is four times higher for PVD-W split. It is evident that the PVD-W introduced higher fixed charges ( Q f), oxide trap charges, and interface traps, even though the W electrode was deposited on the 30-nm-thick CVD-TiN films. Fig. 6 summarizes the evolution of D it as determined by G m/x–log x curves with PMA. In brief, the D it level with CVD-W is lower than the one with PVD-W by a factor of two, which can be attributed to the plasma-free process and hydrogen passivation during deposition. The D it trends with PVD-W are easily understood. For example, the D it of aspatterned PVD-W/CVD-TiN is ~31011/eV cm2 and this level has reduced to ~11011/eV cm2 and ~81010/eV cm2 after FGA and PMA (950 8C)+FGA, respectively. It is worthwhile to reciting previous work on the D it results of PVD-W on PVD-TiN and CVD-TiN [11]. The D it level gated with as-patterned PVD-W/PVD-TiN stack is about five times higher than the one with PVD-W/CVD-TiN. The D it value (21012/eV cm2) of as-patterned PVD-W/PVD-
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Fig. 6. The D it level of the W/CVD-TiN/SiO2/p-Si MOS as a function of W deposition and PMA at the given gate voltage as determined by the conductance loss. The detailed conditions for thermal split are as follows; A: as-patterned, B: FGA (450 8C for 30 min), C: RTA 650 8C+FGA, D: RTA 800 8C+FGA, E: RTA 950 8C+FGA.
TiN was reduced to 31011/eV cm2 by the PMA at 450 8C and this was further improved by the combination of high temperature RTP and FGA. This trend is consistent with the present result of PVD-W/CVD-TiN, while the D it level was lower with CVD-TiN by a factor of two. On the other hand, the D it tendency with CVD-W is somewhat different. The lower D it (~51010/eV cm2) was obtained from the as-patterned CVD-W/TiN/SiO2/Si MOS capacitors and the D it increased to ~11011/eV cm2 after FGA. This D it level was further reduced by a series of RTA+FGA toward ~41010/eV cm2, in which the D it trend is similar to PVD-W. The low D it level (~51010/eV cm2) of as-patterned CVD-W is ascribed to plasma-free CVD-W process and hydrogen passivation of Si dangling bond during W and/or TiN deposition, in which hydrogen atoms are produced from SiH4 or NH3. The increased D it level after FGA, however, is not a common behavior and need more speculation for further understanding. The plausible
Fig. 5. (a) The C–V curves and conductance loss (G m/x)–gate voltage (V) of the W/TiN/SiO2 (3 nm)/p-Si MOS structures for a given frequency of 100 kHz and (b) conductance loss (G m/x)–log x of the W/TiN/SiO2 (3 nm)/p-Si MOS structures without anneal. The solid lines are for CVD-W and the dashed ones are for PVD-W. The applied gate voltages or surface potentials are also shown.
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Fig. 7. The J–V curves of the W/CVD-TiN/SiO2 (3 nm)/p-Si MOS structures as a function of PMA temperature; (a) PVD-W and (b) CVD-W.
sources of D it change for CVD-W can be related with impurity ([F], [Cl]) behaviors or stress change of W/TiN structure during thermal cycle, which need to be further clarified. The PMA with FGA done at higher temperature seems to be beneficial to passivate Si dangling bonds as evidenced by D it decrease. Fig. 7 depicts current density ( J)–voltage (V) characteristics of W/TiN/SiO2 (3 nm)/p-Si MOS capacitors as a function of W deposition and PMA temperature. The generic J–V characteristics are very the same for two different W depositions. The leakage current decreases with PMA at lower voltage range (b 1.3 V); however, the leakage current increases with PMA at high voltage range (N 1.3 V). The deteriorated leakage current behavior at high voltage field region (N 1.3 V) was consistent with the earlier work [11,12], at which the Cl-induced trap-sites in SiO2 were responsible. The leakage reduction at low voltage is noticeable after PMA at 800 8C+FGA, where the reduction of leakage current is much more pronounced with CVD-W after 950 8C+FGA. This is plausibly attributed to the increased CET as a result of fluorinated SiO2 as noticed from SIMS profile in Fig. 4(a). Shown in Fig. 8 are J–V characteristics with two different W depositions, showing almost identical J–V characteristics at 650 8C and 800 8C. From the identical J–V characteristics, it is expected that the higher CET value (~0.5 nm) for CVD-W after PMA at 800 8C may be resulted from the fluorinated SiO2 rather than the increased SiO2 thickness. For instance, lower effective permittivity (k) of fluorinated-SiO2 at the similar SiO2
thickness can be resulted in higher CET. It is worthwhile to mentioning that the J–V uniformity within the wafer is bad especially for CVD-W annealed at 950 8C (not shown). Fig. 9 exhibits the breakdown voltage (BV) of W/TiN/SiO2 (3 nm)/Si MOS capacitors as a function of W deposition and PMA. Interestingly, the breakdown voltage and the wear-out current levels are decreased with PMA temperature even with increased CET values regardless of W deposition. The BV of CVD-W after PMA at 950 8C showed non-uniform distribution with ~30% initial failure, which might be related with the poor J–V uniformity. Fig. 10 displays time-to-breakdown (T BD) of W/TiN/ SiO2 (3 nm)/Si MOS capacitor as determined by the constant current stress (CCS) condition of 1.2510 3 A/ cm2. The results showed that the T BD characteristics of the CVD-W samples were slightly degraded compared to those of PVD-W up to 650C (not shown), but those were seriously deteriorated with PMA at over 800 . The T BD characteristics of the MOS structure gated with CVD-W after PMA at 950 8C showed earlier failure and noticeable degradation compared to those of PVD-W samples, that was expected from the non-uniform BV distribution (Fig. 8). These nonuniform J–V and shorter T BD characteristics are plausibly resulted from the F related bulk defects in SiO2 or the Clrelated defect sites as further aggravated by the F incorporation. Moriwaki and Yamada [12] proposed a local defect spot in the SiO2 when used CVD-TiN due to the Clrelated trap-sites, which was observed only for thick SiO2 (5.6 nm) samples annealed at 1000 8C. Unfortunately we
Fig. 8. The J–V curves of the W/CVD-TiN/SiO2 (3 nm)/p-Si MOS structures as a function of W deposition at PMA temperature of (a) 650 8C+FGA and (b) 800 8C+FGA.
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Fig. 9. The breakdown voltage characteristics of the W/CVD-TiN/SiO2 (3 nm)/p-Si MOS structures as a function of W deposition and PMA temperature.
have not observed such a remarkable degradation from PVD-W/CVD-TiN/SiO2/Si stack probably because of the different SiO2 thickness range (~3 nm) experimented. However, as the fluorine has involved by replacing PVDW with CVD-W, a notable reliability worsening was observed by means of abnormal J–V, BV distribution and shorter T BD after PMA at 950 8C. Fig. 11 exhibits the T BD characteristics of W/TiN/SiO2 (3 nm)/Si MOS capacitors exposed to PMA at 800 8C under the constant voltage stress (CVS) condition. The general T BD characteristics are equivalent by means of similar T BD trends with same voltage applied; however, we need to normalize the applied voltage by CET for fair comparison. Shown in Fig. 12 is a projection of 10-year lifetime, i.e., mean time to failure (MTTF) versus applied field (MV/cm). The critical
Fig. 10. Time to breakdown characteristics of W/CVD-TiN/SiO2 (~3 nm)/pSi MOS structures at constant current density of 1.25e 3 A/cm2 as a function of W deposition and PMA temperature.
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Fig. 11. Time to breakdown characteristics of W/CVD-TiN/SiO2 (3 nm)/pSi MOS structures at constant voltage stress as a function of W deposition at a PMA temperature of 800 8C+FGA.
oxide field (E ox, critical) of over 10.1 MV/cm may be used with PVD-W/CVD-TiN electrode combination at room temperature, while the E ox, critical of 8.4 MV/cm can be used for CVD-W/CVD-TiN after PMA at 800 8C. For the low thermal budget devices (b650 8C) such as damascene gate or replacement gate structure, E ox, critical of over 11.3 MV/cm and 9.7 MV/cm may be used for PVD-W and CVD-W, respectively. It is obvious that the applied electric field at 10-year lifetime projection is higher with PVD-W
Fig. 12. 10-year lifetime of W/TiN/SiO2 (3 nm)/p-Si MOS structures with PMA measured at room temperature. Each data point represents mean time to failure (MTTF) of 40 data points on the 8-in. wafers. The critical oxide field, E ox, critical of over 10.1 MV/cm may be used with PVD-W/CVDTiN electrode combination at room temperature, while the E ox, critical of 8.4 MV/cm can be used for CVD-W/CVD-TiN after PMA at 800 8C. For the low thermal budget devices (b650 8C) such as damascene gate or replacement gate structure, E ox, critical of over 11.3 MV/cm and 9.7 MV/ cm may be used for PVD-W and CVD-W, respectively.
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than CVD-W for a given PMA temperature of 650 8C and 800 8C. The root cause of GOI degradation was strongly related with the impurity incorporation such as Cl and F, which should be minimized during deposition process.
4. Conclusion We evaluated the effects of F and Cl on the gate oxide integrity of W/TiN/SiO2 (3 nm)/Si metal–oxide–semiconductor (MOS) structure as a function of two different W deposition and post-metal anneal (PMA). CVD-W process induced higher CET increase with PMA, while lower D it and defect charges were generated. PVD-W generated the higher D it, fixed charges and oxide trap charges resulted from the damages in the SiO2 and at the SiO2/Si interface even on top of 30-nm-thick CVD-TiN. However, a noticeable degradation of gate oxide quality was observed with CVD-W by means of smaller breakdown field, lower charge to breakdown, and shorter lifetime. The reliability degradation was partially attributed to the Cl from the TiCl4 source, while more severe degradation was assigned to the F from WF6 source after the PMA at 650 8C and above. A deposition method to minimize the impurity concentration is necessary.
Acknowledgments The authors would like to thank Jung-Kyu Ko, Jae-Young Kim, Se-Aug Jang, Heung-Jae Cho, Kwan-Yong Lim, and Tae-Ho Cha for SIMS analyses and sample preparation.
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