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Au–Sb sandwich structure
Journal of Alloys and Compounds 484 (2009) 570–574
Contents lists available at ScienceDirect
Journal of Alloys and Compounds journal homepage: www.elsevier.com/locate/jallcom
Effects of thermal annealing on electrical characteristics of Cd/CdS/n-Si/Au–Sb sandwich structure M. Sa˘glam a,∗ , A. Ates¸ a , B. Güzeldir a , A. Astam a , M.A. Yıldırım b a b
Department of Physics, Faculty of Sciences and Arts, University of Atatürk, 25240 Erzurum, Turkey Department of Physics, Faculty of Education, University of Erzincan, Erzincan, Turkey
a r t i c l e
i n f o
Article history: Received 28 January 2009 Received in revised form 29 April 2009 Accepted 29 April 2009 Available online 6 May 2009 Keywords: SILAR method Sandwich structure CdS Series resistance Thermal annealing
a b s t r a c t In general, at the metal–semiconductor contacts, interfacial layers have been fabricated by different methods such as molecular beam epitaxy, metal organic chemical vapor deposition, sputtering and vacuum evaporation. However, all of these techniques have encountered various difficulties in the deposited films. Instead of these methods, since Successive Ionic Layer Adsorption and Reaction (SILAR) method is simple, fast, sensitive, and less costly to prepare interfacial layer, we have first employed this method in order to prepare Cd/CdS/n-Si/Au–Sb sandwich structure. For this reason, the CdS thin film has been directly formed on n-type Si substrate by means of SILAR method. The Cd/CdS/n-Si/Au–Sb sandwich structure has demonstrated clearly rectifying behaviour by the current–voltage (I–V) curves studied at room temperature. In order to observe the effect of the thermal annealing, this structure has been annealed at temperatures from 50 to 300 ◦ C for 3 min in N2 atmosphere. The characteristic parameters such as barrier height, ideality factor and series resistance of this structure have been calculated from the forward bias I–V characteristics as a function of annealing temperature with different methods. The values of n, ˚b and mean Rs of the initial Cd/CdS/n-Si/Au–Sb sandwich structure were found to be 2.31, 0.790 eV and 1.86 k respectively. After annealing at 300 ◦ C, these values were changed to 1.89, 0.765 eV and 0.48 k. It has been seen that the barrier height, ideality factor and series resistance have slightly changed with increasing annealing temperature up to 300 ◦ C. © 2009 Elsevier B.V. All rights reserved.
1. Introduction Metal-interfacial layer-semiconductor sandwich structures are of essential importance in semiconductor devices. Such sandwich structures with very thin interlayer behave electrically like Schottky contacts. The barrier heights of such devices depend on the nature of the interfacial layer, its thickness, and the specific metal used [1]. The electrical properties of metal-interfacial layer-semiconductor sandwich structures have been widely studied, both for their basic physical properties and for their technological applications to electronic devices. The thermal stability of the metal–semiconductor (M–S), metal-insulator-semiconductor (MIS) and metal-interfacial layer-semiconductor structures is of great practical importance in device technology owing to the subjection to elevated temperatures at some stage of the manufacturing process [2–14]. In practical, silicon devices in the interface region react with the deposited metals. This reaction may cause the generation of trap states due to the microscopic inhomogeneity of the Schottky barrier height. Therefore, the interface of Schottky diodes should carefully be analyzed
∗ Corresponding author. E-mail address: [email protected] (M. Sa˘glam). 0925-8388/$ – see front matter © 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.jallcom.2009.04.140
for the improvement of the device performance. In recent years, polycrystalline CdS thin films have received intensive attention due to the their very important role on the photovoltaic technology and optoelectronic devices. CdS thin film has been obtained by several methods, such as, electrodeposition, vacuum evaporation, screen printing, photochemical deposition, chemical bath deposition, spray pyrolysis, and sputtering. CdS thin film manufacture technology has been the subject of many papers [15–23], where more details about it can be seen. Up to now, much effort has been devoted to the preparation of metal-interfacial layersemiconductor structures. However, in the past, there has been no report on preparation of such structures by means of SILAR method. We report here how Cd/CdS/n-Si/Au–Sb sandwich structure has been prepared and the characteristic parameters of this structure have been calculated as a function of annealing temperature. In this study, a simple and economical technique for manufacturing of Cd/CdS/n-Si/Au–Sb sandwich structure has been presented and the effects of thermal annealing on the electrical characteristics of this structure have been investigated. One of the liquid phase methods for deposition of thin films is SILAR-method. The SILAR method has been developed by Nicolau for the deposition of zinc and cadmium chalcogenides thin films 20 years ago [24]. In this method, thin films are fabricated by alternate dipping into
M. Sa˘glam et al. / Journal of Alloys and Compounds 484 (2009) 570–574
571
where I0 is the saturation current derived from the straight line intercept of ln I at V = 0 and is given by:
q˚ b
I0 = AA∗ T 2 exp −
Fig. 1. The structure diagram of the fabricated device.
two solutions of each precursor ion for compound semiconductors. Therefore, the control of the film thickness becomes feasible by changing the number of the dipping cycles. Furthermore, atomically controlled multilayer thin films or super lattices can possibly be fabricated by changing precursor solutions. Since the SILAR method depends on only immersing the substrate into the solutions, the deposition of films with a large area can be achieved at low cost. The adsorption, reaction and rinsing times were chosen experimentally so that deposition occurred layer wise and resulted in homogeneous thin film structure [25]. We investigated electrical and thermal stability of the Cd/CdS/n-Si/Au–Sb sandwich structure by means of the I–V measurements in dark at room temperature. 2. Experimental procedures In this study, n-type Si(1 0 0) wafer which have resistivity of 1–10 -cm was used to fabricate Cd/CdS/n-Si/Au–Sb sandwich structure (see Fig. 1) and then, the n-Si wafer was chemically cleaned using the RCA cleaning procedure (i.e. 10 min boil in NH3 + H2 O2 + 6H2 O followed by a 10 min HCl + H2 O2 + 6H2 O at 60 ◦ C) before making contacts. Au–Sb alloy was selected to make ohmic contact. The ohmic contact was made by evaporating Au–Sb alloy on the back of the substrate, and then, it was annealed at 420 ◦ C for 3 min in N2 atmosphere. The native oxide on the front surface of the n-Si substrate was removed in HF + 10H2 O solution. Finally, it was rinsed in de-ionized water for 30 s and was dried. After ohmic contact made, the ohmic contact side and the edges of the n-Si semiconductor substrate was covered by wax so that the polished and cleaned front side of the sample was exposed to the cationic precursor solution (CdCl2 ) employed for SILAR method. For the deposition of CdS thin film, a well-cleaned n-type Si substrate was immersed in the cationic precursor solution (CdCl2 ) for 40 s, causing cadmium ions to be adsorbed on the surface of the n-type Si substrate. Following this process, the substrate was immersed in doubly distilled water for 50 s to prevent irregular precipitation. The substrate was finally immersed in the anionic precursor solution (Na2 S) for 40 s. Sulfide ions was reacted with the adsorbed cadmium ions on the n-type Si substrate. The substrate was then immersed in double-distilled water for 50 s. Thus, one cycle of CdS film deposition is completed. For homogeneous interface layer, this cycles have been repeated as 20 cycle. Cd dots with diameter of about 1.0 mm (the contact area = 7.85 × 10−3 cm2 ) were evaporated on the CdS layer by thermal resistive heating technique in an ultra high vacuum chamber. In this way, the Cd/CdS/n-Si/Au–Sb sandwich structure was obtained. The thickness of CdS layer was calculated as 299 nm approximately from high frequency capacitance–voltage measurements by using C = εεo /d equation. The I–V measurements of the device were performed at room temperature in dark, using a HP4140B picoampermeter. Moreover, in order to observe the effect of the thermal annealing, the Cd/CdS/n-Si/Au–Sb sandwich structure has been annealed at temperatures 50, 100, 150, 200, 250 and 300 ◦ C for 3 min in N2 atmosphere, respectively.
kT
(2)
where ˚b is effective barrier height at zero bias, Rs is the series resistance of the neutral region and IRs is the voltage drop across the series resistance, q is the electron charge, V is the applied voltage, k is the Boltzmann constant, T is the absolute temperature, A* is the effective Richardson constant of 112 A/cm2 K2 for n-type Si, A is the diode area, n is a well-known ideality factor that is a measure of conformity of the diode to pure thermionic emission. If ideality factor n is equal to one, pure thermionic emission is occurring. However, n usually has a value greater than unity and it is determined from the slope of the straight-line region of the semi-log forward bias I–V characteristics through the relation n=
q dV kT d(ln I)
(3)
The semi-log forward and reverse bias I–V plots of the Cd/CdS/nSi/Au–Sb sandwich structure are shown in Fig. 2 as a function of annealing temperature. It is shown in Fig. 2 that there is complete saturation for the reverse current. The barrier height (BH) ˚b and ideality factor n values of the Cd/CdS/n-Si/Au–Sb structure were calculated with the help of Eqs. (2) and (3) from the y-axis intercept and slope of the linear region of the semi-log-forward bias I–V plots, respectively. The values of the parameters obtained from these characteristics are given in Table 1. As shown in Table 1, the values of 2.31 and 0.790 eV for the ideality factor and barrier height of the non-annealed sample (as-deposited) were obtained, respectively. Besides, the ideality factor, n, was in the range of 1.89–2.31 showing a strong deviation from the thermionic emission theory. The high values of n can be attributed to the effects of the bias volt-
3. Results and discussion Such metal-thin interfacial layer-semiconductor structures behave electrically like Schottky contacts. If a Schottky diode with a series resistance is considered, it is assumed that the forward bias-thermionic emission current of the device can be expressed as [26]
q˚ b
I = AA∗ T 2 exp −
kT
exp
q
(V − IRs ) nkT
(1)
Fig. 2. The semi-log forward and reverse bias current–voltage characteristics of Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
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Table 1 The experimentally obtained from different methods ideality factor n, barrier height ˚b , saturation current I0 and series resistance Rs values as a function of annealing temperature for the Cd/CdS/n-Si/Au–Sb sandwich structure. Annealing temperature (◦ C)
I–V
As dept. 50 100 150 200 250 300
dV/d(ln I)–I
H(I)–I
F(V)–V
n
˚b (eV)
I0 (A)
n
Rs (k)
˚b (eV)
Rs (k)
˚b (eV)
Rs (k)
2.31 2.30 2.12 2.02 1.93 1.91 1.89
0.790 0.795 0.792 0.798 0.800 0.779 0.765
1.69 × 10−8 1.49 × 10−8 1.64 × 10−8 1.28 × 10−8 1.16 × 10−8 2.74 × 10−8 4.62 × 10−8
2.76 2.74 2.43 2.33 2.22 2.21 2.20
1.79 1.74 2.28 1.41 0.82 0.80 0.49
0.754 0.760 0.760 0.764 0.765 0.749 0.740
1.92 1.87 2.37 1.46 0.85 0.82 0.47
0.788 0.791 0.788 0.795 0.798 0.777 0.763
2.24 1.96 1.85 1.66 1.58 1.42 1.28
age drop across the interfacial layer and series resistance, therefore, of the bias voltage dependence of the barrier height. On the other hand, such as a thin interface insulator layer, probably the oxide layer (SiO2 or SiOx ), may be form natively at CdS and n-Si interface before forming the CdS layer (see Fig. 1). The image force effect, recombination-generation and tunneling may be possible mechanisms that could lead to an ideality factor value greater than unity [5]. It should be noted that the forward currents at a fixed voltage, consequently also the saturation currents I0 increase as the annealing temperature rises above 200 ◦ C. Similar phenomena are observed in the reverse characteristics. This implies a decrease in the barrier height by the annealing temperature according to Eq. (2). Several methods to extract the series resistance Rs of a Schottky diode have been suggested [7,27–28]. In our case, we have applied the methods developed by Cheung and Cheung [7] and Norde [27]. Now, to determine diode parameters such n, ˚b and Rs , let us obtain the functions of Cheung and Cheung [7]. From Eq. (1), the following functions can be written as: dV = IRs + n d (ln I) H(I) = V − n
kT
kT q
q ln
(4) I AA∗ T 2
(5)
and H(I) = IRs + n˚b
(6)
Eq. (4) should give a straight line for the data of downward curvature region in the semi-log forward bias I–V characteristics. Thus, the slope of the linear plot of the dV/d(ln I) versus I will give Rs and its y-axis intercept will give nq/kT. Using the n value determined from Eq. (4) and the data of downward curvature region in the semi-log forward bias I–V characteristics in Eq. (5), a plot of H(I) versus I according to Eq. (6) will also give a straight line with y-axis intercept equal to n˚b . The plots associated with these functions are given in Fig. 3 and Fig. 4 as a function of annealing temperature. The least-square fits were used in the draw of the curves related to series resistance. The values of the parameters obtained from these plots are given in Table 1. As seen in Table 1, the mean series resistance values of the Cd/CdS/n-Si/Au–Sb structure are varied from 1.86 to 0.48 k: barrier heights are decreased from 0.754 to 0.740 eV and ideality factors are decreased from 2.76 to 2.20 with increasing annealing temperature. It is seen that there is a good agreement between the values of the series resistance obtained from two Cheung plots. However, it can clearly be seen that there is a relatively a high difference between the values of the ideality factor obtained from the downward curvature region of forward bias I–V plots and from the linear regions of the same characteristics. The reason for this difference can be attributed to the existence of effects such as the series resistance and the bias dependence of the Schottky barrier height, according to the voltage drop across the interfacial layer and charge of the interface states with bias in this concave region of the I–V plot.
Fig. 3. Experimental dV/d(ln I)–I curves of Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
Alternatively, in order to calculate series resistance in the Schottky diode with high ideality factor and series resistance, we also used Norde method modified by Bohlin [27,28]. The Norde function, F(V), is defined as
Fig. 4. Experimental H(I)–I curves of Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
M. Sa˘glam et al. / Journal of Alloys and Compounds 484 (2009) 570–574
F (V ) =
V −
kT q
ln
I (V )
573
(7)
AA∗ T 2
where is an arbitrary constant greater than the ideality factor, I(V) is current obtained from the I–V curve and the other parameters are described above. Thus, the effective Schottky barrier height and series resistance can be determined by ˚b = Fm +
Rs = ( − n)
( − n) n kT qIm
V
m
−
kT q
(8) (9)
Once the minimum of the F(V)–V plot is determined, the Schottky barrier height can be obtained from here, where Fm is the minimum point of F(V) curve, and Vm is the corresponding voltage, Im is the current corresponds to the minimum Vm . Fig. 5 shows the F(V)–V plots of the Cd/CdS/n-Si/Au–Sb structure as a function of increasing annealing temperature. From the F(V)–V plots, the some parameters of the Cd/CdS/n-Si/Au–Sb sandwich structure (˚b , Rs ) have been determined and given in Table 1. From these F(V)–V curves, we found 0.788 and 0.763 eV and 2.24 and 1.28 k values for the barrier height and series resistance at as-deposited sample and at 300 ◦ C thermal annealed sample, respectively. Both barrier height and series resistance have been slightly changed with increasing annealing temperature. It can be said that, especially, the values of series resistance obtained from both methods are slightly different from each other. In most cases, the parameters obtained from Cheung functions and Norde’s functions are not in agreement with each other. Because, Cheung functions are only applied to the nonlinear region (high voltage region) of the semi-log forward bias I–V characteristics whereas, Norde’s functions are applied to the full forward bias I–V characteristics of the junctions. Figs. 6 and 7 summarizes the variation of barrier heights and ideality factors of Cd/CdS/n-Si/Au–Sb structure as-deposited and annealed temperature range of 50–300 ◦ C for 3 min in N2 atmosphere. It is seen from these plots that, especially, the ideality factors are slightly decreased from 2.31 to 1.89 with increasing annealing temperature (from forward bias I–V). Due to the decrease in the series resistance with increasing annealing temperature, the n val-
Fig. 5. Experimental F(V)–V curves of Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
Fig. 6. Experimental ideality factor versus annealing temperatures plots for Cd/CdS/n-Si/Au–Sb sandwich structure.
ues have been decreased with increasing annealing temperature. The values of n obtained from semi-log I–V characteristics are lower than obtained from Cheung’s method. In general, it is found that, these parameters far from ideal diode parameters at high voltage region (series resistance region) because there is a voltage drop in this region and this cause a non-ideal behaviour. Also, the values of the measured barrier height with three different methods remain almost constant up to 200 ◦ C. Fig. 8 shows the variation of the resistivity of Cd/CdS/n-Si/Au–Sb sandwich structure obtained from Cheung and Norde methods as a function of annealing temperature. It can be said that, especially, the values of series resistance obtained from both methods are approximately in agreement with each other. The series resistance of the sample has decreased with increasing annealing temperature. The reason for the lower resistivity of annealed Cd/CdS/n-Si/Au–Sb structure can be attributed to the reactions in the CdS/n-Si interface region due to temperature. This reaction can cause degrade of trap states, causing the improvement of the device performance.
Fig. 7. Experimental barrier height versus annealing temperatures plots for Cd/CdS/n-Si/Au–Sb sandwich structure.
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M. Sa˘glam et al. / Journal of Alloys and Compounds 484 (2009) 570–574
approaches to the initial value. In other words, the rectifying ratio of the device remains almost constant with thermal treatment. 4. Conclusions In this study, since SILAR method is simple, fast, sensitive, easy, and less costly, we prepared Cd/CdS/n-Si/Au–Sb sandwich structure by means of SILAR method and investigated the electrical and thermal stability of this structure by the I–V measurements. The values of the barrier height ˚b and the ideality factor n and series resistance Rs of Cd/CdS/n-Si/Au–Sb structure annealed in the temperature range of 50–300 ◦ C have been determined from the forward-bias ln I–V plots, Cheung plots and Norde plots, respectively. The barrier height and series resistance values calculated with two methods were compared and observed that there is an agreement between the two methods. It is seen that the characteristic parameters of this structure are not remarkably changed in the thermal annealing up to 300 ◦ C. Acknowledgments Fig. 8. Experimental series resistance versus annealing temperatures plots for Cd/CdS/n-Si/Au–Sb sandwich structure.
This work was supported by The Turkish Scientific and Technological Research Council of Turkey (TUBITAK) (Project No: 108T500). The Authors wish to thank to TUBITAK. Also, we would like thanks to Prof. Dr. S. Tüzemen for his assistance on improve of English version. References
Fig. 9. The rectifying ratio versus applied voltages for Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
According to Fig. 2, the variation of the rectifying ratio with respect to applied voltage can be given easily for Cd/CdS/n-Si/Au–Sb structure with increasing annealing temperature. The plot can be seen in Fig. 9. In this figure, the rectifying ratio has slightly decreased up to 150 ◦ C with respect to the as-deposited sample. Afterwards, as the annealing temperature increases further, the rectifying ratio
[1] W. Mönch, Semiconductor Surfaces and Interfaces, third ed., Springer-Verlag Press, 2001. [2] A. Van der Ziel, Solid State Physical Electronics, second ed., Prentice-Hall, New Jersey, 1968. [3] K.M. Yu, M. Jaklevic, E.E. Haller, Appl. Phys. A 44 (1987) 177–181. [4] S.M. Sze, Physics of Semiconductor Devices, second ed., Wiley, New York, 1981. [5] E.H. Rhoderick, R.H. Williams, Metal-Semiconductor Contacts, Clerendon Press, Oxford, 1988. [6] R.H. Williams, G.Y. Robinson, in: C.W. Wilmsen (Ed.), Physics and Chemistry of III–V Compound Semiconductor Interfaces, Plenum Press, New York, 1985. [7] S.K. Cheung, N.W. Cheung, Appl. Phys. Lett. 49 (1986) 85–87. [8] L.J. Brilson, in: L.J. Brilson (Ed.), Contacts to Semiconductors, Noyes Publication, New Jersey, 1993. [9] S. Zhu, R.L. Van Meirhaeghe, S. Forment, G. Ru, B. Li, Solid-State Electron. 48 (2004) 29–35. [10] C¸. Nuho˘glu, E. Ayyıldız, M. Sa˘glam, A. Türüt, Appl. Surf. Sci. 135 (1998) 350– 356. [11] E. Ayyıldız, M. Sa˘glam, C¸. Nuho˘glu, A. Türüt, Phys. Scripta 58 (1998) 636–639. [12] M. Sa˘glam, A. Türüt, Semicond. Sci. Technol. 12 (1997) 1028–1031. [13] C¸. Nuho˘glu, M. Sa˘glam, A. Türüt, Semicond. Sci. Technol. 14 (1999) 114–117. [14] B.L. Sharma, Metal-Semiconductor Schottky Barrier Junctions and Their Applications, Plenum Press, New York and London, 1984. [15] M.A. Green, Prog. Photovoltaics 9 (2001) 123–135. [16] P. Raji, C. Sanjeeviraja, K. Ramachandran, Bull. Mater. Sci. 28 (3) (2005) 233–238. [17] E.I. Ugwu, D.U. Onah, The Pacific J. Sci. Technol. 8 (1) (2007) 155–161. [18] X.L. Tong, D.S. Jiang, Z.M. Liu, M.Z. Luo, Y. Li, P.X. Lu, G. Yang, H. Long, Thin Solid Films 516 (2008) 2003–2008. [19] A. Ashour, J. Optoelectron. Adv. Mater. 8 (4) (2006) 1447–1451. [20] J. Barman, J.P. Borah, K.C. Sarma, Chalcogenide Lett. 5 (11) (2008) 265–271. [21] S.J. Ikhmayies, R.N. Ahmad-Bitar, Am. J. Appl. Sci. 5 (9) (2008) 1141–1143. [22] M. Thambidural, N. Murugan, N. Muthukumarasamy, S. vasantha, R. Balasundaraphu, S. Agilan, Chalcogenide Lett. 6 (4) (2009) 171–179. [23] G.L. Tan, J.H. Du, Q.J. Zhang, J. Alloys Compd. 468 (2009) 421–431. [24] Y.F. Nicolau, Appl. Surf. Sci. 22/23 (1985) 1061–1074. [25] M. Kundakci, A. Ates¸, A. Atsam, M. Yıldırım, Physica E 40 (2008) 600–605. [26] P. Chattopadhyay, B. RayChaudhuri, Solid-State Electron. 36 (1993) 605–610. [27] H. Norde, J. Appl. Phys. 50 (1979) 5052–5053. [28] K.E. Bohlin, J. Appl. Phys. 60 (1986) 1223–1224.
Contents lists available at ScienceDirect
Journal of Alloys and Compounds journal homepage: www.elsevier.com/locate/jallcom
Effects of thermal annealing on electrical characteristics of Cd/CdS/n-Si/Au–Sb sandwich structure M. Sa˘glam a,∗ , A. Ates¸ a , B. Güzeldir a , A. Astam a , M.A. Yıldırım b a b
Department of Physics, Faculty of Sciences and Arts, University of Atatürk, 25240 Erzurum, Turkey Department of Physics, Faculty of Education, University of Erzincan, Erzincan, Turkey
a r t i c l e
i n f o
Article history: Received 28 January 2009 Received in revised form 29 April 2009 Accepted 29 April 2009 Available online 6 May 2009 Keywords: SILAR method Sandwich structure CdS Series resistance Thermal annealing
a b s t r a c t In general, at the metal–semiconductor contacts, interfacial layers have been fabricated by different methods such as molecular beam epitaxy, metal organic chemical vapor deposition, sputtering and vacuum evaporation. However, all of these techniques have encountered various difficulties in the deposited films. Instead of these methods, since Successive Ionic Layer Adsorption and Reaction (SILAR) method is simple, fast, sensitive, and less costly to prepare interfacial layer, we have first employed this method in order to prepare Cd/CdS/n-Si/Au–Sb sandwich structure. For this reason, the CdS thin film has been directly formed on n-type Si substrate by means of SILAR method. The Cd/CdS/n-Si/Au–Sb sandwich structure has demonstrated clearly rectifying behaviour by the current–voltage (I–V) curves studied at room temperature. In order to observe the effect of the thermal annealing, this structure has been annealed at temperatures from 50 to 300 ◦ C for 3 min in N2 atmosphere. The characteristic parameters such as barrier height, ideality factor and series resistance of this structure have been calculated from the forward bias I–V characteristics as a function of annealing temperature with different methods. The values of n, ˚b and mean Rs of the initial Cd/CdS/n-Si/Au–Sb sandwich structure were found to be 2.31, 0.790 eV and 1.86 k respectively. After annealing at 300 ◦ C, these values were changed to 1.89, 0.765 eV and 0.48 k. It has been seen that the barrier height, ideality factor and series resistance have slightly changed with increasing annealing temperature up to 300 ◦ C. © 2009 Elsevier B.V. All rights reserved.
1. Introduction Metal-interfacial layer-semiconductor sandwich structures are of essential importance in semiconductor devices. Such sandwich structures with very thin interlayer behave electrically like Schottky contacts. The barrier heights of such devices depend on the nature of the interfacial layer, its thickness, and the specific metal used [1]. The electrical properties of metal-interfacial layer-semiconductor sandwich structures have been widely studied, both for their basic physical properties and for their technological applications to electronic devices. The thermal stability of the metal–semiconductor (M–S), metal-insulator-semiconductor (MIS) and metal-interfacial layer-semiconductor structures is of great practical importance in device technology owing to the subjection to elevated temperatures at some stage of the manufacturing process [2–14]. In practical, silicon devices in the interface region react with the deposited metals. This reaction may cause the generation of trap states due to the microscopic inhomogeneity of the Schottky barrier height. Therefore, the interface of Schottky diodes should carefully be analyzed
∗ Corresponding author. E-mail address: [email protected] (M. Sa˘glam). 0925-8388/$ – see front matter © 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.jallcom.2009.04.140
for the improvement of the device performance. In recent years, polycrystalline CdS thin films have received intensive attention due to the their very important role on the photovoltaic technology and optoelectronic devices. CdS thin film has been obtained by several methods, such as, electrodeposition, vacuum evaporation, screen printing, photochemical deposition, chemical bath deposition, spray pyrolysis, and sputtering. CdS thin film manufacture technology has been the subject of many papers [15–23], where more details about it can be seen. Up to now, much effort has been devoted to the preparation of metal-interfacial layersemiconductor structures. However, in the past, there has been no report on preparation of such structures by means of SILAR method. We report here how Cd/CdS/n-Si/Au–Sb sandwich structure has been prepared and the characteristic parameters of this structure have been calculated as a function of annealing temperature. In this study, a simple and economical technique for manufacturing of Cd/CdS/n-Si/Au–Sb sandwich structure has been presented and the effects of thermal annealing on the electrical characteristics of this structure have been investigated. One of the liquid phase methods for deposition of thin films is SILAR-method. The SILAR method has been developed by Nicolau for the deposition of zinc and cadmium chalcogenides thin films 20 years ago [24]. In this method, thin films are fabricated by alternate dipping into
M. Sa˘glam et al. / Journal of Alloys and Compounds 484 (2009) 570–574
571
where I0 is the saturation current derived from the straight line intercept of ln I at V = 0 and is given by:
q˚ b
I0 = AA∗ T 2 exp −
Fig. 1. The structure diagram of the fabricated device.
two solutions of each precursor ion for compound semiconductors. Therefore, the control of the film thickness becomes feasible by changing the number of the dipping cycles. Furthermore, atomically controlled multilayer thin films or super lattices can possibly be fabricated by changing precursor solutions. Since the SILAR method depends on only immersing the substrate into the solutions, the deposition of films with a large area can be achieved at low cost. The adsorption, reaction and rinsing times were chosen experimentally so that deposition occurred layer wise and resulted in homogeneous thin film structure [25]. We investigated electrical and thermal stability of the Cd/CdS/n-Si/Au–Sb sandwich structure by means of the I–V measurements in dark at room temperature. 2. Experimental procedures In this study, n-type Si(1 0 0) wafer which have resistivity of 1–10 -cm was used to fabricate Cd/CdS/n-Si/Au–Sb sandwich structure (see Fig. 1) and then, the n-Si wafer was chemically cleaned using the RCA cleaning procedure (i.e. 10 min boil in NH3 + H2 O2 + 6H2 O followed by a 10 min HCl + H2 O2 + 6H2 O at 60 ◦ C) before making contacts. Au–Sb alloy was selected to make ohmic contact. The ohmic contact was made by evaporating Au–Sb alloy on the back of the substrate, and then, it was annealed at 420 ◦ C for 3 min in N2 atmosphere. The native oxide on the front surface of the n-Si substrate was removed in HF + 10H2 O solution. Finally, it was rinsed in de-ionized water for 30 s and was dried. After ohmic contact made, the ohmic contact side and the edges of the n-Si semiconductor substrate was covered by wax so that the polished and cleaned front side of the sample was exposed to the cationic precursor solution (CdCl2 ) employed for SILAR method. For the deposition of CdS thin film, a well-cleaned n-type Si substrate was immersed in the cationic precursor solution (CdCl2 ) for 40 s, causing cadmium ions to be adsorbed on the surface of the n-type Si substrate. Following this process, the substrate was immersed in doubly distilled water for 50 s to prevent irregular precipitation. The substrate was finally immersed in the anionic precursor solution (Na2 S) for 40 s. Sulfide ions was reacted with the adsorbed cadmium ions on the n-type Si substrate. The substrate was then immersed in double-distilled water for 50 s. Thus, one cycle of CdS film deposition is completed. For homogeneous interface layer, this cycles have been repeated as 20 cycle. Cd dots with diameter of about 1.0 mm (the contact area = 7.85 × 10−3 cm2 ) were evaporated on the CdS layer by thermal resistive heating technique in an ultra high vacuum chamber. In this way, the Cd/CdS/n-Si/Au–Sb sandwich structure was obtained. The thickness of CdS layer was calculated as 299 nm approximately from high frequency capacitance–voltage measurements by using C = εεo /d equation. The I–V measurements of the device were performed at room temperature in dark, using a HP4140B picoampermeter. Moreover, in order to observe the effect of the thermal annealing, the Cd/CdS/n-Si/Au–Sb sandwich structure has been annealed at temperatures 50, 100, 150, 200, 250 and 300 ◦ C for 3 min in N2 atmosphere, respectively.
kT
(2)
where ˚b is effective barrier height at zero bias, Rs is the series resistance of the neutral region and IRs is the voltage drop across the series resistance, q is the electron charge, V is the applied voltage, k is the Boltzmann constant, T is the absolute temperature, A* is the effective Richardson constant of 112 A/cm2 K2 for n-type Si, A is the diode area, n is a well-known ideality factor that is a measure of conformity of the diode to pure thermionic emission. If ideality factor n is equal to one, pure thermionic emission is occurring. However, n usually has a value greater than unity and it is determined from the slope of the straight-line region of the semi-log forward bias I–V characteristics through the relation n=
q dV kT d(ln I)
(3)
The semi-log forward and reverse bias I–V plots of the Cd/CdS/nSi/Au–Sb sandwich structure are shown in Fig. 2 as a function of annealing temperature. It is shown in Fig. 2 that there is complete saturation for the reverse current. The barrier height (BH) ˚b and ideality factor n values of the Cd/CdS/n-Si/Au–Sb structure were calculated with the help of Eqs. (2) and (3) from the y-axis intercept and slope of the linear region of the semi-log-forward bias I–V plots, respectively. The values of the parameters obtained from these characteristics are given in Table 1. As shown in Table 1, the values of 2.31 and 0.790 eV for the ideality factor and barrier height of the non-annealed sample (as-deposited) were obtained, respectively. Besides, the ideality factor, n, was in the range of 1.89–2.31 showing a strong deviation from the thermionic emission theory. The high values of n can be attributed to the effects of the bias volt-
3. Results and discussion Such metal-thin interfacial layer-semiconductor structures behave electrically like Schottky contacts. If a Schottky diode with a series resistance is considered, it is assumed that the forward bias-thermionic emission current of the device can be expressed as [26]
q˚ b
I = AA∗ T 2 exp −
kT
exp
q
(V − IRs ) nkT
(1)
Fig. 2. The semi-log forward and reverse bias current–voltage characteristics of Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
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Table 1 The experimentally obtained from different methods ideality factor n, barrier height ˚b , saturation current I0 and series resistance Rs values as a function of annealing temperature for the Cd/CdS/n-Si/Au–Sb sandwich structure. Annealing temperature (◦ C)
I–V
As dept. 50 100 150 200 250 300
dV/d(ln I)–I
H(I)–I
F(V)–V
n
˚b (eV)
I0 (A)
n
Rs (k)
˚b (eV)
Rs (k)
˚b (eV)
Rs (k)
2.31 2.30 2.12 2.02 1.93 1.91 1.89
0.790 0.795 0.792 0.798 0.800 0.779 0.765
1.69 × 10−8 1.49 × 10−8 1.64 × 10−8 1.28 × 10−8 1.16 × 10−8 2.74 × 10−8 4.62 × 10−8
2.76 2.74 2.43 2.33 2.22 2.21 2.20
1.79 1.74 2.28 1.41 0.82 0.80 0.49
0.754 0.760 0.760 0.764 0.765 0.749 0.740
1.92 1.87 2.37 1.46 0.85 0.82 0.47
0.788 0.791 0.788 0.795 0.798 0.777 0.763
2.24 1.96 1.85 1.66 1.58 1.42 1.28
age drop across the interfacial layer and series resistance, therefore, of the bias voltage dependence of the barrier height. On the other hand, such as a thin interface insulator layer, probably the oxide layer (SiO2 or SiOx ), may be form natively at CdS and n-Si interface before forming the CdS layer (see Fig. 1). The image force effect, recombination-generation and tunneling may be possible mechanisms that could lead to an ideality factor value greater than unity [5]. It should be noted that the forward currents at a fixed voltage, consequently also the saturation currents I0 increase as the annealing temperature rises above 200 ◦ C. Similar phenomena are observed in the reverse characteristics. This implies a decrease in the barrier height by the annealing temperature according to Eq. (2). Several methods to extract the series resistance Rs of a Schottky diode have been suggested [7,27–28]. In our case, we have applied the methods developed by Cheung and Cheung [7] and Norde [27]. Now, to determine diode parameters such n, ˚b and Rs , let us obtain the functions of Cheung and Cheung [7]. From Eq. (1), the following functions can be written as: dV = IRs + n d (ln I) H(I) = V − n
kT
kT q
q ln
(4) I AA∗ T 2
(5)
and H(I) = IRs + n˚b
(6)
Eq. (4) should give a straight line for the data of downward curvature region in the semi-log forward bias I–V characteristics. Thus, the slope of the linear plot of the dV/d(ln I) versus I will give Rs and its y-axis intercept will give nq/kT. Using the n value determined from Eq. (4) and the data of downward curvature region in the semi-log forward bias I–V characteristics in Eq. (5), a plot of H(I) versus I according to Eq. (6) will also give a straight line with y-axis intercept equal to n˚b . The plots associated with these functions are given in Fig. 3 and Fig. 4 as a function of annealing temperature. The least-square fits were used in the draw of the curves related to series resistance. The values of the parameters obtained from these plots are given in Table 1. As seen in Table 1, the mean series resistance values of the Cd/CdS/n-Si/Au–Sb structure are varied from 1.86 to 0.48 k: barrier heights are decreased from 0.754 to 0.740 eV and ideality factors are decreased from 2.76 to 2.20 with increasing annealing temperature. It is seen that there is a good agreement between the values of the series resistance obtained from two Cheung plots. However, it can clearly be seen that there is a relatively a high difference between the values of the ideality factor obtained from the downward curvature region of forward bias I–V plots and from the linear regions of the same characteristics. The reason for this difference can be attributed to the existence of effects such as the series resistance and the bias dependence of the Schottky barrier height, according to the voltage drop across the interfacial layer and charge of the interface states with bias in this concave region of the I–V plot.
Fig. 3. Experimental dV/d(ln I)–I curves of Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
Alternatively, in order to calculate series resistance in the Schottky diode with high ideality factor and series resistance, we also used Norde method modified by Bohlin [27,28]. The Norde function, F(V), is defined as
Fig. 4. Experimental H(I)–I curves of Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
M. Sa˘glam et al. / Journal of Alloys and Compounds 484 (2009) 570–574
F (V ) =
V −
kT q
ln
I (V )
573
(7)
AA∗ T 2
where is an arbitrary constant greater than the ideality factor, I(V) is current obtained from the I–V curve and the other parameters are described above. Thus, the effective Schottky barrier height and series resistance can be determined by ˚b = Fm +
Rs = ( − n)
( − n) n kT qIm
V
m
−
kT q
(8) (9)
Once the minimum of the F(V)–V plot is determined, the Schottky barrier height can be obtained from here, where Fm is the minimum point of F(V) curve, and Vm is the corresponding voltage, Im is the current corresponds to the minimum Vm . Fig. 5 shows the F(V)–V plots of the Cd/CdS/n-Si/Au–Sb structure as a function of increasing annealing temperature. From the F(V)–V plots, the some parameters of the Cd/CdS/n-Si/Au–Sb sandwich structure (˚b , Rs ) have been determined and given in Table 1. From these F(V)–V curves, we found 0.788 and 0.763 eV and 2.24 and 1.28 k values for the barrier height and series resistance at as-deposited sample and at 300 ◦ C thermal annealed sample, respectively. Both barrier height and series resistance have been slightly changed with increasing annealing temperature. It can be said that, especially, the values of series resistance obtained from both methods are slightly different from each other. In most cases, the parameters obtained from Cheung functions and Norde’s functions are not in agreement with each other. Because, Cheung functions are only applied to the nonlinear region (high voltage region) of the semi-log forward bias I–V characteristics whereas, Norde’s functions are applied to the full forward bias I–V characteristics of the junctions. Figs. 6 and 7 summarizes the variation of barrier heights and ideality factors of Cd/CdS/n-Si/Au–Sb structure as-deposited and annealed temperature range of 50–300 ◦ C for 3 min in N2 atmosphere. It is seen from these plots that, especially, the ideality factors are slightly decreased from 2.31 to 1.89 with increasing annealing temperature (from forward bias I–V). Due to the decrease in the series resistance with increasing annealing temperature, the n val-
Fig. 5. Experimental F(V)–V curves of Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
Fig. 6. Experimental ideality factor versus annealing temperatures plots for Cd/CdS/n-Si/Au–Sb sandwich structure.
ues have been decreased with increasing annealing temperature. The values of n obtained from semi-log I–V characteristics are lower than obtained from Cheung’s method. In general, it is found that, these parameters far from ideal diode parameters at high voltage region (series resistance region) because there is a voltage drop in this region and this cause a non-ideal behaviour. Also, the values of the measured barrier height with three different methods remain almost constant up to 200 ◦ C. Fig. 8 shows the variation of the resistivity of Cd/CdS/n-Si/Au–Sb sandwich structure obtained from Cheung and Norde methods as a function of annealing temperature. It can be said that, especially, the values of series resistance obtained from both methods are approximately in agreement with each other. The series resistance of the sample has decreased with increasing annealing temperature. The reason for the lower resistivity of annealed Cd/CdS/n-Si/Au–Sb structure can be attributed to the reactions in the CdS/n-Si interface region due to temperature. This reaction can cause degrade of trap states, causing the improvement of the device performance.
Fig. 7. Experimental barrier height versus annealing temperatures plots for Cd/CdS/n-Si/Au–Sb sandwich structure.
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approaches to the initial value. In other words, the rectifying ratio of the device remains almost constant with thermal treatment. 4. Conclusions In this study, since SILAR method is simple, fast, sensitive, easy, and less costly, we prepared Cd/CdS/n-Si/Au–Sb sandwich structure by means of SILAR method and investigated the electrical and thermal stability of this structure by the I–V measurements. The values of the barrier height ˚b and the ideality factor n and series resistance Rs of Cd/CdS/n-Si/Au–Sb structure annealed in the temperature range of 50–300 ◦ C have been determined from the forward-bias ln I–V plots, Cheung plots and Norde plots, respectively. The barrier height and series resistance values calculated with two methods were compared and observed that there is an agreement between the two methods. It is seen that the characteristic parameters of this structure are not remarkably changed in the thermal annealing up to 300 ◦ C. Acknowledgments Fig. 8. Experimental series resistance versus annealing temperatures plots for Cd/CdS/n-Si/Au–Sb sandwich structure.
This work was supported by The Turkish Scientific and Technological Research Council of Turkey (TUBITAK) (Project No: 108T500). The Authors wish to thank to TUBITAK. Also, we would like thanks to Prof. Dr. S. Tüzemen for his assistance on improve of English version. References
Fig. 9. The rectifying ratio versus applied voltages for Cd/CdS/n-Si/Au–Sb sandwich structure as a function of annealing temperature.
According to Fig. 2, the variation of the rectifying ratio with respect to applied voltage can be given easily for Cd/CdS/n-Si/Au–Sb structure with increasing annealing temperature. The plot can be seen in Fig. 9. In this figure, the rectifying ratio has slightly decreased up to 150 ◦ C with respect to the as-deposited sample. Afterwards, as the annealing temperature increases further, the rectifying ratio
[1] W. Mönch, Semiconductor Surfaces and Interfaces, third ed., Springer-Verlag Press, 2001. [2] A. Van der Ziel, Solid State Physical Electronics, second ed., Prentice-Hall, New Jersey, 1968. [3] K.M. Yu, M. Jaklevic, E.E. Haller, Appl. Phys. A 44 (1987) 177–181. [4] S.M. Sze, Physics of Semiconductor Devices, second ed., Wiley, New York, 1981. [5] E.H. Rhoderick, R.H. Williams, Metal-Semiconductor Contacts, Clerendon Press, Oxford, 1988. [6] R.H. Williams, G.Y. Robinson, in: C.W. Wilmsen (Ed.), Physics and Chemistry of III–V Compound Semiconductor Interfaces, Plenum Press, New York, 1985. [7] S.K. Cheung, N.W. Cheung, Appl. Phys. Lett. 49 (1986) 85–87. [8] L.J. Brilson, in: L.J. Brilson (Ed.), Contacts to Semiconductors, Noyes Publication, New Jersey, 1993. [9] S. Zhu, R.L. Van Meirhaeghe, S. Forment, G. Ru, B. Li, Solid-State Electron. 48 (2004) 29–35. [10] C¸. Nuho˘glu, E. Ayyıldız, M. Sa˘glam, A. Türüt, Appl. Surf. Sci. 135 (1998) 350– 356. [11] E. Ayyıldız, M. Sa˘glam, C¸. Nuho˘glu, A. Türüt, Phys. Scripta 58 (1998) 636–639. [12] M. Sa˘glam, A. Türüt, Semicond. Sci. Technol. 12 (1997) 1028–1031. [13] C¸. Nuho˘glu, M. Sa˘glam, A. Türüt, Semicond. Sci. Technol. 14 (1999) 114–117. [14] B.L. Sharma, Metal-Semiconductor Schottky Barrier Junctions and Their Applications, Plenum Press, New York and London, 1984. [15] M.A. Green, Prog. Photovoltaics 9 (2001) 123–135. [16] P. Raji, C. Sanjeeviraja, K. Ramachandran, Bull. Mater. Sci. 28 (3) (2005) 233–238. [17] E.I. Ugwu, D.U. Onah, The Pacific J. Sci. Technol. 8 (1) (2007) 155–161. [18] X.L. Tong, D.S. Jiang, Z.M. Liu, M.Z. Luo, Y. Li, P.X. Lu, G. Yang, H. Long, Thin Solid Films 516 (2008) 2003–2008. [19] A. Ashour, J. Optoelectron. Adv. Mater. 8 (4) (2006) 1447–1451. [20] J. Barman, J.P. Borah, K.C. Sarma, Chalcogenide Lett. 5 (11) (2008) 265–271. [21] S.J. Ikhmayies, R.N. Ahmad-Bitar, Am. J. Appl. Sci. 5 (9) (2008) 1141–1143. [22] M. Thambidural, N. Murugan, N. Muthukumarasamy, S. vasantha, R. Balasundaraphu, S. Agilan, Chalcogenide Lett. 6 (4) (2009) 171–179. [23] G.L. Tan, J.H. Du, Q.J. Zhang, J. Alloys Compd. 468 (2009) 421–431. [24] Y.F. Nicolau, Appl. Surf. Sci. 22/23 (1985) 1061–1074. [25] M. Kundakci, A. Ates¸, A. Atsam, M. Yıldırım, Physica E 40 (2008) 600–605. [26] P. Chattopadhyay, B. RayChaudhuri, Solid-State Electron. 36 (1993) 605–610. [27] H. Norde, J. Appl. Phys. 50 (1979) 5052–5053. [28] K.E. Bohlin, J. Appl. Phys. 60 (1986) 1223–1224.