Electrical characteristics and reliability properties of metal–oxide–semiconductor capacitors with HfZrLaO gate dielectrics

Microelectronics Reliability 50 (2010) 599–602

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Electrical characteristics and reliability properties of metal–oxide–semiconductor capacitors with HfZrLaO gate dielectrics C.H. Liu *, H.W. Chen Dept. of Mechatronic Technology, National Taiwan Normal University, No. 162, Sec. 1, He-Ping E. Rd., Taipei 106, Taiwan

a r t i c l e

i n f o

Article history: Received 25 November 2009 Received in revised form 7 January 2010 Available online 12 February 2010

a b s t r a c t Metal–oxide–semiconductor (MOS) capacitors incorporating atomic-layer-deposition (ALD) HfZrLaO high-j gate dielectric were fabricated and investigated. The equivalent oxide thickness (EOT) is 0.68 nm and the gate leakage current density (Jg) is only 9.3  101 A/cm2. The time-dependence dielectric breakdown (TDDB) behavior agrees with the percolation model, and the TDDB characteristics are consistent with the thermochemical E-model for lifetime projection. The experimental results show that the Weibull slopes are almost independent of capacitor area and stress conditions. The field acceleration parameter (c) and activation energy (DH0) are determined around 5.9–7.0 cm/MV and 0.54–0.60 eV, respectively. At 85 °C, the maximum voltage projected for 10-years TDDB lifetime is 1.87 V. Ó 2010 Elsevier Ltd. All rights reserved.

1. Introduction In the literatures, hafnium dioxide (HfO2) gate dielectrics have encountered the following process integration related problems: (1) low crystallization temperature (500 °C); (2) high threshold voltages (VT) for n- and p-MOSFETs, which is due to the so-called Fermi-level pinning (FLP) [1,2] or flat-band voltage (VFB) rolloff [3,4]. Researchers have introduced Si, N, Al, or Ta into HfO2 thin films in an attempt to increase the crystallization temperature and solve unacceptable VT issue [5–8]. Although the above additives can improve crystallization temperature and obtain low VT for metal–oxide–semiconductor field-effect-transistors (MOSFETs), the dielectric constants and the barrier heights at gate/dielectric or dielectric/substrate decrease significantly compared to pure HfO2 [9]. More recently, rare earth metal La (lanthanum) incorporation into HfO2 gate dielectrics has been successfully demonstrated to achieve desired device characteristics with low VT, increased crystallization temperature without degradation of dielectric constant, relatively high barrier height at metal gate and high-j gate dielectric interface, and improved positive bias temperature instability (PBTI) reliability [10–14]. Another approach to solve the HfO2 problems is to adding Zr (zirconium). It was reported that HfZrO (hafnium zirconate) has lower n-channel MOSFETs VT, higher transconductance, lower charge trapping density and interface trap density, higher drive current, reduced capacitance–voltage (C–V) hysteresis, superior wafer-level thickness uniformity, and improved PBTI reliability [15–17]. * Corresponding author. Tel.: +886 2 77343515; fax: +886 2 23583074. E-mail address: [email protected] (C.H. Liu). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.01.014

In order to obtain a better gate oxide dielectric, to combine the additives of La and Zr is a worthy attempt. Therefore, in this study we reveal a process for making HfZrLaO thin films and then investigate their electrical characteristics. In addition, time-dependentdielectric breakdown (TDDB) reliability is one major concern in advanced technology. It has not yet been fully understood for Hfbased high-j dielectrics, especially for HfZrLaO gate dielectrics. Hence, this work also investigates the TDDB characteristics of HfZrLaO high-j/metal gate stack structures. 2. Experiment P-type (1 0 0) Si wafers were used as the starting substrates. After the standard cleaning procedures, a 2-nm HfZrO thin film was first deposited by using atomic-layer-deposition (ALD), followed by 1-nm ALD LaO capping layer. A 10-nm TaC metal gate was subsequently deposited by physical vapor deposition (PVD) as the gate electrode. Finally, a post-metal-anneal (PMA) was done at 420 °C in forming gas for 30 min. The areas of the MOS capacitors range from 9.0  107 to 3.0  103 cm2. Based on capacitance–voltage (C–V) measurements, the equivalent oxide thickness (EOT) and flat-band voltage (VFB) are extracted from capacitance–voltage-capacitor (CVC) model of North Carolina State University (NCSU) with quantum effects taken into account. Constant voltage stress (CVS) with a negative bias on the top gate (gate injection) is applied to investigate the TDDB characteristics of HfZrLaO high-j gate dielectrics. The C–V, current–voltage (I–V) and, current–time (J–t) measurements of TaC/HfZrLaO/p-Si MOS capacitors were carried out through Agilent 4284A precision LCR Meter and Agilent 4156C semiconductor parameter analyzer.

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1×10-1

3.5

-5

100k Hz

3

-7

2

2

Area=9.5×10 cm

Area=1.0×10 cm

Simulation -2

1×10

EOT = 0.68 nm 2.5

Jg (A/cm )

V FB = -0.91 V

2

2

Capacitance (µF/cm2)

Tac/HfZrLaO/p-Si capacitor

TaC/HfZrLaO/p-Si cpacitor

= 17.2 11

1.5

-1

-2

D it~6.6×10 eV -cm

1

1×10-3

1×10-4

0.5

Stress condition: Vg = -2.65 V at 25ºC 0 -1.6

-1.2

-0.8

-0.4

0

1×10-5

0.4

0

50

100

150

Gate Voltage (V) Fig. 1. C–V characteristics of TaC/HfZrLaO/p-Si capacitors. The inset shows the structure of the samples.

300

2

2

-4

Stress conditions:Vg = -2.65 V at 25ºC

2

1×10 cm

1

5×10 -4 cm2

1×100

-5

2

0

ln[-ln(1-F)]

1×10 cm 2

250

Fig. 3. The Jg–t plot of TaC/HfZrLaO/p-Si capacitors with various areas stressed at Vg = 2.65 V.

1×10

Jg (A/cm )

200

Stress Time (s)

1×10-2

1×10-4

Area = 9.5×10

-7

cm

Area = 3.1×10

-6

2

cm

2

-1

-2

-3 1×10-6 -4 1×10-8

-6

-4

-2

0

-5

1

Electric Field (MV/cm) Fig. 2. J–E plot of TaC/HfZrLaO/p-Si capacitors with different areas. The inset further compares the Jg (Vg @ VFB  1 V) versus EOT characteristics among SiO2, HfO2, HfSiON, HfAlO, HfZrO4, and HfZrLaO (this work).

3. Results and discussion 3.1. Electrical characteristics of MOS capacitors with HfZrLaO gate dielectric The inset in Fig. 1 illustrates the stacking of TaC/LaO/HfZrO/p-Si capacitors in this article. Based on process sequence, however, it is believed that mutual diffusion of LaO and HfZrO have occurred such that certain form of mixing and bonding is generated after annealing [13,14]. Therefore, the gate dielectric is name HfZrLaO hereafter although it is not accurately correct stoichiometrically. Fig. 1 shows the high-frequency (100 kHz) and simulated C–V characteristics of MOS capacitor with HfZrLaO thin film. The dielectric constant and EOT are determined to be about 17.2 and 0.68 nm, respectively. According to International Technology Roadmap for Semiconductors (ITRS), an EOT of 0.68 nm can be applied to 36nm-node CMOS technology with 14-nm gate length [18]. The density of interface trap per area and energy (Dit) is also extracted to be about 6.6  1011 eV1 cm2 near midgap using Terman method [19]. Fig. 2 shows the gate leakage density–electrical field (Jg – E) characteristics for MOS capacitors with different areas and it shows that the gate current density (Jg) is independent of device areas. In addition, the Jg of the TaC/HfZrLaO/p-Si capacitor with 0.68 nm EOT

10

100

1000

Normalized TBD (s) Fig. 4. Normalized Weibull distributions of TaC/HfZrLaO/p-Si capacitors with various areas stressed at Vg = 2.65 V.

is about 9.3  101 (A/cm2) at VFB  1 V. The Jg is about 4–5 orders of magnitude smaller than that of SiO2-gated MOS capacitors [20]. The inset of Fig. 2 compares the Jg (Jg = Vg at VFB  1 V) versus EOT characteristics among HfSiON [5], HfO2 [15], HfZrO4 [15], SiO2 [20], HfAlO/SiON [21], and HfZrLaO (this work). The lower Jg means that HfZrLaO high-j gate dielectric has potential scalability for current and future advanced gate dielectric applications. 3.2. Time-dependent-dielectric-breakdown (TDDB) properties of MOS capacitors with HfZrLaO gate dielectric To study the breakdown characteristics of the HfZrLaO gate dielectric, CVS tests were carried out using MOS capacitors. It’s well known that the time-to-breakdown (TBD) is statistically distributed and it can be described by the Weibull distribution [22],

"   # b t ; FðtÞ ¼ 1  exp  t 63 WðtÞ ¼ ln½ lnð1  FÞ ¼ b ln

ð1Þ 

t

t63

 ;

ð2Þ

where F(t) denotes the function of cumulative fraction of breakdown devices, t represents the variable of time-to-breakdown, b is the Weibull slope, and t63 corresponds to the scale factor (or characteristic lifetime) of the distribution.

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8

Vg = -2.55 V,

H0 = 0.60 eV

Vg = -2.60 V,

H0 = 0.56 eV

Vg = -2.65 V,

H0 = 0.54 eV

7 0

-2

-4

Area=1.0×10 -5cm2

Vg = -2.65 V, = 1.62

0.6

4 3

p0 =2.86 eÅ

0.58 0.56 0.54

y = 0.1833x + 2.1593 R2 = 0.9966

0.52 0.5

Area=9.5×10 -7cm2

Vg = -2.60 V, = 1.62

1

10

1000

-9

-8.8

-8.6

-8.4

Electric field (MV/cm)

Vg = -2.55 V, = 1.65 -8 0.1

E a (eV) = -0.1833E OX + 2.1593

0.62

2

Vg = -2.65 V, = 1.64 -6

0.64

5

E a (eV)

ln(TBD @ 63.2% CDF)

ln[-ln(1-F)]

6

0 100000

0

1

2

TBD (s) Fig. 5. The TDDB Weibull distributions of TaC/HfZrLaO/p-Si capacitors with various areas under different stress voltages.

3

4

1000/T (K -1) Fig. 7. Arrhenius plot of TBD. The inset is the dependence of TDDB activation energy on oxide field.

1×1010

2

10-year lifetime 1

Time to breakdown (s)

1×108

ln[-ln(1-F)]

0

-1

-2

25

, = 1.64

-3

55

, = 1.62

85

-4

Vg = -2.65 V, Area=9.5×10 -5 0.1

1

10

100

cm

6

1×106

4

1×10

y = 5.8956x + 53.079 R2 = 0.9953

2 25 85

0 -8.9

-8.8

-8.7

-8.6

-8.5

-8.4

E (MV/cm)

2

1000

y = 7.0206x + 66.567 R2 = 0.9963

4

1×102

, = 1.68 -7

8

10000

1×100 -9

TBD (s)

-6

-3

0

Electric Field (MV/cm)

Fig. 6. The TDDB Weibull distributions of TaC/HfZrLaO/p-Si capacitors at different temperatures.

Fig. 8. TBD is plotted as a function of electric filed. The inset is the ln (t63) as a function of electric field.

For example, the gate leakage current density-stressed time (Jg–t) characteristics of the TaC/HfZrLaO/p-Si capacitors with various areas are shown in Fig. 3, where time-to-breakdown (TBD) is defined as hard breakdown (HBD) occurs. Fig. 4 shows the area-scaled Weibull distributions of different capacitor areas (Ax) normalized to those of 9.5  107 cm2 samples (Anorm) by multiplying ln (Ax/Anorm). The normalized Weibull distributions of two different capacitor areas match to a single line means that the breakdown is intrinsic and can be explained by percolation model [22]. Fig. 5 shows the TDDB Weibull distributions of different capacitor areas under various stress voltages at room temperature. A very similar Weibull slope (b) is obtained for all distributions. On the other hand, Fig. 6 shows the Weibull distributions at various temperatures. A very similar Weibull slope (b) is also obtained for all distributions. The basically parallel slopes indicate that the Weibull slopes are almost independent of stress voltage, capacitor area, and temperature as well as Dy2O3 [23], La2O3 [24], and SiO2 [25] gate dielectric. As we analyze the TDDB data of the HfZrLaO gate dielectric under gate injection, the thermochemical breakdown E-model has been adopted and can be expressed as [26–29]

Table 1 Some important parameters of ALD LaO/HfZrO stacked thin films. Gate oxide

LaO/HfZrO

EOT (nm) Jg (A/cm2) Dit (cm2 eV1) EBD,acc. (MV/cm) DH0 (eV) DH0 (eV) c (cm/MV) E10-years at 85 °C (MV/cm)

0.68 9.3  101 6.6  1011 12.5 0.54–0.60 2.16 5.9–7.0 5.6

DH 0  cEox ; kB T   2þj DH0 ¼ DH0  p0 Eox ; 3 lnðT BD Þ /

ð3Þ ð4Þ

where TBD is the time-to-breakdown, DH0 is the enthalpy of activation for bond breakage, kB = 1.38  1023 J/K is the Boltzmann’s constant, T is the absolute temperature, c is the field acceleration parameter, Eox is the externally applied electric field, DH0 is the

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activation energy in the absence of field, p0 is the molecular dipolemoment component opposite to local field, and j is the dielectric constant. The DH0 is determined from the Arrhenius plot of the 63.2% cumulative-distribution-failure (CDF) of TBD, as shown in Fig. 7. The extracted DH0 values are in the range of 0.54–0.60 eV. The inset of Fig. 7 shows DH0 versus electric-field characteristics and the DH0 and p0 can be determined to be about 2.16 eV and 2.86 eÅ, respectively. Fig. 8 shows the TDDB dependence on electric field, in which the thermochemical breakdown E-model has been adopted. Through the use of Eqs. (3) and (4), the c are extracted in the range of 5.9–7.0 cm/MV. From the inset of Fig. 8, c decreases slightly with increasing temperature, as expected [26,27]. From Fig. 8, Vg = 1.87 V (or equivalently 5.6 MV/cm) is projected to yield 10-years TDDB lifetime at normal operation of 85 °C. Table 1 summarizes some important parameters of this work. 4. Conclusions In summary, MOS capacitors with novel HfZrLaO gate dielectrics were fabricated and extensively investigated. The breakdown behavior agrees with the percolation model, and the TDDB characteristics are consistent with the thermochemical E-model for lifetime projection. It was observed that the Weibull slopes were almost independent of capacitor area, stress voltage and temperature. The c, DH0, DH0 , and p0 are determined about 5.9–7.0 cm/MV, 0.54–0.60 eV, 2.16 eV, and 2.86 eÅ, respectively. At 85 °C, the maximum voltage projected to have 10-years TDDB lifetime is 1.87 V. The excellent electrical properties and TDDB characteristics indicate that this La-incorporated HfZrO (HfZrLaO) gate dielectric has outstanding scalability for current and future complementary MOS (CMOS) applications. Acknowledgements The authors would like to acknowledge Prof. S.Y. Chen and Prof. H.S. Huang at NTUT and Dr. L.W. Cheng at UMC for informative discussions.

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