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Electrical characteristics related to silicon film thickness in advanced FD SOI–MOSFETs
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Solid-State Electronics 52 (2008) 126–133 www.elsevier.com/locate/sse
Electrical characteristics related to silicon film thickness in advanced FD SOI–MOSFETs A. Ohata a
a,*
, M. Casse´ b, O. Faynot
b
IMEP, Minatec – INPG, 3 Parvis Louis Ne´el, BP 257, 38016 Grenoble Cedex 1, France b CEA Le´ti-MINATEC, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France
Received 13 February 2007; received in revised form 7 July 2007; accepted 23 July 2007 Available online 18 September 2007
The review of this paper was arranged by Prof. E. Calleja
Abstract The impact of silicon-on-insulator (SOI) thinning on electrical characteristics is investigated for various SOI impurity concentrations, and for advanced structures with TiN gates and HfO2 gate dielectrics. It is experimentally and theoretically verified that the SOI film thickness that influences the quantum-confinement effect when the thickness decreases, clearly depends on the impurity concentration of SOI. However, once the quantum-confinement effect of the channel associated with SOI thinning occurs, the subband structure depends weakly on the SOI impurity concentration. Furthermore, the mobility in ultra-thin SOI–MOSFETs with HfO2 gate dielectrics and TiN gates is investigated. It is shown that the mobility of both the front and back channels is reduced, particularly, in the low electron density region. In addition, the mobility exhibits considerable variations in this region. These variations do not correspond to the variations in SOI thickness or gate-oxide thickness. The results suggest that they are due to the variations in the Coulomb scattering centers. 2007 Elsevier Ltd. All rights reserved. Keywords: MOSFET; SOI; Ultra-thin silicon; HfO2; Metal gate
1. Introduction Thin fully-depleted silicon-on-insulator (SOI) MOSFETs are promising candidates for a deca-nano-scaled MOSFET structure [1]. SOI thickness (TSi) is a key parameter for scaling because the short-channel effect can be suppressed by reducing it; therefore, an ultra-thin SOI film is required [2]. In addition, new materials for gate and gate insulator instead of poly-Si gate and SiO2 gate insulator are required for scaling [3]. Although poly-Si depletion reduces the nominal gate control, this can be avoided by using a metal gate. If a gate material with a work function close to the midgap is used, the manufacturing processes for *
Corresponding author. E-mail address: [email protected] (A. Ohata).
0038-1101/$ - see front matter 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.07.028
both n- and p-channel devices are simplified. Moreover, high-k gate dielectrics allow the scaling of the gate oxide while maintaining a low leakage current. However, the effect of SOI thickness on electrical characteristics has been studied only for limited parameters of SOI films or structures [4–9]. Furthermore, the effect of using new materials for the gate and gate insulator, combined with an ultra-thin body has not been discussed. In addition, the role of Coulomb scattering associated with trapped charges or interface states in low-doped Si, which will be used only for SOI structures in deca-nano-scaled devices, is large compared with that in high-doped Si. Since it has been reported that Coulomb scattering significantly reduces mobility in bulk MOSFETs with high impurity Si substrates owing to the integration of high-k gate dielectrics and metal gates, it is crucial to study the effect of
A. Ohata et al. / Solid-State Electronics 52 (2008) 126–133
integrating them in low-doped SOI films on electrical characteristics [10,11]. In this paper, we investigate the effect of SOI thinning on transport with respect to various SOI impurity concentrations and ultra-thin SOI n-MOSFETs having a TiN gate and HfO2 gate dielectric. 2. Quantum-confinement effect of ultra-thin SOI with various impurity concentrations Phonon-limited mobility depends on TSi because of the changes in the occupancy of valleys having different conductive mass, inversion-layer thickness, and subband energy splitting. These occur due to the modulation of the two-dimensional (2D) subband structure associated with SOI film thinning [12]. In order to investigate these effects for various SOI impurity concentrations, we calculated the subband structure of p-type SOI films for various TSi values, using 1D-Poisson–Schrodinger solver (Schred) [13,14]. Fig. 1a and b show the occupancy ratio in the lowest twofold valleys and the energy levels of the lowest twofold and fourfold valleys at the electron density Ns = 3 · 1012 cm2 for an SOI with a device structure as shown. In bulk or thick SOI, the occupancy ratio of the twofold valleys increases with the impurity concentration of the SOI film. This is due to the increase in the energy difference between twofold and fourfold valleys because of the high electric field at the surface. Fig. 1c shows the average distance of the electron from the interface (Zav). Since the electron mobility limited by the intra-valley phonon scattering for 2D electrons decreases with the inversionlayer thickness [12], the mobility decreases when TSi limits Zav. TSi first influences the wave function of the electrons in fourfold valleys because the Zav in fourfold valleys is longer than that in the twofold valleys. Fig. 1 shows that, in high-doped devices with SOI thicknesses greater than 10 nm, the subband structures are not influenced by the quantum confinement effect associated with SOI thinning, while in low-doped SOIs, they are influenced in this region, i.e., the occupancy ratio in the lowest twofold valleys slightly increases and Zav decreases with TSi in low-doped SOIs. Even when the electron density increases (Ns = 7 · 1012 cm2) in high-doped SOI, i.e., the occupancy ratio in fourfold valleys increases, it is not influenced in this TSi region. In 5 nm SOI, the occupancy ratio does not depend on the impurity concentration. This reflects the fact that the subband structure depends weakly on the impurity concentration, as shown in Fig. 1b, since it is limited by TSi. Although a metal gate having a work function close to the midgap is used, these characteristics remain similar, as indicated by the closed symbols in Fig. 1a and c. These results show that for an SOI thickness of approximately 10–15 nm, the electrical characteristics in highdoped SOIs are not affected by the quantum-confinement effect associated with SOI film thinning, while its effect
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induces the mobility decrease with TSi in low-doped SOIs as shown in several studies on non-doped SOIs [7]. In fact, our experimental results using SOI n-MOSFETs with TSi = 10–15 nm and high-doped SOIs having Na = 4 · 1017 cm3 show that mobility does not depend on TSi (Fig. 2). In these SOI devices, back-channel mobility does not depend on TSi either, as previously reported in [15]. Therefore, it can be concluded that the electrical characteristics in SOI–MOSFETs with thicknesses ranging from 10 nm to 15 nm and high-doped SOIs are not affected by the quantum-confinement effect associated with SOI film thinning. Furthermore, in these high-doped devices, once the interface between buried oxide and SOI is inverted by applying a large positive back-gate voltage (Vg2), the transconductance peak becomes constant, as shown in Fig. 3. This implies that front-channel mobility is not modulated by the inversion layer in the back channel, and the two channels are independent. This is consistent with the result that the SOI film is not sufficiently thin to modulate a subband structure. It can be concluded that these devices have no mobility enhancement effect when both channels are inverted [16].
3. Mobility in ultra-thin SOI–MOSFETs with metal gates and high-k gate dielectrics 3.1. Experimental method N-channel SOI devices were fabricated on standard UNIBOND SOI wafers using several advanced technologies. The superficial silicon was thinned down by successive thermal oxidation and oxide wet-etching. The thickness of the buried oxide was 145 nm. The targeted HfO2 layer using atomic-layer deposition had a thickness of 3 nm. The gate electrode was formed by chemical vapor deposition of TiN and capped with poly-Si. A transmission electron microscopy (TEM) image of the final device shows the thickness of the HfO2 (T HfO2 ) and interfacial SiO2 layers (T SiO2 ) to be 3 nm and 1.4 nm, respectively. The TiN thickness is approximately 10 nm, determined from a TEM image. The main process for introducing new materials for the metal gate and gate insulator is the same as the previously reported one [11]. The transistor channel was left undoped, with a p-type background concentration (Na = 1 · 1016 cm3). All the devices were probed on the same wafer, in which thickness variations were locally induced by the inherent material and process fluctuations. This enabled us to compare the effect of thickness variations while excluding the impact of different CMOS manufacturing processes. In order to evaluate the electrical characteristics of ultrathin SOI–MOSFETs, it is important to accurately determine TSi. In our devices, electrical characteristics such as the threshold voltage or drain current exhibited variations because of the charge trappings in the high-k gate
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Fig. 1. Calculated electron-occupancy ratio in the lowest twofold valleys (a) and the energy levels of the lowest twofold and fourfold valleys (b) as a function of SOI thickness when the electron density is Ns = 3 · 1012 cm2. The schematic figure shows the device structure used for the simulation. The parameters considered are the impurity concentration (Na) of the SOI film and SOI thickness (TSi). The back-gate voltage is 0 V. Open symbol: poly-Si gate. Closed symbol: metal gate. + denotes the case for Ns = 7 · 1012 cm2 and Na = 4 · 1017 cm3. The energy in (b) is measured with respect to the P conduction band (c) The average distance of the electron (Zav) from the interface calculated by i N i zi =N s , where R edge 2at the interface. P 2 N s ¼ i N i ; zi ¼ zj1i ðzÞj dz=j1i ðzÞj dz, Ni is the sheet density of the two-dimensional electron gas of the subband Ei, and 1i is the wave function (see [14] for the details).
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Fig. 2. Front-channel mobility versus effective field (Eeff) for doped (Na = 4 · 1017 cm3) SOI films. TSi = 13.6 nm and 11.6 nm. The SiO2 gate-oxide thickness is 2 nm, and the buried-oxide thickness is 400 nm. The gate material is n-type poly-Si. The back gate voltage is 0 V. L = W = 100 lm.
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where Cox and CBOX denote the gate oxide and BOX capacitances, respectively. We evaluated VT2 as theVg2 value that yields Ns = 3 · 1011 cm2 using the front-gate splitCV method (see [19] for the details). If we use the capacitance value measured using the split-CV measurement as Cox in Eq. (1), TSi is underestimated because the measured capacitance values decrease owing to the inversion-layer capacitances (Cinv). The results simulated using Schred indicated that the Cox value determined from the physical gate-oxide thickness is 23% larger at Ns = 1 · 1013 cm2 than that determined by electrical measurement, and that the difference in Cinv at Ns = 1 · 1013 cm2 in the range of TSi = 7 10 nm, is less than 0.5%. Therefore, we evaluated TSi by using Eq. (1) and the value of 1.23 · Cox converted from the Cox value measured using the split-CV measurement for each device. Further, we measured the electron density and mobility of the front and back channels by the front-gate split-CV method on long and wide devices (L = W = 10 lm). 3.2. Experimental results
Fig. 3. Channel transconductance versus gate voltage with the back-gate bias (Vg2) as a parameter in doped (4 · 1017 cm3) 15-nm-thick SOI nMOSFET. Once the back channel is created by applying the large backgate voltage (Vg2), the transconductance peak around Vg1 = 0.7 V is independent of Vg2. L = W = 100 lm. The inset shows the transconductance peak versus Vg2.
dielectrics. Therefore, the TSi value determined from the relationship between the threshold voltage of the back channel (VT2) and the front-gate voltage (Vg1) [17] resulted in more accurate TSi. TSi is given by the relationship DVT2/ DVg1 as follows [18]: 1 eSi DV T2 eSi T Si ¼ ; ð1Þ C BOX DV g1 C ox
3.2.1. Front-channel mobility at the interface of SOI and high-k gate dielectric In high-k gate dielectric MOSFETs, the hysteresis of the drain current induced by charge trappings could lead to the misevaluation of electrical characteristics [20]. In our devices, a small hysteresis appears if the gate voltage is swept from a large negative value (e.g., from 1 V to 1 V), while it disappears if it is swept across a narrow gate voltage range (from 0.5 V to 1 V). However, the hysteresis is so small that we can neglect this effect for our main results. Fig. 4a and b show Id–Vg1 and the mobility of the front channel for the different devices (Table 1) on the same wafer. Table 1 shows the capacitance value Co per unit area at Vg1 = VT1 + 1.06 V, and the TSi determined using Eq. (1) and the converted value from Co, as described above. The threshold voltage of the front channel (VT1) and the back channel (VT2) is also shown in this table. Device D has a low threshold voltage. This type of sudden shift to a low threshold voltage and the subsequent recovery is observed frequently. However, these slow-trapped charges do not affect mobility, as indicated by the data for device D in Fig. 4b, although the loss of mobility in all samples is clearly observed. It should be noted that the mobility increases with electron density in the range of Ns = 1 2 · 1012 cm3, although in the poly-Si/SiO2 structures with non-doped SOI films, the mobility decreases with the increase in the electron density, as shown in several studies [7,9]. It is apparently shown in Fig. 4c that the front-channel mobility in the poly-Si/SiO2 structure decreases with the increase in the electron density. This is because the contribution of Coulomb scattering associated with the impurity of SOI film or interface states to the mobility reduction is small due to the screening effect in these conditions, and phonon
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Fig. 4. (a) Drain current versus gate voltage and (b) front-channel mobility versus electron density at Vg2 = 0 V in SOI–MOSFETs with TiN gates and HfO2 gate dielectrics. The average of the source (Is) and drain (Id) currents, (Is + Id)/2, was used as a correction for the front-channel current to compensate the gate leakage current. (c) Back-channel mobility in SOI–MOSFETs with TiN gates and HfO2 gate dielectrics at Vg1 = 0.1 V (L = W = 10 lm) and the mobility of the front (Vg2 = 0 V) and back channels (Vg1: · 1.1 V, c 1.2 V) in a 10.3-nm-thick, non-doped SOI n-MOSFET with a poly-Si gate and SiO2 (9 nm) gate insulator (L = 10 lm, W = 50 lm). The back-channel mobility for B, C, and E from the devices in Table 1 are indicated; this is because other devices were broken by the application of a large Vg2. In the device with a poly-Si gate and SiO2 gate insulator, the back-channel mobility is smaller than the front-channel mobility at the same electron density because the effective field in the back channel is larger than that in the front channel.
scattering is the main mobility limiting factor. This difference suggests that in our samples with TiN gates and HfO2 gate dielectrics, Coulomb scattering is enhanced and is the main limiting factor in this Ns region. Indeed, soft-phonon limited mobility, which is another possible mechanism for mobility reduction caused by integrating the HfO2 gate dielectric and TiN gate, is expected to decrease with the increase in Ns and is effective in the large Ns region [21]. Moreover, in the region where the mobility increases with Ns, the mobility value depends on the samples, and exhibits considerable variations. This fact strongly suggests that these variations are caused by the variations in the Coulomb scattering centers. In order to confirm this, we discuss the relationship between the variations in the mobility and other physical parameters. In our devices with SOI thicknesses ranging from 7 nm to 10 nm, the mobility is expected to decrease with TSi owing to the quantum-confinement effect associated with SOI thinning. However, the mobility does not exhibit a clear relation with TSi, as shown in Fig. 4b. Table 1 shows the SiO2 thickness (ESiO2 ) and HfO2 thickness (EHfO2 ) evaluated from Co, assuming that the variation in Co is caused by the variations in T SiO2 under constant T HfO2 and in T HfO2 under constant T SiO2 , respectively. The 1-nm variation in EHfO2 in Table 1 cannot cause mobility variation, as reported in the previous study [11]. A variation of a few angstroms in ESiO2 can affect the mobility since remote charges at the interface between HfO2 and interfacial SiO2 layers (IFL) significantly reduce the mobility [11] in addition to the Coulomb scattering centers at the interface between SOIs and IFL or in IFL. The experimental results do not exhibit a clear relation between the variations in mobility and ESiO2 , implying that it is not the main factor. In addition, the TiN thickness could vary. However, these variations are expected to affect the mobility reduction in a wide range of Ns [22], i.e., it differs from our results. Therefore, although further research using mass data is necessary, these results suggest the possibility that variations in Coulomb scattering centers induced by the integration of high-k gate dielectrics or metal gates cause these mobility variations. Fig. 5 shows VT1 and VT2 versus TSi. The variation in VT1 does not correspond to that in Tinv as shown in Table 1, and VT1 does not depend on TSi, while VT2 clearly increases as TSi decreases. In non-doped devices with thicknesses of 7–10 nm, both of them are expected to increase as TSi decreases owing to the quantum-confinement effect associated with SOI thinning, as previously reported [4,9]. This fact may also reflect the variation in trapped charges around the energy level near VT1, some of which can be the Coulomb scattering centers. 3.2.2. Back-channel mobility at the interface of SOI and buried SiO2 Fig. 4c shows the back-channel mobility for B, C, and E and the front- and back-channel mobility in the poly-Si/
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Table 1 Capacitance value (Co) per unit area at Vg1 = VT1 + 1.06 V, TSi determined by using Eq. (1) and the value of 1.23 · Co (see details in the text), threshold voltage of the front channel (VT1) at Vg2 = 0 V, threshold voltage of the back channel (VT2) at Vg1 = 0.1 V, and inversion thickness (Tinv) determined from Co Device
Co (F/m2)
TSi (nm)
VT1 (V)
VT2 (V)
Tinv (nm)
EHfO2 (nm)
ESiO2 (nm)
A B C D E F
0.0153 0.0155 0.0158 0.0159 0.0158 0.0173
7.0 7.2 7.3 7.5 8.0 9.2
0.369 0.375 0.348 0.245 0.353 0.358
20.4 20.3 19.9 15.8 19.1 14.3
2.3 2.2 2.2 2.2 2.2 2.0
2.8 2.6 2.4 2.3 2.4 1.4
1.4 1.3 1.3 1.3 1.3 1.2
Ns is approximately 1 · 1013 cm2 at V g1 = VT1 + 1.06 V. VT1 at Vg2 = 0 V is determined as the voltage that yields Ns = 3 · 1011 cm2 using the split-CV method. Since VT2 at Vg1 = 0.1 V cannot be determined directly, it was determined as the value of VT2 at Vg1 = 0.1 V for the function VT2(Vg1), which was obtained as the Vg2 value yielding Ns = 3 · 1011 cm2 (see [19] for the details) by using the front-gate split-CV method. EHfO2 and ESiO2 are the equivalent HfO2 thickness and SiO2 thickness, determined from Co values under the assumption of constant T SiO2 (1.4 nm) and T HfO2 (3 nm), respectively; T T HfO2 ð3 nmÞ ð1:4 nmÞ 1 1 and ESiO2 ¼ eSiO2 1:23C . When EHfO2 and ESiO2 are estimated using these equations, the value of EHfO2 ¼ eHfO2 ðj¼25Þ 1:23C SiOe2SiO eHfO o o ðj¼25Þ 2
2
primitive constant j for HfO2 does not affect significantly the variations in EHfO2 or ESiO2 , i.e., DEHfO2 6 1:5 nm and DESiO2 6 0:2 nm for 20 6 j 6 25.
Fig. 5. Threshold voltage of the front (VT1) and back (VT2) channels versus SOI thickness. VT1 and VT2 for D decrease temporarily because of the slowtrapped charges.
SiO2 structure with non-doped SOI. Note that the backchannel mobility also increases with the electron density in the range of Ns = 1–2 · 1012 cm3, although, in the poly-Si/SiO2 structure with non-doped SOI film, the mobility of the front and back channels decreases with the increase in the electron density. This suggests that the Coulomb scattering is enhanced even in the back channel. The electron density for evaluating mobility is often overestimated because of the effect of parasitic capacitance [23]. Although devices with wide and long channels were used in order to avoid this effect, it must be reexamined, because the parasitic capacitances between the Si substrate and source/drain cause overestimation of the capacitance value in back-channel measurement. Fig. 6 shows the capacitance measured by the split-CV method at a high
voltage Vg2. Although a constant value, such as 0.01 pF or 0.05 pF, was deducted from each capacitance value in order to eliminate the effect of parasitic capacitance, back-channel mobility still increases with electron density, as shown in Fig. 6. These results show that the back-channel mobility is apparently reduced, and the contribution of Coulomb scattering is rather large, even for back-channel mobility. Thus, this implies that the introduction of new materials to the gate and gate insulator influences backchannel mobility as well. This result is different from our previous result in [24], evaluated using an ultra-thin SOI–MOSFET with a TaSiN gate and HfO2 gate dielectric, i.e., back-channel mobility follows the universal mobility curve and decreases with the increase in the electron density in the range of
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ness. Although further research using mass data is necessary, these results suggest that they are due to variations in the Coulomb scattering centers induced by the integration of the new materials. Acknowledgments Special thanks are due to our colleagues S. Cristoloveanu, F. Balestra, and X. Mescot for total support. References
Fig. 6. Back-channel mobility versus electron density for device C measured by the front-gate split-CV method at Vg2 = 28, at which the back channel is inverted.
Ns = 1–2 · 1012 cm3. In that study, the TSi was 17.5 nm and the thickness of IFL under the high-k dielectric was 2.5 nm. This difference suggests the possibility that using a TiN, thin IFL, thin SOI film, or the combined effects of these factors might reduce the back-channel mobility. The strong dependence of the back-channel mobility on Ns suggests the contribution of the Coulomb scattering associated with charges in a high-k gate structure. In addition, since, in the samples of this study, the subband structure could be affected by TSi and the wave function of the electron could spread across the entire film, as explained in Section 2, a high-k gate dielectric could cause a reduction in back-channel mobility. These results suggest that the mobility may be affected not only by the nearest gate or gate insulator but also by the other gates or gate insulators in multi-gate structures with thin non-doped bodies. 4. Summary The impact of SOI thinning on transport is investigated for various SOI impurity concentrations. It is experimentally and theoretically verified that TSi that influences the quantum-confinement effect, clearly depends on the impurity concentration of SOI. However, once the quantumconfinement effect of the channel associated with SOI thinning occurs, the subband structure depends weakly on the SOI impurity concentration. Furthermore, the mobility in ultra-thin SOI–MOSFETs with HfO2 gate dielectrics and TiN gates was investigated. It was shown that the mobility of both the front and back channels is reduced, particularly, in the low electron density region. The results suggest that it is due to enhanced Coulomb scattering. Furthermore, the mobility exhibits considerable variations in this region. These variations do not correspond to the variations in SOI or gate-oxide thick-
[1] International Technology Roadmap for Semiconductors: SEMATECH. [2] Chau R, Kavalieros J, Doyle B, Murthy M, Paulsen N, Lionberger D. A 50 nm depleted-substrate CMOS transistor (DST). IEDM; 2001. p. 621–4. [3] Vandooren A, Barr A, Mathew L, White T, Egley S, et al. Fullydepleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions. IEEE Electron Device Lett 2003;24:342–4. [4] Omura Y, Horiguchi S, Tabe M, Kishi K. Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFET’s. IEEE Electron Device Lett 1993;14:569–71. [5] Sherony MJ, Su LT, Chung JE, Antoniasis DA. SOI MOSFET effective channel mobility. IEEE Electron Device Lett 1995;16:100–2. [6] Toriumi A, Koga J, Satake H, Ohata A. Performance and reliability concerns of ultra-thin SOI and ultra-thin gate oxide MOSFETs. In: Tech. Dig. Int. Electron Devices Meet.; 1995. p. 847–50. [7] Esseni D, Mastrapasqua M, Celler GK, Fiegna C, Selmi L, Sangiorgi E. Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application. IEEE Trans Electron Devices 2001;48:2842–50. [8] Ernst T, Cristoloveanu S, Ghibaudo G, Ouisse T, Horiguchi S, Ono Y, et al. Ultimately thin double-gate SOI MOSFETs. IEEE Trans Electron Devices 2003;50:830–5. [9] Uchida K, Koga J, Ohba R, Numata T, Takagi S. Experimental evidences of quantum-mechanical effect on low-field mobility, gatechannel capacitance, and threshold voltage of ultrathin body SOI MOSFETs. In: Tech. Dig. Int. Electron Devices Meet.; 2001. p. 633– 6. [10] Saito SI, Torii K, Hiratani M, Onai T. Improved theory for remotecharge-scattering-limited mobility in metal-oxide-semiconductor transistors. Appl Phys Lett 2002;81:2391. [11] Casse´ M, Thevenod L, Guillaumot B, et al. Carrier transport in HfO2/metal gate MOSFETs: physical insight into critical parameters. IEEE Trans on Electron Devices 2006;53:759–68. [12] Takagi S, Koga J, Toriumi A. Subband structure engineering for performance enhancement of Si MOSFETs. In: IEDM Tech. Dig.; 1997. p. 219–21. [13]
A. Ohata et al. / Solid-State Electronics 52 (2008) 126–133 [19] Ohata A, Cristoloveanu S, Casse´ M. Front and back channel mobility in ultrathin SOI–MOSFETs by front-gate split CV method. Solid State Electron 2007;51(2):245–51. [20] Kerber A, Cartier E, Ragnarsson LA, Rosmeulen M, Pantisano L, Degraeve R et al. Direct measurement of the inversion charge in MOSFETs: application to mobility extraction in alternative gate dielectrics. In: Symp. VLSI Tech. Dig., Kyoto, Japan; 2003. p. 159– 60. [21] Datta S, Dewey G, Doczy M, Doyle B, Kavalieros J, Kotlyar R et al. High mobility Si/SiGe strained channel MOS transistors with HfO2/ TiN gate stack. In: IEDM Tech. Dig.; 2003. p. 28.1.1–4.
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Solid-State Electronics 52 (2008) 126–133 www.elsevier.com/locate/sse
Electrical characteristics related to silicon film thickness in advanced FD SOI–MOSFETs A. Ohata a
a,*
, M. Casse´ b, O. Faynot
b
IMEP, Minatec – INPG, 3 Parvis Louis Ne´el, BP 257, 38016 Grenoble Cedex 1, France b CEA Le´ti-MINATEC, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France
Received 13 February 2007; received in revised form 7 July 2007; accepted 23 July 2007 Available online 18 September 2007
The review of this paper was arranged by Prof. E. Calleja
Abstract The impact of silicon-on-insulator (SOI) thinning on electrical characteristics is investigated for various SOI impurity concentrations, and for advanced structures with TiN gates and HfO2 gate dielectrics. It is experimentally and theoretically verified that the SOI film thickness that influences the quantum-confinement effect when the thickness decreases, clearly depends on the impurity concentration of SOI. However, once the quantum-confinement effect of the channel associated with SOI thinning occurs, the subband structure depends weakly on the SOI impurity concentration. Furthermore, the mobility in ultra-thin SOI–MOSFETs with HfO2 gate dielectrics and TiN gates is investigated. It is shown that the mobility of both the front and back channels is reduced, particularly, in the low electron density region. In addition, the mobility exhibits considerable variations in this region. These variations do not correspond to the variations in SOI thickness or gate-oxide thickness. The results suggest that they are due to the variations in the Coulomb scattering centers. 2007 Elsevier Ltd. All rights reserved. Keywords: MOSFET; SOI; Ultra-thin silicon; HfO2; Metal gate
1. Introduction Thin fully-depleted silicon-on-insulator (SOI) MOSFETs are promising candidates for a deca-nano-scaled MOSFET structure [1]. SOI thickness (TSi) is a key parameter for scaling because the short-channel effect can be suppressed by reducing it; therefore, an ultra-thin SOI film is required [2]. In addition, new materials for gate and gate insulator instead of poly-Si gate and SiO2 gate insulator are required for scaling [3]. Although poly-Si depletion reduces the nominal gate control, this can be avoided by using a metal gate. If a gate material with a work function close to the midgap is used, the manufacturing processes for *
Corresponding author. E-mail address: [email protected] (A. Ohata).
0038-1101/$ - see front matter 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.07.028
both n- and p-channel devices are simplified. Moreover, high-k gate dielectrics allow the scaling of the gate oxide while maintaining a low leakage current. However, the effect of SOI thickness on electrical characteristics has been studied only for limited parameters of SOI films or structures [4–9]. Furthermore, the effect of using new materials for the gate and gate insulator, combined with an ultra-thin body has not been discussed. In addition, the role of Coulomb scattering associated with trapped charges or interface states in low-doped Si, which will be used only for SOI structures in deca-nano-scaled devices, is large compared with that in high-doped Si. Since it has been reported that Coulomb scattering significantly reduces mobility in bulk MOSFETs with high impurity Si substrates owing to the integration of high-k gate dielectrics and metal gates, it is crucial to study the effect of
A. Ohata et al. / Solid-State Electronics 52 (2008) 126–133
integrating them in low-doped SOI films on electrical characteristics [10,11]. In this paper, we investigate the effect of SOI thinning on transport with respect to various SOI impurity concentrations and ultra-thin SOI n-MOSFETs having a TiN gate and HfO2 gate dielectric. 2. Quantum-confinement effect of ultra-thin SOI with various impurity concentrations Phonon-limited mobility depends on TSi because of the changes in the occupancy of valleys having different conductive mass, inversion-layer thickness, and subband energy splitting. These occur due to the modulation of the two-dimensional (2D) subband structure associated with SOI film thinning [12]. In order to investigate these effects for various SOI impurity concentrations, we calculated the subband structure of p-type SOI films for various TSi values, using 1D-Poisson–Schrodinger solver (Schred) [13,14]. Fig. 1a and b show the occupancy ratio in the lowest twofold valleys and the energy levels of the lowest twofold and fourfold valleys at the electron density Ns = 3 · 1012 cm2 for an SOI with a device structure as shown. In bulk or thick SOI, the occupancy ratio of the twofold valleys increases with the impurity concentration of the SOI film. This is due to the increase in the energy difference between twofold and fourfold valleys because of the high electric field at the surface. Fig. 1c shows the average distance of the electron from the interface (Zav). Since the electron mobility limited by the intra-valley phonon scattering for 2D electrons decreases with the inversionlayer thickness [12], the mobility decreases when TSi limits Zav. TSi first influences the wave function of the electrons in fourfold valleys because the Zav in fourfold valleys is longer than that in the twofold valleys. Fig. 1 shows that, in high-doped devices with SOI thicknesses greater than 10 nm, the subband structures are not influenced by the quantum confinement effect associated with SOI thinning, while in low-doped SOIs, they are influenced in this region, i.e., the occupancy ratio in the lowest twofold valleys slightly increases and Zav decreases with TSi in low-doped SOIs. Even when the electron density increases (Ns = 7 · 1012 cm2) in high-doped SOI, i.e., the occupancy ratio in fourfold valleys increases, it is not influenced in this TSi region. In 5 nm SOI, the occupancy ratio does not depend on the impurity concentration. This reflects the fact that the subband structure depends weakly on the impurity concentration, as shown in Fig. 1b, since it is limited by TSi. Although a metal gate having a work function close to the midgap is used, these characteristics remain similar, as indicated by the closed symbols in Fig. 1a and c. These results show that for an SOI thickness of approximately 10–15 nm, the electrical characteristics in highdoped SOIs are not affected by the quantum-confinement effect associated with SOI film thinning, while its effect
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induces the mobility decrease with TSi in low-doped SOIs as shown in several studies on non-doped SOIs [7]. In fact, our experimental results using SOI n-MOSFETs with TSi = 10–15 nm and high-doped SOIs having Na = 4 · 1017 cm3 show that mobility does not depend on TSi (Fig. 2). In these SOI devices, back-channel mobility does not depend on TSi either, as previously reported in [15]. Therefore, it can be concluded that the electrical characteristics in SOI–MOSFETs with thicknesses ranging from 10 nm to 15 nm and high-doped SOIs are not affected by the quantum-confinement effect associated with SOI film thinning. Furthermore, in these high-doped devices, once the interface between buried oxide and SOI is inverted by applying a large positive back-gate voltage (Vg2), the transconductance peak becomes constant, as shown in Fig. 3. This implies that front-channel mobility is not modulated by the inversion layer in the back channel, and the two channels are independent. This is consistent with the result that the SOI film is not sufficiently thin to modulate a subband structure. It can be concluded that these devices have no mobility enhancement effect when both channels are inverted [16].
3. Mobility in ultra-thin SOI–MOSFETs with metal gates and high-k gate dielectrics 3.1. Experimental method N-channel SOI devices were fabricated on standard UNIBOND SOI wafers using several advanced technologies. The superficial silicon was thinned down by successive thermal oxidation and oxide wet-etching. The thickness of the buried oxide was 145 nm. The targeted HfO2 layer using atomic-layer deposition had a thickness of 3 nm. The gate electrode was formed by chemical vapor deposition of TiN and capped with poly-Si. A transmission electron microscopy (TEM) image of the final device shows the thickness of the HfO2 (T HfO2 ) and interfacial SiO2 layers (T SiO2 ) to be 3 nm and 1.4 nm, respectively. The TiN thickness is approximately 10 nm, determined from a TEM image. The main process for introducing new materials for the metal gate and gate insulator is the same as the previously reported one [11]. The transistor channel was left undoped, with a p-type background concentration (Na = 1 · 1016 cm3). All the devices were probed on the same wafer, in which thickness variations were locally induced by the inherent material and process fluctuations. This enabled us to compare the effect of thickness variations while excluding the impact of different CMOS manufacturing processes. In order to evaluate the electrical characteristics of ultrathin SOI–MOSFETs, it is important to accurately determine TSi. In our devices, electrical characteristics such as the threshold voltage or drain current exhibited variations because of the charge trappings in the high-k gate
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Fig. 1. Calculated electron-occupancy ratio in the lowest twofold valleys (a) and the energy levels of the lowest twofold and fourfold valleys (b) as a function of SOI thickness when the electron density is Ns = 3 · 1012 cm2. The schematic figure shows the device structure used for the simulation. The parameters considered are the impurity concentration (Na) of the SOI film and SOI thickness (TSi). The back-gate voltage is 0 V. Open symbol: poly-Si gate. Closed symbol: metal gate. + denotes the case for Ns = 7 · 1012 cm2 and Na = 4 · 1017 cm3. The energy in (b) is measured with respect to the P conduction band (c) The average distance of the electron (Zav) from the interface calculated by i N i zi =N s , where R edge 2at the interface. P 2 N s ¼ i N i ; zi ¼ zj1i ðzÞj dz=j1i ðzÞj dz, Ni is the sheet density of the two-dimensional electron gas of the subband Ei, and 1i is the wave function (see [14] for the details).
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Fig. 2. Front-channel mobility versus effective field (Eeff) for doped (Na = 4 · 1017 cm3) SOI films. TSi = 13.6 nm and 11.6 nm. The SiO2 gate-oxide thickness is 2 nm, and the buried-oxide thickness is 400 nm. The gate material is n-type poly-Si. The back gate voltage is 0 V. L = W = 100 lm.
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where Cox and CBOX denote the gate oxide and BOX capacitances, respectively. We evaluated VT2 as theVg2 value that yields Ns = 3 · 1011 cm2 using the front-gate splitCV method (see [19] for the details). If we use the capacitance value measured using the split-CV measurement as Cox in Eq. (1), TSi is underestimated because the measured capacitance values decrease owing to the inversion-layer capacitances (Cinv). The results simulated using Schred indicated that the Cox value determined from the physical gate-oxide thickness is 23% larger at Ns = 1 · 1013 cm2 than that determined by electrical measurement, and that the difference in Cinv at Ns = 1 · 1013 cm2 in the range of TSi = 7 10 nm, is less than 0.5%. Therefore, we evaluated TSi by using Eq. (1) and the value of 1.23 · Cox converted from the Cox value measured using the split-CV measurement for each device. Further, we measured the electron density and mobility of the front and back channels by the front-gate split-CV method on long and wide devices (L = W = 10 lm). 3.2. Experimental results
Fig. 3. Channel transconductance versus gate voltage with the back-gate bias (Vg2) as a parameter in doped (4 · 1017 cm3) 15-nm-thick SOI nMOSFET. Once the back channel is created by applying the large backgate voltage (Vg2), the transconductance peak around Vg1 = 0.7 V is independent of Vg2. L = W = 100 lm. The inset shows the transconductance peak versus Vg2.
dielectrics. Therefore, the TSi value determined from the relationship between the threshold voltage of the back channel (VT2) and the front-gate voltage (Vg1) [17] resulted in more accurate TSi. TSi is given by the relationship DVT2/ DVg1 as follows [18]: 1 eSi DV T2 eSi T Si ¼ ; ð1Þ C BOX DV g1 C ox
3.2.1. Front-channel mobility at the interface of SOI and high-k gate dielectric In high-k gate dielectric MOSFETs, the hysteresis of the drain current induced by charge trappings could lead to the misevaluation of electrical characteristics [20]. In our devices, a small hysteresis appears if the gate voltage is swept from a large negative value (e.g., from 1 V to 1 V), while it disappears if it is swept across a narrow gate voltage range (from 0.5 V to 1 V). However, the hysteresis is so small that we can neglect this effect for our main results. Fig. 4a and b show Id–Vg1 and the mobility of the front channel for the different devices (Table 1) on the same wafer. Table 1 shows the capacitance value Co per unit area at Vg1 = VT1 + 1.06 V, and the TSi determined using Eq. (1) and the converted value from Co, as described above. The threshold voltage of the front channel (VT1) and the back channel (VT2) is also shown in this table. Device D has a low threshold voltage. This type of sudden shift to a low threshold voltage and the subsequent recovery is observed frequently. However, these slow-trapped charges do not affect mobility, as indicated by the data for device D in Fig. 4b, although the loss of mobility in all samples is clearly observed. It should be noted that the mobility increases with electron density in the range of Ns = 1 2 · 1012 cm3, although in the poly-Si/SiO2 structures with non-doped SOI films, the mobility decreases with the increase in the electron density, as shown in several studies [7,9]. It is apparently shown in Fig. 4c that the front-channel mobility in the poly-Si/SiO2 structure decreases with the increase in the electron density. This is because the contribution of Coulomb scattering associated with the impurity of SOI film or interface states to the mobility reduction is small due to the screening effect in these conditions, and phonon
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Fig. 4. (a) Drain current versus gate voltage and (b) front-channel mobility versus electron density at Vg2 = 0 V in SOI–MOSFETs with TiN gates and HfO2 gate dielectrics. The average of the source (Is) and drain (Id) currents, (Is + Id)/2, was used as a correction for the front-channel current to compensate the gate leakage current. (c) Back-channel mobility in SOI–MOSFETs with TiN gates and HfO2 gate dielectrics at Vg1 = 0.1 V (L = W = 10 lm) and the mobility of the front (Vg2 = 0 V) and back channels (Vg1: · 1.1 V, c 1.2 V) in a 10.3-nm-thick, non-doped SOI n-MOSFET with a poly-Si gate and SiO2 (9 nm) gate insulator (L = 10 lm, W = 50 lm). The back-channel mobility for B, C, and E from the devices in Table 1 are indicated; this is because other devices were broken by the application of a large Vg2. In the device with a poly-Si gate and SiO2 gate insulator, the back-channel mobility is smaller than the front-channel mobility at the same electron density because the effective field in the back channel is larger than that in the front channel.
scattering is the main mobility limiting factor. This difference suggests that in our samples with TiN gates and HfO2 gate dielectrics, Coulomb scattering is enhanced and is the main limiting factor in this Ns region. Indeed, soft-phonon limited mobility, which is another possible mechanism for mobility reduction caused by integrating the HfO2 gate dielectric and TiN gate, is expected to decrease with the increase in Ns and is effective in the large Ns region [21]. Moreover, in the region where the mobility increases with Ns, the mobility value depends on the samples, and exhibits considerable variations. This fact strongly suggests that these variations are caused by the variations in the Coulomb scattering centers. In order to confirm this, we discuss the relationship between the variations in the mobility and other physical parameters. In our devices with SOI thicknesses ranging from 7 nm to 10 nm, the mobility is expected to decrease with TSi owing to the quantum-confinement effect associated with SOI thinning. However, the mobility does not exhibit a clear relation with TSi, as shown in Fig. 4b. Table 1 shows the SiO2 thickness (ESiO2 ) and HfO2 thickness (EHfO2 ) evaluated from Co, assuming that the variation in Co is caused by the variations in T SiO2 under constant T HfO2 and in T HfO2 under constant T SiO2 , respectively. The 1-nm variation in EHfO2 in Table 1 cannot cause mobility variation, as reported in the previous study [11]. A variation of a few angstroms in ESiO2 can affect the mobility since remote charges at the interface between HfO2 and interfacial SiO2 layers (IFL) significantly reduce the mobility [11] in addition to the Coulomb scattering centers at the interface between SOIs and IFL or in IFL. The experimental results do not exhibit a clear relation between the variations in mobility and ESiO2 , implying that it is not the main factor. In addition, the TiN thickness could vary. However, these variations are expected to affect the mobility reduction in a wide range of Ns [22], i.e., it differs from our results. Therefore, although further research using mass data is necessary, these results suggest the possibility that variations in Coulomb scattering centers induced by the integration of high-k gate dielectrics or metal gates cause these mobility variations. Fig. 5 shows VT1 and VT2 versus TSi. The variation in VT1 does not correspond to that in Tinv as shown in Table 1, and VT1 does not depend on TSi, while VT2 clearly increases as TSi decreases. In non-doped devices with thicknesses of 7–10 nm, both of them are expected to increase as TSi decreases owing to the quantum-confinement effect associated with SOI thinning, as previously reported [4,9]. This fact may also reflect the variation in trapped charges around the energy level near VT1, some of which can be the Coulomb scattering centers. 3.2.2. Back-channel mobility at the interface of SOI and buried SiO2 Fig. 4c shows the back-channel mobility for B, C, and E and the front- and back-channel mobility in the poly-Si/
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Table 1 Capacitance value (Co) per unit area at Vg1 = VT1 + 1.06 V, TSi determined by using Eq. (1) and the value of 1.23 · Co (see details in the text), threshold voltage of the front channel (VT1) at Vg2 = 0 V, threshold voltage of the back channel (VT2) at Vg1 = 0.1 V, and inversion thickness (Tinv) determined from Co Device
Co (F/m2)
TSi (nm)
VT1 (V)
VT2 (V)
Tinv (nm)
EHfO2 (nm)
ESiO2 (nm)
A B C D E F
0.0153 0.0155 0.0158 0.0159 0.0158 0.0173
7.0 7.2 7.3 7.5 8.0 9.2
0.369 0.375 0.348 0.245 0.353 0.358
20.4 20.3 19.9 15.8 19.1 14.3
2.3 2.2 2.2 2.2 2.2 2.0
2.8 2.6 2.4 2.3 2.4 1.4
1.4 1.3 1.3 1.3 1.3 1.2
Ns is approximately 1 · 1013 cm2 at V g1 = VT1 + 1.06 V. VT1 at Vg2 = 0 V is determined as the voltage that yields Ns = 3 · 1011 cm2 using the split-CV method. Since VT2 at Vg1 = 0.1 V cannot be determined directly, it was determined as the value of VT2 at Vg1 = 0.1 V for the function VT2(Vg1), which was obtained as the Vg2 value yielding Ns = 3 · 1011 cm2 (see [19] for the details) by using the front-gate split-CV method. EHfO2 and ESiO2 are the equivalent HfO2 thickness and SiO2 thickness, determined from Co values under the assumption of constant T SiO2 (1.4 nm) and T HfO2 (3 nm), respectively; T T HfO2 ð3 nmÞ ð1:4 nmÞ 1 1 and ESiO2 ¼ eSiO2 1:23C . When EHfO2 and ESiO2 are estimated using these equations, the value of EHfO2 ¼ eHfO2 ðj¼25Þ 1:23C SiOe2SiO eHfO o o ðj¼25Þ 2
2
primitive constant j for HfO2 does not affect significantly the variations in EHfO2 or ESiO2 , i.e., DEHfO2 6 1:5 nm and DESiO2 6 0:2 nm for 20 6 j 6 25.
Fig. 5. Threshold voltage of the front (VT1) and back (VT2) channels versus SOI thickness. VT1 and VT2 for D decrease temporarily because of the slowtrapped charges.
SiO2 structure with non-doped SOI. Note that the backchannel mobility also increases with the electron density in the range of Ns = 1–2 · 1012 cm3, although, in the poly-Si/SiO2 structure with non-doped SOI film, the mobility of the front and back channels decreases with the increase in the electron density. This suggests that the Coulomb scattering is enhanced even in the back channel. The electron density for evaluating mobility is often overestimated because of the effect of parasitic capacitance [23]. Although devices with wide and long channels were used in order to avoid this effect, it must be reexamined, because the parasitic capacitances between the Si substrate and source/drain cause overestimation of the capacitance value in back-channel measurement. Fig. 6 shows the capacitance measured by the split-CV method at a high
voltage Vg2. Although a constant value, such as 0.01 pF or 0.05 pF, was deducted from each capacitance value in order to eliminate the effect of parasitic capacitance, back-channel mobility still increases with electron density, as shown in Fig. 6. These results show that the back-channel mobility is apparently reduced, and the contribution of Coulomb scattering is rather large, even for back-channel mobility. Thus, this implies that the introduction of new materials to the gate and gate insulator influences backchannel mobility as well. This result is different from our previous result in [24], evaluated using an ultra-thin SOI–MOSFET with a TaSiN gate and HfO2 gate dielectric, i.e., back-channel mobility follows the universal mobility curve and decreases with the increase in the electron density in the range of
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ness. Although further research using mass data is necessary, these results suggest that they are due to variations in the Coulomb scattering centers induced by the integration of the new materials. Acknowledgments Special thanks are due to our colleagues S. Cristoloveanu, F. Balestra, and X. Mescot for total support. References
Fig. 6. Back-channel mobility versus electron density for device C measured by the front-gate split-CV method at Vg2 = 28, at which the back channel is inverted.
Ns = 1–2 · 1012 cm3. In that study, the TSi was 17.5 nm and the thickness of IFL under the high-k dielectric was 2.5 nm. This difference suggests the possibility that using a TiN, thin IFL, thin SOI film, or the combined effects of these factors might reduce the back-channel mobility. The strong dependence of the back-channel mobility on Ns suggests the contribution of the Coulomb scattering associated with charges in a high-k gate structure. In addition, since, in the samples of this study, the subband structure could be affected by TSi and the wave function of the electron could spread across the entire film, as explained in Section 2, a high-k gate dielectric could cause a reduction in back-channel mobility. These results suggest that the mobility may be affected not only by the nearest gate or gate insulator but also by the other gates or gate insulators in multi-gate structures with thin non-doped bodies. 4. Summary The impact of SOI thinning on transport is investigated for various SOI impurity concentrations. It is experimentally and theoretically verified that TSi that influences the quantum-confinement effect, clearly depends on the impurity concentration of SOI. However, once the quantumconfinement effect of the channel associated with SOI thinning occurs, the subband structure depends weakly on the SOI impurity concentration. Furthermore, the mobility in ultra-thin SOI–MOSFETs with HfO2 gate dielectrics and TiN gates was investigated. It was shown that the mobility of both the front and back channels is reduced, particularly, in the low electron density region. The results suggest that it is due to enhanced Coulomb scattering. Furthermore, the mobility exhibits considerable variations in this region. These variations do not correspond to the variations in SOI or gate-oxide thick-
[1] International Technology Roadmap for Semiconductors: SEMATECH
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