- Email: [email protected]
Electrical characterization of conductive and non-conductive barrier layers for Cu-metallization
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surface science ELSEVIER
Applied Surface Science 91 (1995) 285-290
Electrical characterization of conductive and non-conductive barrier layers for Cu-metallization C. Ahrens *, D. Depta, F. Schitthelm, S. Wilhelm Institutfiir Halbleitertechnologie, UniversitlitHannover, Appelstrasse 11A, D-30167Hannover, Germany
Received 20 March 1995; accepted for publication 11 May 1995
Abstract For application of copper in advanced multi-level metallization schemes it is indispensable to prevent Cu diffusion into the active area and into interlevel dielectrics by total encapsulation of Cu with barrier films. For that purpose the barrier properties of W / T i N / T i S i 2 contact systems were evaluated using electrical measurements. It is shown that barrier stability up to 600-700°C can be obtained by optimizing the sputtering conditions for TiN films (N 2 flow, temperature, collimator). Low frequency admittance measurements on Schottky diodes were shown to provide a very reliable and easy way to test the barrier stability. As a non-conductive barrier the Si3N4/SiO2(50 nm) system was investigated for different thicknesses of Si3N4 (0-200 nm). After annealing up to 550°C the samples did not show any degradation of the capacitance-voltage ( C - V ) and breakdown voltage characteristics. Bias thermal stress (BTS) test conditions (1-3 M V / c m , 220°C) reduce significantly the S i t 2 barrier lifetime, while 50 or 100 nm thin Si3N4 films improve the barrier mean time to failure by a factor of 25 or 100, respectively.
1. I n t r o d u c t i o n Copper has very high diffusion constants and solubilities in many materials. Additionally, Cu has high reactivity with Si, m a n y metals and atmospheric oxygen or water vapor. F o r application o f Cu as a metallization material, a complete and reliable encapsulation o f the copper is thus necessary to maintain the device characteristics over the thermal budget and the required lifetime. F o r total encapsulation Cu has to be coated by either conductive (between
* Corresponding author. Tel.: +49 511 762 4218; Fax: +49 511 762 4229; E-mail: [email protected].
C u / S i ) or non-conductive (between C u / S i O 2) barrier layers. TiSi 2, which is c o m m o n l y used as a contact material, employing the self-aligned silicide process ( S A L I C I D E ) shows interaction with Cu at temperatures below 300°C [1,2]. Therefore, a T i N / T i S i 2 bilayer structure is envisaged to obtain both, a low contact resistance and a stable diffusion barrier, respectively [3]. Investigations on TiN barriers layers have shown that film structure and barrier stability strongly depend on the fabrication method and parameters [4-6]. As non-conductive barriers we investigated S i t 2 and S i 3 N 4 / S i O 2 films for application as intermetal dielectric layer without additional con-
0169-4332/95/$09.50 © 1995 Elsevier Science B.V. All rights reserved SSDI 0169-4332(95)00132-8
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C. Ahrens et al. / Applied Surface Science 91 (1995) 285-290
ducting barrier. Previous results from other workers have shown that copper diffusion in SiO 2 can not be observed at relative high temperatures (450°C) without bias in vacuum ambient and that interstitial copper diffusion occurs if an electric field is used [7,8]. When measured under N 2 / H 2 atmosphere Cu was reported to penetrate much easier into the SiO 2 [7]. Testing of the barrier performance needs measurement techniques which are extremely sensitive to the presence of copper. Current-voltage ( I - V ) or capacitance-voltage ( C - V ) measurements on Schottky diodes and pn junctions seem promising in multiple respects; test conditions are close to future applications and electrical measurements show excellent sensitivity to very small amounts of impurities. In the case of Schottky diodes the presence of additional charge in the depletion region due to copper deep levels causes a contribution to the total capacitance under reverse bias [9] up to forward voltages where the cartier Fermi level at the metal interface coincides with the copper energy level [10]. As a result, bowing and shifting of the 1 / C 2 characteristics was often observed when deep levels a n d / o r interface states were present [10-16]. Leakage current measurements can be done on Schottky diodes in order to reveal variations of the barrier hight of the contact system, induced by the presence of copper. The frequently applied barrier test using I - V measurement on pn junctions is based on additional generation current components in the reverse domain when a deep copper level is present in the depletion region. Electrical testing of non-conductive barrier materials can be done by characterizing the parameters of MIS structures like flatband voltage Uw, interface state density Dit (both with C - V ) and the dielectric breakdown voltage after thermal a n d / o r bias thermal stress (BTS) [7,8].
2. Experimental 2.1. Conductive barriers The cross-sectional view of the general diode test structure (Fig. 1) shows the employed layer sequence and thicknesses. The Schottky contact and pn junc-
~
.
SiO2
(50 nm)
Cu
(300 .m}
W
00 nm}
TiN
(50 nm)
T[Si2
(50 rim)
W
(200 nm)
Fig. 1. Cross-sectional view of the applied diode test structure and layer thicknesses.
tion samples were prepared on wet oxidized (600 nm) p-Si (100) (5-10 f ~ . c m ) wafers. Prior to titanium sputter deposition (30 nm), contact holes were etched by RIE with CHF 3 and the wafers were prepared using H2SO 4 and a HF(I%) dip. The TiSi 2 contact (C54 phase) was formed using three different processes: (1) ion implantation through metal (ITM) of As + (120 keV, 5 × 1015 cm -2) and subsequent SALICIDE process with two RTA steps (650°C, 30 s and 900°C, 20 s, N 2 atmosphere) using intermediate selective etching to remove unreacted Ti; (2) SALICIDE process; (3) one step RTA (900°C, 30 s, N 2 atmosphere). After Ar if-plasma cleaning the TiN barrier films (50 nm) were reactively sputtered (2000 W dc, 0.47 Pa, 53 sccm Ar) employing different N z flows (9,14,19 sccm) and temperatures (40°C, 250°C): Both collimated (aspect ratio: 2) and noncollimated sputtering were used. Additionally, blanket TiN films, deposited in the same process runs were characterized by sheet resistance measurement and profilometer scans to determine their resistivity, surface roughness and film stress values. To improve adhesion of Cu to TiN, non-stressed W seed layers (10 nm) were dc sputtered onto most barrier systems without braking the vacuum. Some of the wafers with W / T i N barriers were submitted to a further RTA step (900°C, 30 s) under N2: Prior to Cu deposition by dc sputtering (300 nm, 1.99 /z~2 • cm) the barrier systems were patterned by RIE with SF6 and 02. Patterning of the metallization was done by wet etching. Finally a 50 nm PECVD SiO 2 passivation layer and 200 nm W for backside contact were deposited. The samples were submitted to different thermal treatment steps (300-700°C for 60-120 min) in N z / H 2 (9 : 1) flow (6 f/rain).
287
C. Ahrens et al. /Applied Surface Science 91 (1995) 285-290 C - V measurement was done on square-shaped 1 mm 2 diodes at 10 kHz using a HP4277 LCZ meter. l - V measurement was performed at a reverse bias of 5 V on 0.0625 m m 2 large Schottky diodes and pn junctions using a HP 4145 parameter analyzer.
ments under bias thermal stress conditions in N 2 ambient were done by in-situ I - V measurement using non-reversible increases of leakage current as the failure criteria.
4. Results and discussion 3. Noneonductive barriers 4.1. Conductive barriers
Simple MIS capacitors were fabricated using SiO 2 films or Si3N4/SiO 2 bilayers as an insulator and Cu or A1 pads as top electrodes, where aluminum was used as a reference. T C A - S i O 2 films (50 nm) were thermally grown on 4 inch p-Si and n-Si (100) wafers. Deposition of Si3N 4 was done in a L P C V D process with various thicknesses ( 0 - 2 0 0 nm). After dc sputter deposition of either Cu or A1, the front electrodes were patterned by wet etching. Backside contacts were realized using dc sputtering of W (200 nm) for Cu samples and A1 (200 nm) for A1 samples. Finally a 50 nm thick SiO 2 passivation layer was deposited in a P E C V D process. Thermal treatment was done at 100-600°C for 30 and 60 min under N 2 (Cu) or N 2 / N 2 (A1) atmosphere. Lifetime measure-
The measured film properties of blanket TiN films (50 nm) such as resistivity, surface roughness and stress values showed a strong dependence upon the sputtering conditions. The film stress is compressive for all films. Using a standard process with a medium N 2 flow (14 sccm) TiN films have an acceptable resistivity (167 ~ l ~ . cm) and very low film stress ( - 0.4 Gpa) and they show a smooth surface. Deviations from the medium N 2 flow increase both, the resistivity (about 270 /~f~. cm) and the film stress (up to - 4 . 6 Gpa). The use of a collimator between substrate and the target appreciably lowers the resistivity ( 8 5 / x f ~ . c m ) o f the film but increases the film stress ( - 4 . 7 GPa) and surface roughness.
Table 1 Summary of failure temperatures of the tested barrier systems; the layer thicknesses are: TiSi2 and TiN, 50 nm; W, 10 nm
failure temperature barrier system
4500C, 60min
600°C, 60min
700°C, 60min
failure determination
TiSiz
I-V, C-V, SEM, AES, SIMS
TIN(14 sccm N2)/TiSi2
C-V
W/TiN(9 sccm N2)/TiSi2
I-V, C-V, SEM
W/TiN(14 sccm N2)/TiSi2
I-V (beginning)
W/TiN(14 seem N2)/TiSi2 + RTA 900"C
I-V, SEM
W/TiN(19 sccm N2)/TiSi2
C-V
W/TiN(14 scem Nz, 250*C)/TiSi2
I-V, C-V, SEM
W/TiN(14 sccm N2, eollimated)/TiSi2
I-V, C-V, SEM
I
288
C. Ahrens et al. / Applied Surface Science 91 (1995) 285-290
1E-03
60t ~C, 60t tin !
1E-04
1E-05 1E-06 ~ E 1E'07 1/ -- 1E-08 1E-09 1E-10
1E-11 1E-12
/\
-0.5
]rP'~ 0.5
1.5
2.5
3.5
4.5
dc bias [V]
1E-03 1E-04 1E-05 I~
70( 'C, ~O = nln
voltages, indicating a decreased barrier height. This result corresponds very well with I - V measurements where the leakage current showed a slightly increased value after 700°C too (from 9.6 m A / c m 2 after 300°C to 15.2 m A / c m 2 after annealing at 700°C). However, the observed barrier shift can not definitely be attributed to the presence of copper. Schottky contacts with W / T i N barrier showed degradation of 1 / C 2 plots at 600°C although the diode leakage current did not increase significantly (from 9.0 m A / c m 2 after 300°C to 10.1 m A / c m 2 after annealing at 700°C). This admits the conclusion that C - V measurement provides more accurate information about barrier failure. Inconsistencies be-
1E-O6
1.2~16
IE=08 ~ -- - - - ~--';--1E-O9 r I ~'=" 1E-10 "~ 1E-11 "/ 1E-12 1~4@ " ~ -0.5 0.5 1.5 2.5 3.5 4.5
W / T •i N (19 s e e m )
/ /300eC
< $e+15
./ j~//450q2 '~ 450*(2
~
w
e~ 6e+15 <
o .
~
4=+IS
7000(
de bias [V]
Fig. 2. Current-voltage plots of n + p junctions (0.0625 mm2 area) with annealed (900°C) W/TiN barrier system and Cu metallization after thermal treatment at 600°C (top) and 700°C (bottom).
'-~ / 600"C' : As deI
le+16
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o
-0.2
0
0.2
0.4
0.6
0.8
1
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de bi= [Vl
An overview over the tested barrier systems and their failure temperatures is given in Table 1. The W / T i N barrier system with pn junctions showed decreasing reverse current densities up to 600°C annealing (16 n A / c m 2) and revealed first changes of I - V reverse characteristics at 700°C (Fig. 2). The increase of reverse current at 700°C was much more pronounced for the unannealed barrier system. Annealing of the W / T i N barrier in N z thus tends to have a positive influence on barrier stability. The admittance measurements on Schottky diodes offered significant changes of the 1 / C 2 graphs. Deviations from linear plots were observed at 600 and 700°C for most samples as represented exemplarily in Fig. 3 (above) for high N 2 flow (19 sccm). Exclusively the TiN barrier without tungsten showed an almost linear shape after 700°C (Fig. 3, below), although the graph slightly shifts to higher reverse
9¢+15
i
.
.
.
.
.
450°C.]
$e+15 TiN'I(14 sccm) • 7=+t5 i
F 6e+t55e+15
i
~ 4e+15
:
2¢+15
1 ~Ss0~Ctlb ..-'12~ 600°Cj
I Z ~ -~- 7oooc
.-•. . . . J " "
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~-,/
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Ie+15 0
•-0.2
0
.
0.2
.
.
0.4
.
0.6
.
0.8
I
1.2
de biu [V]
Fig. 3. 1 / C 2 versus voltage plots of Sehottky diodes with W/TiN(19 secm N2) barrier (top) and TIN(14 seem N2) harrier (bottom) after different thermal treatments. The measurement frequency is 10 kHz.
289
C. Ahrens et al. /Applied Surface Science 91 (1995) 285-290 mean time to failure [min]
'VO
1
2
3
4
measurement temperature : 220 *C
5
6
7
8
9
10
electric field [MV/cm]
Fig. 4. Mean time to failure of bias thermal stressed SiO2 and SiO2 / S i 3N4 barrier systems.
tween the failure temperatures of the W / T i N barrier with either Schottky contacts (600°C) or n + p junctions (700°C) can be assumed to be a result of the ion implantation process. TiN deposition with N 2 flows other than the standard process (14 sccm) resulted in barriers which failed at lower temperatures. In fact the best results can thus be achieved for the low resistivity, low stress TiN films. The hot deposited (250°C) and the collimated TiN films provide only insufficient barrier stability as can be shown by increased leakage currents (several hundred m A / c m 2) and deviations from the linear 1 / C 2 plots after thermal aging at 600 or 700°C. With regard to the fact that improved step coverage is important in sub-/z technologies, an optimization of the collimated deposition of TiN barrier films seems necessary.
5. Nonconductive barriers The results of the MIS parameter measurements of the SiO 2 and S i O 2 / S i 3 N 4 systems are represented in Table 2. After exclusive thermal stressing of the SiO 2 samples the C - V and I - V plots showed that no shifts of the flatband voltage (0.48 V) and no changes of the breakdown voltage (9 M V / c m ) occur Upon annealing at 550°C for 1 h. After bias thermal stressing at 220°C, 1 - 2 M V / c m for 1 - 3 h the flatband voltage was significantly increased to about 1.7 V and the breakdown voltage has decreased to about 7 M V / c m , indicating that copper has penetrated into the SiO 2 and reached the S i O z / S i interface. For thermally stressed S i O 2 / S i 3 N 4 samples the breakdown voltage did not change compared to the unstressed reference for annealing temperatures up to 600°C. The same results were also obtained after bias thermal stress at 220°C, 1 - 8 M V / c m for 1 h. However, interpretation is difficult here because the leakage current increased by two orders of magnitude after bias thermal stress. It can be estimated that the effective thickness of the barrier is decreased by beginning penetration of Cu into the Si3N 4. A graph representing the mean time to failure data upon bias and thermal stressing is given in Fig. 4. The mean time to failure depends exponentially on the electric field. The application of a Si3N 4 layer significantly increases the mean time to failure by a factor of 25 to 100 depending on the thickness (50 and 100 nm). The BTS tests show that for application of SiO 2 in Cu metallization the reduced lifetime has to be taken into account.
Table 2 MIS parameters of Cu/SiO2/Si and Cu/Si 2 N4/SIO2(50 nm)/Si systems after different thermal and bias thermal stress conditions Si3N4/SiO2 thickness
Thermaltreatment
BTS conditions
UFB(V)
Dit (1/eV/cm 2)
Eba (MV/cm)
50 nm SiO2 only
As deposited 450°C, 1 h 550°C, 1 h 450°C, 1 h 450°C, I h 450-600°C, 1 h 450-600°C, 1 h 450-600°C, 1 h -
220°C, 3 h 1 MV/cm 220°C, 1 h 2 MV/cm 220°C, 1 h 1-8 MV/cm 220°C, 1 h 5-7 MV/cm 220°C, 1 h 1-4 MV/cm
* 0.463 0.484 1.63 1.74 * * * * * *
8 × 10~ 4 X 101° 4 × 10l° 3 × l0 II 4 × 10I1 * * * * * *
8.5 9 9 7.5 7 8 8 > 7.5 > 7.5 >5 >5
50/50 nm 100/50 nm 200/50 nm
290
C. Ahrens et al. /Applied Surface Science 91 (1995) 285-290
6. Conclusion
I-V and C-V measurements on the conductive barrier system W / T i N / T i S i 2 showed that stability against copper diffusion is maintained at 600°C for 1 h in a N 2 / H 2 ambient and that beginning failure can be observed at 700°C. n+p Junctions with Cu metallization using the W / T i N / T i S i 2 barrier showed decreasing leakage current densities up to 600°C during 1 h and very high current densities after 700°C. Low frequency admittance measurement on Schottky diodes was proved to be very sensitive to the presence of copper in Si or at the metal/Si interface, showing bowing of t h e 1 / C 2 plots for most samples after 600°C. Exclusively the T i N / T i S i 2 barrier without W (14 sccm N z, 40°C) maintained its linear characteristic up to 700°C. Collimated sputtering of TiN has to be improved yet, as the barrier fails at 600°C already. It can be concluded that TiN barrier stability depends significantly on the fabrication procedure. A correlation between low TiN film stress and high barrier stability was observed. As a non-conductive barrier the investigated 50 nm TCA S i O 2 maintains its stability upon thermal treatment up to 550°C for 1 h (I-V, C-V) whereas for the Si3N4/SiO 2 samples no Cu diffusion was detectable for thermal treatment at 600°C for 1 h (l-V, C-V). Under BTS conditions the 50 nm SiO 2 barrier failed depending exponentially on the electric field (mean time to failure: 118 min for 220°C, 1 M V / c m ) . The use of Si3N 4 significantly improves the mean lifetime by a factor of 25-100 depending on its thickness. It is questionable whether S i O 2 alone will provide sufficient barrier stability.
Acknowledgements This work was financially supported by European Commission Project ESPRIT No. 9021 (COIN). The authors would like to thank their colleagues for good cooperation.
References [1] J.O. Olowolafe, J. Li and J.W. Mayer, J. Appl. Phys. 68 (1990) 6207. [2] E. Kolawa, J.S. Reid and J.-S. Chen, Submicron Metallization, 1805, SPIE Bellingham (1992) p. 11. [3] M. Delfino, E.K. Broadbent, A.E. Morgan, B.J. Burrow and M.H. Norcott, IEEE Electron Dev. Lett. EDL-6 (1985) 591. [4] G.A. Dixit, C.C. Wei and F.T. Liou, Appl. Phys. Lett. 62 (1993) 357: [5] S. Kanamori, Thin Solid Films 136 (1986) 215. [6] S.-Q. Wang, S. Suthar, C. Hoeflich and B.J. Burrow, J. Appl. Phys. 73 (1993) 2301. [7] J.D. McBrayer, R.M. Swanson and T.W. Sigmon, J. Electrochem. Soc. 133 (1986) 1243. [8] Y. Shacham-Diamand, A. Dedhia, D. Hoffstetter and W.G. Oldham, IEEE Proc. VMIC Conference (1991) p. 109. [9] S.M. Sze, Physics of Semiconductor Devices (Wiley, New York, 1981). [10] G.I. Roberts and C.R. Crowell, Solid-State Electron. 16 (1973) 29. [11] D. Bauza, J. Appl. Phys. 73 (1993) 1858. [12] S.J. Fonash, J. Appl. Phys. 54 (1983) 1966. [13] A. Goodman, J. Appl. Phys. 34 (1963) 329. [14] D. Bauza, Appl. Surf. Sci. 63 (1993) 291. [15] P.P. Sahay, M. Shamsuddin and R.S. Srivastava, J. Mater. Sci. Lett. 10 (1991) 556. [16] K. Steiner, IEEE Trans. Instr. Meas. 42 (1993) 39.
~ii~...~.:~:.$.:.-:. . . . . . . . . .
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surface science ELSEVIER
Applied Surface Science 91 (1995) 285-290
Electrical characterization of conductive and non-conductive barrier layers for Cu-metallization C. Ahrens *, D. Depta, F. Schitthelm, S. Wilhelm Institutfiir Halbleitertechnologie, UniversitlitHannover, Appelstrasse 11A, D-30167Hannover, Germany
Received 20 March 1995; accepted for publication 11 May 1995
Abstract For application of copper in advanced multi-level metallization schemes it is indispensable to prevent Cu diffusion into the active area and into interlevel dielectrics by total encapsulation of Cu with barrier films. For that purpose the barrier properties of W / T i N / T i S i 2 contact systems were evaluated using electrical measurements. It is shown that barrier stability up to 600-700°C can be obtained by optimizing the sputtering conditions for TiN films (N 2 flow, temperature, collimator). Low frequency admittance measurements on Schottky diodes were shown to provide a very reliable and easy way to test the barrier stability. As a non-conductive barrier the Si3N4/SiO2(50 nm) system was investigated for different thicknesses of Si3N4 (0-200 nm). After annealing up to 550°C the samples did not show any degradation of the capacitance-voltage ( C - V ) and breakdown voltage characteristics. Bias thermal stress (BTS) test conditions (1-3 M V / c m , 220°C) reduce significantly the S i t 2 barrier lifetime, while 50 or 100 nm thin Si3N4 films improve the barrier mean time to failure by a factor of 25 or 100, respectively.
1. I n t r o d u c t i o n Copper has very high diffusion constants and solubilities in many materials. Additionally, Cu has high reactivity with Si, m a n y metals and atmospheric oxygen or water vapor. F o r application o f Cu as a metallization material, a complete and reliable encapsulation o f the copper is thus necessary to maintain the device characteristics over the thermal budget and the required lifetime. F o r total encapsulation Cu has to be coated by either conductive (between
* Corresponding author. Tel.: +49 511 762 4218; Fax: +49 511 762 4229; E-mail: [email protected].
C u / S i ) or non-conductive (between C u / S i O 2) barrier layers. TiSi 2, which is c o m m o n l y used as a contact material, employing the self-aligned silicide process ( S A L I C I D E ) shows interaction with Cu at temperatures below 300°C [1,2]. Therefore, a T i N / T i S i 2 bilayer structure is envisaged to obtain both, a low contact resistance and a stable diffusion barrier, respectively [3]. Investigations on TiN barriers layers have shown that film structure and barrier stability strongly depend on the fabrication method and parameters [4-6]. As non-conductive barriers we investigated S i t 2 and S i 3 N 4 / S i O 2 films for application as intermetal dielectric layer without additional con-
0169-4332/95/$09.50 © 1995 Elsevier Science B.V. All rights reserved SSDI 0169-4332(95)00132-8
286
C. Ahrens et al. / Applied Surface Science 91 (1995) 285-290
ducting barrier. Previous results from other workers have shown that copper diffusion in SiO 2 can not be observed at relative high temperatures (450°C) without bias in vacuum ambient and that interstitial copper diffusion occurs if an electric field is used [7,8]. When measured under N 2 / H 2 atmosphere Cu was reported to penetrate much easier into the SiO 2 [7]. Testing of the barrier performance needs measurement techniques which are extremely sensitive to the presence of copper. Current-voltage ( I - V ) or capacitance-voltage ( C - V ) measurements on Schottky diodes and pn junctions seem promising in multiple respects; test conditions are close to future applications and electrical measurements show excellent sensitivity to very small amounts of impurities. In the case of Schottky diodes the presence of additional charge in the depletion region due to copper deep levels causes a contribution to the total capacitance under reverse bias [9] up to forward voltages where the cartier Fermi level at the metal interface coincides with the copper energy level [10]. As a result, bowing and shifting of the 1 / C 2 characteristics was often observed when deep levels a n d / o r interface states were present [10-16]. Leakage current measurements can be done on Schottky diodes in order to reveal variations of the barrier hight of the contact system, induced by the presence of copper. The frequently applied barrier test using I - V measurement on pn junctions is based on additional generation current components in the reverse domain when a deep copper level is present in the depletion region. Electrical testing of non-conductive barrier materials can be done by characterizing the parameters of MIS structures like flatband voltage Uw, interface state density Dit (both with C - V ) and the dielectric breakdown voltage after thermal a n d / o r bias thermal stress (BTS) [7,8].
2. Experimental 2.1. Conductive barriers The cross-sectional view of the general diode test structure (Fig. 1) shows the employed layer sequence and thicknesses. The Schottky contact and pn junc-
~
.
SiO2
(50 nm)
Cu
(300 .m}
W
00 nm}
TiN
(50 nm)
T[Si2
(50 rim)
W
(200 nm)
Fig. 1. Cross-sectional view of the applied diode test structure and layer thicknesses.
tion samples were prepared on wet oxidized (600 nm) p-Si (100) (5-10 f ~ . c m ) wafers. Prior to titanium sputter deposition (30 nm), contact holes were etched by RIE with CHF 3 and the wafers were prepared using H2SO 4 and a HF(I%) dip. The TiSi 2 contact (C54 phase) was formed using three different processes: (1) ion implantation through metal (ITM) of As + (120 keV, 5 × 1015 cm -2) and subsequent SALICIDE process with two RTA steps (650°C, 30 s and 900°C, 20 s, N 2 atmosphere) using intermediate selective etching to remove unreacted Ti; (2) SALICIDE process; (3) one step RTA (900°C, 30 s, N 2 atmosphere). After Ar if-plasma cleaning the TiN barrier films (50 nm) were reactively sputtered (2000 W dc, 0.47 Pa, 53 sccm Ar) employing different N z flows (9,14,19 sccm) and temperatures (40°C, 250°C): Both collimated (aspect ratio: 2) and noncollimated sputtering were used. Additionally, blanket TiN films, deposited in the same process runs were characterized by sheet resistance measurement and profilometer scans to determine their resistivity, surface roughness and film stress values. To improve adhesion of Cu to TiN, non-stressed W seed layers (10 nm) were dc sputtered onto most barrier systems without braking the vacuum. Some of the wafers with W / T i N barriers were submitted to a further RTA step (900°C, 30 s) under N2: Prior to Cu deposition by dc sputtering (300 nm, 1.99 /z~2 • cm) the barrier systems were patterned by RIE with SF6 and 02. Patterning of the metallization was done by wet etching. Finally a 50 nm PECVD SiO 2 passivation layer and 200 nm W for backside contact were deposited. The samples were submitted to different thermal treatment steps (300-700°C for 60-120 min) in N z / H 2 (9 : 1) flow (6 f/rain).
287
C. Ahrens et al. /Applied Surface Science 91 (1995) 285-290 C - V measurement was done on square-shaped 1 mm 2 diodes at 10 kHz using a HP4277 LCZ meter. l - V measurement was performed at a reverse bias of 5 V on 0.0625 m m 2 large Schottky diodes and pn junctions using a HP 4145 parameter analyzer.
ments under bias thermal stress conditions in N 2 ambient were done by in-situ I - V measurement using non-reversible increases of leakage current as the failure criteria.
4. Results and discussion 3. Noneonductive barriers 4.1. Conductive barriers
Simple MIS capacitors were fabricated using SiO 2 films or Si3N4/SiO 2 bilayers as an insulator and Cu or A1 pads as top electrodes, where aluminum was used as a reference. T C A - S i O 2 films (50 nm) were thermally grown on 4 inch p-Si and n-Si (100) wafers. Deposition of Si3N 4 was done in a L P C V D process with various thicknesses ( 0 - 2 0 0 nm). After dc sputter deposition of either Cu or A1, the front electrodes were patterned by wet etching. Backside contacts were realized using dc sputtering of W (200 nm) for Cu samples and A1 (200 nm) for A1 samples. Finally a 50 nm thick SiO 2 passivation layer was deposited in a P E C V D process. Thermal treatment was done at 100-600°C for 30 and 60 min under N 2 (Cu) or N 2 / N 2 (A1) atmosphere. Lifetime measure-
The measured film properties of blanket TiN films (50 nm) such as resistivity, surface roughness and stress values showed a strong dependence upon the sputtering conditions. The film stress is compressive for all films. Using a standard process with a medium N 2 flow (14 sccm) TiN films have an acceptable resistivity (167 ~ l ~ . cm) and very low film stress ( - 0.4 Gpa) and they show a smooth surface. Deviations from the medium N 2 flow increase both, the resistivity (about 270 /~f~. cm) and the film stress (up to - 4 . 6 Gpa). The use of a collimator between substrate and the target appreciably lowers the resistivity ( 8 5 / x f ~ . c m ) o f the film but increases the film stress ( - 4 . 7 GPa) and surface roughness.
Table 1 Summary of failure temperatures of the tested barrier systems; the layer thicknesses are: TiSi2 and TiN, 50 nm; W, 10 nm
failure temperature barrier system
4500C, 60min
600°C, 60min
700°C, 60min
failure determination
TiSiz
I-V, C-V, SEM, AES, SIMS
TIN(14 sccm N2)/TiSi2
C-V
W/TiN(9 sccm N2)/TiSi2
I-V, C-V, SEM
W/TiN(14 sccm N2)/TiSi2
I-V (beginning)
W/TiN(14 seem N2)/TiSi2 + RTA 900"C
I-V, SEM
W/TiN(19 sccm N2)/TiSi2
C-V
W/TiN(14 scem Nz, 250*C)/TiSi2
I-V, C-V, SEM
W/TiN(14 sccm N2, eollimated)/TiSi2
I-V, C-V, SEM
I
288
C. Ahrens et al. / Applied Surface Science 91 (1995) 285-290
1E-03
60t ~C, 60t tin !
1E-04
1E-05 1E-06 ~ E 1E'07 1/ -- 1E-08 1E-09 1E-10
1E-11 1E-12
/\
-0.5
]rP'~ 0.5
1.5
2.5
3.5
4.5
dc bias [V]
1E-03 1E-04 1E-05 I~
70( 'C, ~O = nln
voltages, indicating a decreased barrier height. This result corresponds very well with I - V measurements where the leakage current showed a slightly increased value after 700°C too (from 9.6 m A / c m 2 after 300°C to 15.2 m A / c m 2 after annealing at 700°C). However, the observed barrier shift can not definitely be attributed to the presence of copper. Schottky contacts with W / T i N barrier showed degradation of 1 / C 2 plots at 600°C although the diode leakage current did not increase significantly (from 9.0 m A / c m 2 after 300°C to 10.1 m A / c m 2 after annealing at 700°C). This admits the conclusion that C - V measurement provides more accurate information about barrier failure. Inconsistencies be-
1E-O6
1.2~16
IE=08 ~ -- - - - ~--';--1E-O9 r I ~'=" 1E-10 "~ 1E-11 "/ 1E-12 1~4@ " ~ -0.5 0.5 1.5 2.5 3.5 4.5
W / T •i N (19 s e e m )
/ /300eC
< $e+15
./ j~//450q2 '~ 450*(2
~
w
e~ 6e+15 <
o .
~
4=+IS
7000(
de bias [V]
Fig. 2. Current-voltage plots of n + p junctions (0.0625 mm2 area) with annealed (900°C) W/TiN barrier system and Cu metallization after thermal treatment at 600°C (top) and 700°C (bottom).
'-~ / 600"C' : As deI
le+16
/ / ..2:-
f.J
:_.
o
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
de bi= [Vl
An overview over the tested barrier systems and their failure temperatures is given in Table 1. The W / T i N barrier system with pn junctions showed decreasing reverse current densities up to 600°C annealing (16 n A / c m 2) and revealed first changes of I - V reverse characteristics at 700°C (Fig. 2). The increase of reverse current at 700°C was much more pronounced for the unannealed barrier system. Annealing of the W / T i N barrier in N z thus tends to have a positive influence on barrier stability. The admittance measurements on Schottky diodes offered significant changes of the 1 / C 2 graphs. Deviations from linear plots were observed at 600 and 700°C for most samples as represented exemplarily in Fig. 3 (above) for high N 2 flow (19 sccm). Exclusively the TiN barrier without tungsten showed an almost linear shape after 700°C (Fig. 3, below), although the graph slightly shifts to higher reverse
9¢+15
i
.
.
.
.
.
450°C.]
$e+15 TiN'I(14 sccm) • 7=+t5 i
F 6e+t55e+15
i
~ 4e+15
:
2¢+15
1 ~Ss0~Ctlb ..-'12~ 600°Cj
I Z ~ -~- 7oooc
.-•. . . . J " "
300°C'
~-,/
J/
Ie+15 0
•-0.2
0
.
0.2
.
.
0.4
.
0.6
.
0.8
I
1.2
de biu [V]
Fig. 3. 1 / C 2 versus voltage plots of Sehottky diodes with W/TiN(19 secm N2) barrier (top) and TIN(14 seem N2) harrier (bottom) after different thermal treatments. The measurement frequency is 10 kHz.
289
C. Ahrens et al. /Applied Surface Science 91 (1995) 285-290 mean time to failure [min]
'VO
1
2
3
4
measurement temperature : 220 *C
5
6
7
8
9
10
electric field [MV/cm]
Fig. 4. Mean time to failure of bias thermal stressed SiO2 and SiO2 / S i 3N4 barrier systems.
tween the failure temperatures of the W / T i N barrier with either Schottky contacts (600°C) or n + p junctions (700°C) can be assumed to be a result of the ion implantation process. TiN deposition with N 2 flows other than the standard process (14 sccm) resulted in barriers which failed at lower temperatures. In fact the best results can thus be achieved for the low resistivity, low stress TiN films. The hot deposited (250°C) and the collimated TiN films provide only insufficient barrier stability as can be shown by increased leakage currents (several hundred m A / c m 2) and deviations from the linear 1 / C 2 plots after thermal aging at 600 or 700°C. With regard to the fact that improved step coverage is important in sub-/z technologies, an optimization of the collimated deposition of TiN barrier films seems necessary.
5. Nonconductive barriers The results of the MIS parameter measurements of the SiO 2 and S i O 2 / S i 3 N 4 systems are represented in Table 2. After exclusive thermal stressing of the SiO 2 samples the C - V and I - V plots showed that no shifts of the flatband voltage (0.48 V) and no changes of the breakdown voltage (9 M V / c m ) occur Upon annealing at 550°C for 1 h. After bias thermal stressing at 220°C, 1 - 2 M V / c m for 1 - 3 h the flatband voltage was significantly increased to about 1.7 V and the breakdown voltage has decreased to about 7 M V / c m , indicating that copper has penetrated into the SiO 2 and reached the S i O z / S i interface. For thermally stressed S i O 2 / S i 3 N 4 samples the breakdown voltage did not change compared to the unstressed reference for annealing temperatures up to 600°C. The same results were also obtained after bias thermal stress at 220°C, 1 - 8 M V / c m for 1 h. However, interpretation is difficult here because the leakage current increased by two orders of magnitude after bias thermal stress. It can be estimated that the effective thickness of the barrier is decreased by beginning penetration of Cu into the Si3N 4. A graph representing the mean time to failure data upon bias and thermal stressing is given in Fig. 4. The mean time to failure depends exponentially on the electric field. The application of a Si3N 4 layer significantly increases the mean time to failure by a factor of 25 to 100 depending on the thickness (50 and 100 nm). The BTS tests show that for application of SiO 2 in Cu metallization the reduced lifetime has to be taken into account.
Table 2 MIS parameters of Cu/SiO2/Si and Cu/Si 2 N4/SIO2(50 nm)/Si systems after different thermal and bias thermal stress conditions Si3N4/SiO2 thickness
Thermaltreatment
BTS conditions
UFB(V)
Dit (1/eV/cm 2)
Eba (MV/cm)
50 nm SiO2 only
As deposited 450°C, 1 h 550°C, 1 h 450°C, 1 h 450°C, I h 450-600°C, 1 h 450-600°C, 1 h 450-600°C, 1 h -
220°C, 3 h 1 MV/cm 220°C, 1 h 2 MV/cm 220°C, 1 h 1-8 MV/cm 220°C, 1 h 5-7 MV/cm 220°C, 1 h 1-4 MV/cm
* 0.463 0.484 1.63 1.74 * * * * * *
8 × 10~ 4 X 101° 4 × 10l° 3 × l0 II 4 × 10I1 * * * * * *
8.5 9 9 7.5 7 8 8 > 7.5 > 7.5 >5 >5
50/50 nm 100/50 nm 200/50 nm
290
C. Ahrens et al. /Applied Surface Science 91 (1995) 285-290
6. Conclusion
I-V and C-V measurements on the conductive barrier system W / T i N / T i S i 2 showed that stability against copper diffusion is maintained at 600°C for 1 h in a N 2 / H 2 ambient and that beginning failure can be observed at 700°C. n+p Junctions with Cu metallization using the W / T i N / T i S i 2 barrier showed decreasing leakage current densities up to 600°C during 1 h and very high current densities after 700°C. Low frequency admittance measurement on Schottky diodes was proved to be very sensitive to the presence of copper in Si or at the metal/Si interface, showing bowing of t h e 1 / C 2 plots for most samples after 600°C. Exclusively the T i N / T i S i 2 barrier without W (14 sccm N z, 40°C) maintained its linear characteristic up to 700°C. Collimated sputtering of TiN has to be improved yet, as the barrier fails at 600°C already. It can be concluded that TiN barrier stability depends significantly on the fabrication procedure. A correlation between low TiN film stress and high barrier stability was observed. As a non-conductive barrier the investigated 50 nm TCA S i O 2 maintains its stability upon thermal treatment up to 550°C for 1 h (I-V, C-V) whereas for the Si3N4/SiO 2 samples no Cu diffusion was detectable for thermal treatment at 600°C for 1 h (l-V, C-V). Under BTS conditions the 50 nm SiO 2 barrier failed depending exponentially on the electric field (mean time to failure: 118 min for 220°C, 1 M V / c m ) . The use of Si3N 4 significantly improves the mean lifetime by a factor of 25-100 depending on its thickness. It is questionable whether S i O 2 alone will provide sufficient barrier stability.
Acknowledgements This work was financially supported by European Commission Project ESPRIT No. 9021 (COIN). The authors would like to thank their colleagues for good cooperation.
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