- Email: [email protected]
Electrical characterization of integrated circuit metal line thickness
~
Pergamon
Solid-State Electronics Vol. 38, No. 12, pp. 1993-2000, 1995 Copyright © 1995 Elsevier Science Ltd 0038-1101(95)00080-1 Printed in Great Britain. All fights reserved 0038-1101/95 $9.50+ 0.00
ELECTRICAL CHARACTERIZATION OF INTEGRATED CIRCUIT METAL LINE THICKNESS SANTOS MAYO and HARRY A. S C H A F F ' ( National Institute of Standards and Technology, Bid 225, Room B360, Gaithersburg, MD 20899, U.S.A.
(Received 14 February 1995) Abstract--Resistance measurements of thin aluminum-silicon alloy lines, 10 and 30 #m wide, were made at various temperatures in the 9.2295.5 K range. Deviations from Matthiessen's rule were observed over the whole temperature range. At temperatures near room ambient data for these lines are in good agreement with those reported for aluminum-copper alloy wires. A formalism was developed to calculate line thickness and cross-sectional area from electrical resistance data. Line thickness calculations are in good agreement with thickness data measured via scanning electron microscopy. The stress distributions in these lines were modeled by using finite element stress analysis. The results show large stress gradients localized at the line edge region, whereas at the central part of the line there is a high stress value and a low stress gradient. In submicrometer lines the whole line body is under large stress gradients.
1. INTRODUCTION
Although an electrical method to measure average width, w, of straight, thin-film metal lines used for integrated circuit (IC) interconnects is available[l], at present there is no electrical technique available to measure the line thickness, t. Dimensional characterization of IC interconnect lines is generally done via scanning electron microscopy (SEM) which involves a destructive, expensive technique requiring cross-sectional line preparation, and yields information limited to the specific cross section observed. Because of nonuniformity in line width, multiple SEM observations of different cross sections along the line are needed in order to average the crosssectional area data. By measuring the electrical resistivity of cylindrical wires with known dimensions, Matthiessen[2] stated empirically that the electrical resistivity of dilute binary alloys at any given temperature has only two components: a temperature-dependent term, pi(T), due to the ideally pure solvent metal, and a temperature-independent term, the residual resistivity, p (c, 0), due to metallic impurities with concentration c, plus other alloy structural defects. The residual resistivity is measured at absolute zero, where pi(0) is assumed to be negligible. Thus Matthiessen's rule (MR) is written as:
p(c, T) = p(c, 0) + pi(T).
(1)
If the resistivity of aluminum-based alloy wires were exactly described by eqn (1), the cross-sectional area could be determined from resistance data measured within the linearity range. If thermal variation in wire dimensions is negligible within the selected temperature interval, the change in resistance is given SSE 38/12--B
by the length to area ratio times dp(c, T)/dT. From eqn (1) the latter factor is given by dp~/dT, thus the cross-sectional area can be calculated from easily accessible parameters. Since experimental evidence with aluminum-based alloys has shown temperature-dependent deviations from MR[3], it is necessary to correct eqn (1) by introducing a resistivity term, A(c, T), called the deviation from Matthiessen's rule (DMR). Equation (1) is now written
p(c, T) = p(c, O) + pi(T) + A(c, T),
(la)
where the terms p(c, 0) and A(c, T) are dependent on the alloy composition, structural defects, dimensions, and sample fabrication procedure. However, there are significant differences between the electrical properties of free wires and metallization lines fabricated with the same material. Particularly, for IC interconnects we analyze, with eqn (la), the magnitude of thermal effects on the line cross-sectional area, and develop a formalism suitable for line thickness characterization. By definition, A(c, T) is zero at absolute zero, and consequently, there is a need to measure the line resistance at temperatures near the absolute zero in order to characterize p(c, 0). For the purpose of this work we are concerned with determining A(c, T) at various temperatures in order to evaluate the specific differences between eqns (1) and (la) at temperatures around room ambient. These differences determine the error in line thickness introduced by using eqn (l) rather than eqn (la). Due to instrumental limitations in our apparatus, and because of the very small variation in the electrical resistance of metals in the vicinity of absolute
1993
Santos Mayo and Harry A. Schafft
1994
zero, excluding superconductive transitions, we approximate the term p(c, 0) by p(c, 9.2), calculated from resistance data measured at the minimum temperature experimentally available with our instrumentation, 9.2K. The p~(T) value is taken from aluminum resistivity tables[4]. In order to evaluate p(c, 9.2) we developed a formalism to calculate the line cross-sectional area as a function of temperature. Although the DMR is more prominent at low temperatures, where thermal and residual components of resistance are about equal[5,6], at temperatures around room ambient and higher such deviations are small but still measurable. This has been experimentally confirmed over a wide temperature range with thin aluminum-copper alloy wires[7] and thin pure aluminum films[8].
alter the accuracy of the measurement. Contacts located at each end of the line serve to apply current, and two side contacts located along the line define the actual length and serve to measure the voltage drop along the line. The wires connecting the metal line terminals to the measuring apparatus were thermally anchored to the cold finger. A 5 mA d.c. current was passed through the line with a high-stability, constant-current supply. Resistance data were collected with a maximum current density of approx. 105 A/cm 2. The maximum power dissipated was less than 100#W. No evidence of joule heating was observed due to the power dissipated in the structure. After reaching thermal equilibrium, the voltage drop along the line was measured with 10 nV resolution, by using both current polarities, and averaged over a 400-power-line-cycle time interval.
2. EXPERIMENTAL 3. THEORY
Thin metallization lines were fabricated at the NIST Semiconductor Processing Laboratory by d.c. sputter deposition of an AI-I at.% Si alloy on (100) silicon wafers, having a 780nm thick thermally grown wet oxide film. Metallization lines were patterned by photolithography. A 500nm nominal thickness film was deposited with a planar d.c. magnetron sputtering source operated at approx. 6A, 540 V arc, in argon at 0.3 Pa. Total deposition time was 25min. The initial pressure in the sputtering chamber before admitting argon was 1.3 x 10 4 Pa. Metallization lines, 10 and 30 #m wide, and 640 and 805/~m long, respectively, were patterned, and later annealed at 420°C for 30 min in forming gas. Source total impurities reported by the supplier were about 5 ppm metals, 6 ppm carbon, and 8 ppm oxygen. Secondary ion mass spectrometry (SIMS) analysis based on sensitivity factors[9], showed about 70 ppm Cu, and less than 10 ppm total content of B, Cr, Co, Ti, Ca, V and Mg. In addition, there is over 1 at.% oxygen and 0.6 at.% nitrogen contamination from the sputtering chamber residual atmosphere, plus argon (not measured by SIMS) resulting from gas occluded during sputter deposition. The high copper content in the sputtered film is assumed to be due to contamination from a copper anode used for the d.c. sputtering arc. Argon in the metal would increase film resistivity[10]. A chip containing metallization lines TC30 and TCiOS with nominal width 30 and 10#m, respectively, was diced out of a fabricated wafer and mounted with silver-filled epoxy resin on a goldcoated ceramic carrier provided with contacts. The line terminals were bonded to the chip carrier contacts with aluminum wire 25 #m in diameter. The chip carrier was mounted in thermal contact with the cold finger of a helium refrigerator capable of reaching temperatures down to l0 K with 0.1 K resolution. Each line was fabricated with four contact pads to make Kelvin resistance measurements. Thus, the resistances of wires bonded to the contacts do not
Based on line resistance vs temperature data we have developed a formalism to calculate line crosssectional area and thickness as a function of temperature. Although c and T are explicit variables in eqns (1) and (la) that determine the residual resistivity, there is an additional implicit parameter, the stress a, that influences resistivity[l 1]. However, a is temperature and geometry dependent, and we have not done an independent measurement to characterize its effect on resistivity. Therefore in our formalism we use the independent variables only. From the line resistance, R(T)=L(T)p(c, T)/A(T), we obtain:
L(T) dp(c, T) A(T) dT
dR(T)
dT [
l
+ L(T)
dL(T)
i
aT
A(T)
dd~)]R(T),
(2)
and by differentiating eqn (la), we extract the derivative of p(c, T) vs temperature, dp(c, T)/dT= dpi(T)/dT + dA(c, T)/dT, which we use in eqn (2), to obtain: dp~(T) dA(c, T) A(T)
dT dR(T)
dT L(T) 1 dA(T) + A(T) aT [
1
L(T)
d d ( ~ ) JR(T))"
(3) In order to evaluate the coefficient of R(T) in the square brackets of eqn (3) it should be recognized that, due to the metallization-to-substrate pinning in IC interconnect lines, length variations are fully controlled by the substrate thermal expansion, whereas cross-sectional area variations are partially controlled by the substrate thermal expansion, through width variations, and partially controlled by the metal thermal expansion through thickness variations. In addition to these thermal effects, there are elastic effects in the metal, inducing cross-sectional
Characterization of IC line thickness area variations as a function of line length variations. The line cross-sectional area is expressed as A = t(T, L) x w(T, L), where t(T, L) and w(T, L) are, respectively, the thickness and width, which in turn are functions of temperature T and line length L. By taking the total derivative of the area we write:
The aluminum and silicon thermal coefficients are defined, respectively, as:
expansion
L(T) A(T) = dR(T)
1995
G,(T) - 2 x 10-4p(c, 9.2) dT
(
7
>
Now we solve eqn (3e) at T = 273.2 K by eliminating the unknown p(c, 9.2) in the numerator. To do this we express the line cross-sectional area at T = 9.2 K in terms of the area at 273.2 K via eqn (3f), which allows calculation of A(273.2). The area variation for a temperature change T, - T,, where T, > T, is calculated by integrating both sides of eqn (3~):
dT. In(z) =ff ctA,(T)dT+0.475 ~r~%U’)
at(T) IQ(T) =p -. t(T) dT ’
1
w
1 aw(T) a,,(T)=--=--. w(T) aT
1 L(T)
From the elastic properties write:
at aL=-vL;
t
aL(T) dT
(3b)
of the metal, we can
aw z=-v
dA(T) -
dT
= Q,(T)
For aluminum and silicon the integrals in eqn (3f) over any temperature interval in the O-300 K range are tabulated[ 121. From the definition of sheet resistance, R,(T) = p(c, T)/t(T), we write the line thickness, t:
,w E’
t(T) =
where the Poisson ratio of aluminum, v = 0.35, controls the line thickness expansion, and due to the metal-to-substrate pinning, we use v’= 0.5~ as a modified Poisson ratio controlling the line width expansion. Thus eqn (3a) is now written: 1 ~ A(T)
+ (1 - 1.5v)as,(T).
(3~)
and
from
X
dR(T)
7
TCp(T)
Rs(T)[TCR,(T)
the
-
Q(T)I’
(4)
definition
- TCR(T)
= Q,(T)
- 1.5vcrsi(T),
(4a) (4b)
where: TCp(T)
1 dpG”) -. PG’-) dT ’
= ~
TCR(T)=---TCR,(T)
UT) [~.AI(T)
+
TCp(T) - TCR,(T) = G,(T),
are, +
, WC, T) ’ dT
of line resistance, sheet resistance, plus eqn (3c), we derive the following relations:
@i(T) + ---=WC, T) A(T) dT
G,(T) dT
R(T) = p(c, T)L(T)/A(T),
Equation (3~) states that for a given temperature change, the relative variation in cross-sectional area is smaller for anchored lines than for free wires. By using eqn (3~) we can now write eqn (3) as:
dT
(3e)
1.5V~si(T)IR(T)
+ [EN(T)) -
respectively,
1 R(T)
1
dR(T)
dT WV-)
= R,(T) dT
the
’
temperature
’ coefficient
of
1.5vS(T)lR(T) . (3d) resistivity, the temperature coefficient of resistance,
From the definition of p(c, 0), it is known that A(c, T) is zero at absolute zero, and from thin AlLCu wire resistivity data[7], it has been shown that A(c, T) is a continuous function of temperature increasing from zero up to a maximum value, at temperatures below room ambient, and then slowly decreasing at higher temperatures. At temperatures in the 250350 K range, A(c, T) values are insensitive to the Cu concentration in the alloy for the 0.0254.6at.O~ range. In addition, these data show that at 273.2 K, the A(c, T)/p(c, 0) ratio equals 0.067, and the slope of this ratio vs temperature is -2 x 10e4 (see Fig. 1 in Ref. 7). In order to calculate the line cross-sectional area as a function of temperature, we use this slope value in eqn (3e) resulting in:
and the temperature coefficient of sheet resistance. Now we can write eqn (4) as:
r(T) =
dpi(T) dT R,(T)[TCR(T)
, WC, T) ’ dT + Q,(T)
- 1.5va,,(T)]’
(4c)
Equations (4) and (4c) are of general application with aluminum-based lines, provided both terms in the numerator are known. From previous work the first term is known[4]. At temperatures around room ambient, the second term, dA(c, T)/dT, is known from previous work[7], as well as the present work, to be two orders of magnitude smaller than dp,(T)/dT. By neglecting the second term in the numerator, the metallization thickness and the resistivity can be determined to within approx. 2%. Thus for a quick thickness and resistivity characterization,
Santos Mayo and Harry A. Schafft
1996
TEMPERATURE (K)
Fig. 1. Line resistance vs temperature measured with a four-terminal Kelvin probe. A 5 mA constant current is passed through lines TClOS (0) and TC30 (A).
resistance and sheet resistance measurements are needed at two different temperatures around room ambient. Resistivity data are very useful to monitor metallization impurities. 4. RESULTS
Resistance data, R(c, T), are plotted in Fig. 1. There is a linear resistance versus temperature dependence in the 150-300 K region with a deviation from linearity of about 60ppm. At temperatures below 100 K there is a nonlinear transition region extending down to about 50 K. At even lower temperatures, there is another regime with a very slow variation with temperature which extends down to the limit of our experimental range, 9.2 K. We summarize our data in Table 1. Rows # 1 and # 2 show the line resistance data at 273.2 and 9.2 K, respectively. Row #3 shows AR(T)/AT calculated by a linear fit of the resistance vs temperature data in the 150-300 K temperature range. The corresponding correlation coefficient for each line is shown in row #4. The temperature dependence of resistance of similar lines from a different chip of the same wafer used here is known to be linear up to temperatures of about 500 K[13]. Row # 5 shows the tempera-
Table
I
ture coefficient of resistance at 273.2 K for each line. Their difference is 0.1%. From fit variations of the resistance vs temperature data, the standard deviation of the temperature coefficient of resistance at T = 273.2 K is estimated to be 0.2%. Consequently we assume that at temperatures around room ambient both lines have equal temperature coefficient of resistance. This indicates that the metallization has identical chemical composition and structural defects in both lines. Row #6 shows the nominal line length from photomask specifications. Row #7 shows the slope of the resistivity vs temperature data for p,(T) in the 150-300 K range, calculated from aluminum resistivity data [4]. Row # 8 shows the cross-sectional area at T = 273.2 K calculated with eqn (3f), as explained above. Row #9 shows the resistivity at 7’ = 9.2 K. The corresponding cross-sectional area is derived from the area at T = 273.2 K by using eqn (3d). These lines show a significant residual resistivity difference, 2.3%, that we understand in terms of stress differences[l I]. Since the temperature coefficient of resistance at T = 273.2 K is about the same we assume equal chemical composition and structural defect distribution in both lines. By assuming equal metallization thickness for both lines, from the data shown in row #8 we obtain the ratio of the electrically measured line widths at room temperature, W, : [R’,(TC3O)/W,(TClOS)],,,,
Parameter
1 2 3 4 5 6 7 8 9 10 11
R(273.22) (a) ~9.2) (n) AR/AT (150 2 T 5 300) (n/K) Corr. Coeff. TCR(273.2) (l/K) L,_,(295.5) (pm) Ap,/AT (150 2 T I 300) (pQcm/K) A (273.2) (pm*) P (G 9.2) Wcm) P (c, 273.2) (ram) A(c, 273.2) (&cm)
(5)
which is larger than the expected geometrical line width ratio, 3. Because of difficulty in achieving perfect control of the wet chemistry photolithographic processing used to pattern these lines, the actual line width is generally narrower by a small amount t than photomask specifications. We calculate t from the condition:
and used this width ratio to calculate the electrical line widths for TC30 and TCIOS, which are 28.8
Metallization line data
Row
= 3.28,
TC30
TClOS
1.569057 4.098403 0.280741 0.749862 5.9187 x 10-j 1.54404 x 10-r 0.999942 3.772138 x 10-j 3.767419 x IO-’ 805 640 1.147 x 10-Z 15.3682 4.6825 0.5340 0.5467 2.9955 2.9985 30.1 32.6
Characterization of IC line thickness 0.20
i
o TC10S A TC30
0.15
1 dA(c,T) = .2x104 p(e,9.2) dT
.~- O.lO AA A
A ~_~_~
,2oo o ° o ° ° A
A
= o o
O°
O O~
0.05
a~ 0 50
I 1 I 100 150 200 TEMPERATURE (K)
I 250
300
Fig. 2. D M R vs temperature calculated with parameters
shown in Table 1. Line TCIOS (I-1). Line TC30 (A). and 8.8/~m, respectively. With these values we calculate, from data shown in row #8, the room temperature line thickness, 0.534/~m. A calibrated [14] SEM was used to characterize the cross-section of identical lines fabricated on a different chip, thus allowing an independent measurement of the line geometrical thickness. The SEM thickness data were averaged over a number of observations on different cross-sections along the line, resulting in 0.542 ___0.0075 # m (SD 1.4%). This result is within one standard deviation of the electrical thickness data, 0.534 #m. It needs to be emphasized that the SEM thickness characterization technique used involves elaborate and expensive preparations that make difficult its use. However, the observed agreement is significant. The sheet resistance at 273.2K for TC30 is 56.1n~cm/I--1, and for TCIOS is 56.3 mtacm/I-']. Row # 10 shows the line resistivity calculated at 273.2 K, and row # 11 shows the DMR. Figure 2 shows the A(c, T)/p (c, 9.2) vs temperature data, corresponding to each line. At low temperatures there is a continuous increase from zero, up to a wide maximum extending from 200 to 250 K, followed by a slow decay towards room temperature. The slope of this decay is close to - 2 x 10-4. In the high-temperature regime the difference between these two sets of data is about 2%, similar to the difference in p (c, 9.2) values. The lower set of data, represented by squares, corresponds to the narrower line, TCIOS, which has a higher residual resistivity than the wider line. The shape of these curves is sensitive to p(c, 9.2) variations of less than 1%. The stress-induced residual resistivity component has its maximum value at absolute zero, and it decreases as the temperature increases. At temperatures near the annealing point, this component must be negligible. Thus in metallization lines, because of the metal-to-substrate pinning, stress-induced effects are more likely to effect the residual resistivity than in free wires. At temperatures near the absolute zero the shape of our A(c, T)/p(c, 9.2) data is different from the
1997
wire data[7], whereas at temperatures around room ambient both wire and line data are in close agreement. This behavior can be understood in terms of a stress-induced component on the residual resistivity which is a maximum at absolute zero and decreases as the temperature increases. For the purpose of this work, and based on these data agreement at high temperatures, we can evaluate the second term of the numerator in eqns (4) and (4c), i.e. dA(c, 273.2)/dT = - 2 x 10-4p(c, 9.2). As an application of eqn (4c), we show in Table 2, a comparison of both the thickness calculation based on electrical data with the SEM-measured line thickness data, corresponding to three AI-I at.% Si alloy samples patterned with the same mask. Sample A was fabricated at an outside facility, whereas samples B and C were fabricated at our NIST facility. Rows # 1 and # 2 show, respectively, the temperature coefficient of resistance and the sheet resistance at T = 273.2. Row # 3 shows the line thickness calculated with eqn (4c) and row # 4 shows the corresponding SEM measurements. Sample B has considerable debris covering the substrate around the metal. This obstructed a clear SEM observation of the line base, thus resulting in a reduced SEM thickness value. Row # 5 shows the ratio of line thickness calculated with eqn (4c) to the thickness measured by SEM, tt~)/tsEM. The agreement between both sets of data is within the SEM data accuracy. In order to calculate thickness of unknown aluminum-based metallization lines at temperatures around room ambient, from eqn (4a) or eqn (4b) the residual resistivity can be calculated by using present results, i.e. dA(c, 2 7 3 . 2 ) / d T = - 2 × 10-4p(c, 9.2), and A(c, 273.2) = 0.07p(c, 9.2). The metallization thickness can now be extracted from eqns (4) or (4c). 5. STRESS ANALYSIS
Figure 3 shows the resistance ratio of line TC 10S to line TC30 at various temperatures in the 9.2-295.5 K range. At the low temperature end, this ratio is about 2% larger than the room-temperature ratio, where electron-phonon scattering dominates. Between these high- and low-temperature extremes, there is an inflection point in the 50-75 K region where this curve turns from convex at low temperatures, to concave at high temperatures. Although these lines are simultaneously fabricated with the same process and are located about 2 mm apart from each other, they show differences of about 2% in their p(c, 9.2) values, as reported in Table 1 row #9. However, at T = 273.2 K both lines show, within experimental error, the same temperature coefficient of resistance and resistivity, which is indicative of the same residual resistivity at this temperature. We discuss this below, in term of differences in line stress rather than in chemical composition of the metal.
Santos Mayo and Harry A. Schafft
1998
Row 1 2 3 4 5
Parameter
Table 2. Electricaland SEM linethicknessdata Sample A Sample B
TCR(273.2) (K -l) Rs(273.2) (mf~/sq) t (273.2)~) (nm) t (293)SEM (nm) t(4c)/tsEM
4.037 x 10-3 36.98 757 767 0.9869
Although fluctuations in the sputter deposition process may lead to slight differences in line characteristics[15,16], we assume the higher resistance ratio measured at the low temperature region is primarily due to stress differences between the two lines, causing resistivity differences. We have calculated the stress field distribution in these metallization lines by using the ANSYS Finite Element Method, a commercially available solver for three-dimensional modeling*. The structure analyzed is composed of a 0.5 mm thick silicon substrate with 0.78 pm thick oxide overlayer plus 0.5/~m thick aluminum metallization line deposited on the oxide. The line has a rectangular shape, with its width along the x-direction, its thickness along the y-direction, and its length along the z-direction. Stress calculations were done by discretizing the aluminum layer into five, and the oxide layer into six equal-thickness sublayers along the y-direction. Figures 4-6 show calculated stress at 300 K for three different levels in the metal, along the x-, y- and z-directions, as a function of the x distance from the line edge. The annealing temperature is assumed to be 400 K. The maximum stress along each direction is localized at the metal-substrate interface, as expected from line anchoring to the substrate. Near the line edges there is a localized compression region which is clearly seen at the top metallization layer. Stresses are minimal along the y-direction because the metal is free to expand in a direction perpendicular to the
2,700
g
2.675
Sample C
3.559 × 10 -3 56.50 562 544 1.033
3.772 x 10 3 56.10 534 541 0.9871
substrate. The values of tensile or compressive stresses at each metal sublayer are determined by the difference between the annealing temperature, at which the metal-substrate structure is assumed to be in a stress-free condition, and the temperature for which the calculation is performed. Stress distributions were also calculated at 20 K for lines annealed at 700 K, showing similar results, with stresses along the x- and z-directions reaching values above the room-temperature aluminum yield point. Based on these results we conclude that at about 3/~m inside the line edges, the stress field reaches saturation along the x-, y- or z-directions. For lines wider than about 10/~m, the stress gradient near the central region is minimal, whereas the stress gradient near the edges is very large. For example, the results obtained at 20 K show that the x-component of the tensile stress gradient near the line edge is about 2 GPa//~m. For a 30/~m wide line, the central 24/~m wide region is under constant tensile stress. Similar results are obtained for the z-component of the stress. In lines less than 10/~m in width, thermally induced stress distributions have large gradients in the central region, and the effects of stress gradients are extended through the complete body. The maximum tensile stress calculated at 20 K is in excess of 550 MPa, which is above the room-temperature aluminum yield strength. However, these lines were thermally cycled a number of times in the 300-10 K temperature range yielding reproducible resistance data, which indicates that the low temperature yield strength is higher than the maximum calculated tensile stress, and the line preserves its structure with no plastic flow. High tensile stresses are related to metal voiding which is a serious interconnect reliability concern[17]. Based on our stress analysis we suggest Fig. 3 is understood in terms of enhanced resistivity in the narrower line, due to high stress gradient at the edge region.
g 2.650
6. C O N C L U S I O N S
Resistance measurements of two IC aluminumbased metallization lines, 10 and 30 pm in width and
2.625
2.600 0
[ 50
I 100
I 150
I 200
I 250
300
T E M P E R A T U R E (K)
Fig. 3. Resistance ratio R(TCIOS)/R(TC30) for the above two lines vs temperature. The error bar on each data point is +0.1%.
*Certain commercial equipment, instruments, or materials are identifiedin order to specify the experimental procedure. Such identification does not imply recommendation or endorsement by NIST, nor does it imply that the materials or equipment identifiedare necessarilythe best available for the purpose described.
Characterization of IC line thickness 0.020
I
I
I
Interface----~_ ~
I
0.020
I
I
1999 i
I
0.015
I
I 2.0
I 2.5
0.018
-.-...>//'"~.~
/'" Middle
E E O.010
~ 0.016
a
"~-Top
%
Y
'-Top
0.005 o9 uJ rr Io9
I
~
~
0
0.014
CL
N 0.012
-0.005 -0.010
) 015
0
I I I 1.0 1.5 2.0 X-DISTANCE (p.m)
I 2.5
3.0
Fig. 4. x-direction stresscomponent,calculatedat 300K, for the three sublayers, as indicated. The annealing temperature is assumed to be 400 K. The coordinate origin is located at the line edge. The inset shows half line cross section with the y-direction along the line thickness and the z-direction along the line length, which is perpendicular to the figure plane. 0.01 x 10 9 Dyne/mm2 = 100 MPa. 0.5/~m thick, were m a d e over the 9.2-295.5 K temperature range. Analysis of these d a t a shows D M R s consistent with those reported for thin aluminum--copper alloy wires with various copper contents (0.025 a t . % - 0 . 6 a t . ° ) . Q u a n t i t a t i v e agreement was observed at temperatures a b o v e approx. 250 K. F r o m this resistivity d a t a correspondence it can be estim a t e d that, at temperatures a r o u n d r o o m ambient, D M R s are within 2 % , for b o t h a l u m i n u m - b a s e d wires or IC interconnects. Based o n electrical resistance data, a formalism was developed to calculate the line cross-sectional area a n d thickness variation with temperature. M e t a l film thickness data, calculated from electrical resistance m e a s u r e d at two different temperatures, agree within the i n s t r u m e n t a l accuracy, with thickness d a t a m e a s u r e d by a calibrated SEM. A n increase o f the low-temperature resistance ratio of these two lines by approx. 2 % , over the r o o m - t e m -
m
0.020
i
i
i
I
0.0101 0
',
Acknowledgements--We are indebted to Dr Hai Tang for calculating line stress distributions. We thank J. M. Thomas for preparing samples for line cross-sectional observation and, S. N. Jones for the SEM operation. This work was partially supported by the National Semiconductor Metrology Program at the National Institute of Standards and Technology.
REFERENCES
1. A S T M F 1261-89, Standard test method for determin-
3. 4.
~Middle
6. >L -0 005
~'Top
-0.010
I 0.5
7. I I I 1.0 1.5 2.0 X-DISTANCE (Itm)
I 2.5
3.0
Fig. 5. y-direction stress component as a function of the x-direction. Stress along the y-direction is very small due to the metal freedom in a direction perpendicular to the substrate.
3.0
perature ratio value, was assumed to be due to differences in stress distributions in these lines. A finite-element stress analysis shows a large stress gradient located at the line edges, which gradually diminishes while extending approx. 3 p m t o w a r d the line center. Thus a larger fraction of the metal in the n a r r o w e r line would be u n d e r the effect o f this stress gradient, which appears to cause a n increase in the resistance ratio.
5. o.oo5 I--
I 1,5
Fig. 6. z-direction stress component as a function of the x-direction. The edge effects are concentrated on a negligible small region in comparison to the line length.
2.
OOlO
I 1.0
X-DISTANCE(pm)
I
m o.o15[
I 0.5
8. 9.
ing the average width and cross-sectional area of a straight thin film metal line. 1989 Annual Book of A S T M Standards, American Society for Testing and Materials, Philadelphia, Pa (1989). A. Matthiessen and C. Vogt, Ann. Phys., Leipzig 122, 19 (1864). J. Bass, Adv. Phys. 21, 431 (1972). P. D. Desai, H. M. James and C. Y. Ho, J. Phys. Chem. Ref. Data 13, 1131 (1984). D. K. C. MacDonald, Electrical conductivity of metals and alloys at low temperatures. In Encyclopedia of Physics (Edited by S. Flugge), Vol. 15, pp. 137-197. Springer, Berlin (1956). J. S. Dugdale and Z. S. Basinski, Phys. Rev. 157, 552 (1967). C. Papastaikoudis, K. Papathanasopoulos, E. Rocofylou and W. Tselfes, Phys. Rev. B 14, 3394 (1976). A. yon Bassewitz and E. N. Mitchell, Phys. Rev. 182, 712 (1969). R. G. Wilson, F. A. Stevie and P. M. Kahora, in Secondary Ion Mass Spectrometry SIMS VIII (Edited by A. Benninghoven, K. T. F. Janssen, J. Trumpner and H. W. Werner), pp. 487-490. Wiley, New York (1992).
2000
Santos Mayo and Harry A. Schafft
10. G. W. Wilson and B. P. Shina, Thin Solid Films 8, 207 (1971). 11. N. Wiser, Contemp. Phys. 25, 211 (1984). 12. R. J. Corrucini and J. Gniewek, Thermal Expansion of Technical Solids at Low Temperatures. National Bureau of Standards, Monograph 29 (1961). 13. H. A. Schafft and J. S. Suehle, SolM-St. Electron. 35, 403 (1992). 14. To calibrate the SEM magnification, a NIST-developed standard reference material, SRM 484c, was used. See NIST Special Publication 260, p. 90 (1990-1991), U.S.
Department of Commerce, National Institute of Standards and Technology. A discussion on calibration uncertainty of this standard can be found in J. Fu, M. C. Croarkin and T. Vorburger, J. Res. NIST 99, 191 (1994). 15. J. A. Thornton, Ann. Rev. Mater. Sci. 7, 239 (1977). 16. J. A. Thornton, J. Vac. Sci. Technol. 11, 666 (1974). 17. M. A. Korhonen, C. A. Paszkiet and C-Y. Li, J. appl. Phys. 69, 8083 (1991).
Pergamon
Solid-State Electronics Vol. 38, No. 12, pp. 1993-2000, 1995 Copyright © 1995 Elsevier Science Ltd 0038-1101(95)00080-1 Printed in Great Britain. All fights reserved 0038-1101/95 $9.50+ 0.00
ELECTRICAL CHARACTERIZATION OF INTEGRATED CIRCUIT METAL LINE THICKNESS SANTOS MAYO and HARRY A. S C H A F F ' ( National Institute of Standards and Technology, Bid 225, Room B360, Gaithersburg, MD 20899, U.S.A.
(Received 14 February 1995) Abstract--Resistance measurements of thin aluminum-silicon alloy lines, 10 and 30 #m wide, were made at various temperatures in the 9.2295.5 K range. Deviations from Matthiessen's rule were observed over the whole temperature range. At temperatures near room ambient data for these lines are in good agreement with those reported for aluminum-copper alloy wires. A formalism was developed to calculate line thickness and cross-sectional area from electrical resistance data. Line thickness calculations are in good agreement with thickness data measured via scanning electron microscopy. The stress distributions in these lines were modeled by using finite element stress analysis. The results show large stress gradients localized at the line edge region, whereas at the central part of the line there is a high stress value and a low stress gradient. In submicrometer lines the whole line body is under large stress gradients.
1. INTRODUCTION
Although an electrical method to measure average width, w, of straight, thin-film metal lines used for integrated circuit (IC) interconnects is available[l], at present there is no electrical technique available to measure the line thickness, t. Dimensional characterization of IC interconnect lines is generally done via scanning electron microscopy (SEM) which involves a destructive, expensive technique requiring cross-sectional line preparation, and yields information limited to the specific cross section observed. Because of nonuniformity in line width, multiple SEM observations of different cross sections along the line are needed in order to average the crosssectional area data. By measuring the electrical resistivity of cylindrical wires with known dimensions, Matthiessen[2] stated empirically that the electrical resistivity of dilute binary alloys at any given temperature has only two components: a temperature-dependent term, pi(T), due to the ideally pure solvent metal, and a temperature-independent term, the residual resistivity, p (c, 0), due to metallic impurities with concentration c, plus other alloy structural defects. The residual resistivity is measured at absolute zero, where pi(0) is assumed to be negligible. Thus Matthiessen's rule (MR) is written as:
p(c, T) = p(c, 0) + pi(T).
(1)
If the resistivity of aluminum-based alloy wires were exactly described by eqn (1), the cross-sectional area could be determined from resistance data measured within the linearity range. If thermal variation in wire dimensions is negligible within the selected temperature interval, the change in resistance is given SSE 38/12--B
by the length to area ratio times dp(c, T)/dT. From eqn (1) the latter factor is given by dp~/dT, thus the cross-sectional area can be calculated from easily accessible parameters. Since experimental evidence with aluminum-based alloys has shown temperature-dependent deviations from MR[3], it is necessary to correct eqn (1) by introducing a resistivity term, A(c, T), called the deviation from Matthiessen's rule (DMR). Equation (1) is now written
p(c, T) = p(c, O) + pi(T) + A(c, T),
(la)
where the terms p(c, 0) and A(c, T) are dependent on the alloy composition, structural defects, dimensions, and sample fabrication procedure. However, there are significant differences between the electrical properties of free wires and metallization lines fabricated with the same material. Particularly, for IC interconnects we analyze, with eqn (la), the magnitude of thermal effects on the line cross-sectional area, and develop a formalism suitable for line thickness characterization. By definition, A(c, T) is zero at absolute zero, and consequently, there is a need to measure the line resistance at temperatures near the absolute zero in order to characterize p(c, 0). For the purpose of this work we are concerned with determining A(c, T) at various temperatures in order to evaluate the specific differences between eqns (1) and (la) at temperatures around room ambient. These differences determine the error in line thickness introduced by using eqn (l) rather than eqn (la). Due to instrumental limitations in our apparatus, and because of the very small variation in the electrical resistance of metals in the vicinity of absolute
1993
Santos Mayo and Harry A. Schafft
1994
zero, excluding superconductive transitions, we approximate the term p(c, 0) by p(c, 9.2), calculated from resistance data measured at the minimum temperature experimentally available with our instrumentation, 9.2K. The p~(T) value is taken from aluminum resistivity tables[4]. In order to evaluate p(c, 9.2) we developed a formalism to calculate the line cross-sectional area as a function of temperature. Although the DMR is more prominent at low temperatures, where thermal and residual components of resistance are about equal[5,6], at temperatures around room ambient and higher such deviations are small but still measurable. This has been experimentally confirmed over a wide temperature range with thin aluminum-copper alloy wires[7] and thin pure aluminum films[8].
alter the accuracy of the measurement. Contacts located at each end of the line serve to apply current, and two side contacts located along the line define the actual length and serve to measure the voltage drop along the line. The wires connecting the metal line terminals to the measuring apparatus were thermally anchored to the cold finger. A 5 mA d.c. current was passed through the line with a high-stability, constant-current supply. Resistance data were collected with a maximum current density of approx. 105 A/cm 2. The maximum power dissipated was less than 100#W. No evidence of joule heating was observed due to the power dissipated in the structure. After reaching thermal equilibrium, the voltage drop along the line was measured with 10 nV resolution, by using both current polarities, and averaged over a 400-power-line-cycle time interval.
2. EXPERIMENTAL 3. THEORY
Thin metallization lines were fabricated at the NIST Semiconductor Processing Laboratory by d.c. sputter deposition of an AI-I at.% Si alloy on (100) silicon wafers, having a 780nm thick thermally grown wet oxide film. Metallization lines were patterned by photolithography. A 500nm nominal thickness film was deposited with a planar d.c. magnetron sputtering source operated at approx. 6A, 540 V arc, in argon at 0.3 Pa. Total deposition time was 25min. The initial pressure in the sputtering chamber before admitting argon was 1.3 x 10 4 Pa. Metallization lines, 10 and 30 #m wide, and 640 and 805/~m long, respectively, were patterned, and later annealed at 420°C for 30 min in forming gas. Source total impurities reported by the supplier were about 5 ppm metals, 6 ppm carbon, and 8 ppm oxygen. Secondary ion mass spectrometry (SIMS) analysis based on sensitivity factors[9], showed about 70 ppm Cu, and less than 10 ppm total content of B, Cr, Co, Ti, Ca, V and Mg. In addition, there is over 1 at.% oxygen and 0.6 at.% nitrogen contamination from the sputtering chamber residual atmosphere, plus argon (not measured by SIMS) resulting from gas occluded during sputter deposition. The high copper content in the sputtered film is assumed to be due to contamination from a copper anode used for the d.c. sputtering arc. Argon in the metal would increase film resistivity[10]. A chip containing metallization lines TC30 and TCiOS with nominal width 30 and 10#m, respectively, was diced out of a fabricated wafer and mounted with silver-filled epoxy resin on a goldcoated ceramic carrier provided with contacts. The line terminals were bonded to the chip carrier contacts with aluminum wire 25 #m in diameter. The chip carrier was mounted in thermal contact with the cold finger of a helium refrigerator capable of reaching temperatures down to l0 K with 0.1 K resolution. Each line was fabricated with four contact pads to make Kelvin resistance measurements. Thus, the resistances of wires bonded to the contacts do not
Based on line resistance vs temperature data we have developed a formalism to calculate line crosssectional area and thickness as a function of temperature. Although c and T are explicit variables in eqns (1) and (la) that determine the residual resistivity, there is an additional implicit parameter, the stress a, that influences resistivity[l 1]. However, a is temperature and geometry dependent, and we have not done an independent measurement to characterize its effect on resistivity. Therefore in our formalism we use the independent variables only. From the line resistance, R(T)=L(T)p(c, T)/A(T), we obtain:
L(T) dp(c, T) A(T) dT
dR(T)
dT [
l
+ L(T)
dL(T)
i
aT
A(T)
dd~)]R(T),
(2)
and by differentiating eqn (la), we extract the derivative of p(c, T) vs temperature, dp(c, T)/dT= dpi(T)/dT + dA(c, T)/dT, which we use in eqn (2), to obtain: dp~(T) dA(c, T) A(T)
dT dR(T)
dT L(T) 1 dA(T) + A(T) aT [
1
L(T)
d d ( ~ ) JR(T))"
(3) In order to evaluate the coefficient of R(T) in the square brackets of eqn (3) it should be recognized that, due to the metallization-to-substrate pinning in IC interconnect lines, length variations are fully controlled by the substrate thermal expansion, whereas cross-sectional area variations are partially controlled by the substrate thermal expansion, through width variations, and partially controlled by the metal thermal expansion through thickness variations. In addition to these thermal effects, there are elastic effects in the metal, inducing cross-sectional
Characterization of IC line thickness area variations as a function of line length variations. The line cross-sectional area is expressed as A = t(T, L) x w(T, L), where t(T, L) and w(T, L) are, respectively, the thickness and width, which in turn are functions of temperature T and line length L. By taking the total derivative of the area we write:
The aluminum and silicon thermal coefficients are defined, respectively, as:
expansion
L(T) A(T) = dR(T)
1995
G,(T) - 2 x 10-4p(c, 9.2) dT
(
7
>
Now we solve eqn (3e) at T = 273.2 K by eliminating the unknown p(c, 9.2) in the numerator. To do this we express the line cross-sectional area at T = 9.2 K in terms of the area at 273.2 K via eqn (3f), which allows calculation of A(273.2). The area variation for a temperature change T, - T,, where T, > T, is calculated by integrating both sides of eqn (3~):
dT. In(z) =ff ctA,(T)dT+0.475 ~r~%U’)
at(T) IQ(T) =p -. t(T) dT ’
1
w
1 aw(T) a,,(T)=--=--. w(T) aT
1 L(T)
From the elastic properties write:
at aL=-vL;
t
aL(T) dT
(3b)
of the metal, we can
aw z=-v
dA(T) -
dT
= Q,(T)
For aluminum and silicon the integrals in eqn (3f) over any temperature interval in the O-300 K range are tabulated[ 121. From the definition of sheet resistance, R,(T) = p(c, T)/t(T), we write the line thickness, t:
,w E’
t(T) =
where the Poisson ratio of aluminum, v = 0.35, controls the line thickness expansion, and due to the metal-to-substrate pinning, we use v’= 0.5~ as a modified Poisson ratio controlling the line width expansion. Thus eqn (3a) is now written: 1 ~ A(T)
+ (1 - 1.5v)as,(T).
(3~)
and
from
X
dR(T)
7
TCp(T)
Rs(T)[TCR,(T)
the
-
Q(T)I’
(4)
definition
- TCR(T)
= Q,(T)
- 1.5vcrsi(T),
(4a) (4b)
where: TCp(T)
1 dpG”) -. PG’-) dT ’
= ~
TCR(T)=---TCR,(T)
UT) [~.AI(T)
+
TCp(T) - TCR,(T) = G,(T),
are, +
, WC, T) ’ dT
of line resistance, sheet resistance, plus eqn (3c), we derive the following relations:
@i(T) + ---=WC, T) A(T) dT
G,(T) dT
R(T) = p(c, T)L(T)/A(T),
Equation (3~) states that for a given temperature change, the relative variation in cross-sectional area is smaller for anchored lines than for free wires. By using eqn (3~) we can now write eqn (3) as:
dT
(3e)
1.5V~si(T)IR(T)
+ [EN(T)) -
respectively,
1 R(T)
1
dR(T)
dT WV-)
= R,(T) dT
the
’
temperature
’ coefficient
of
1.5vS(T)lR(T) . (3d) resistivity, the temperature coefficient of resistance,
From the definition of p(c, 0), it is known that A(c, T) is zero at absolute zero, and from thin AlLCu wire resistivity data[7], it has been shown that A(c, T) is a continuous function of temperature increasing from zero up to a maximum value, at temperatures below room ambient, and then slowly decreasing at higher temperatures. At temperatures in the 250350 K range, A(c, T) values are insensitive to the Cu concentration in the alloy for the 0.0254.6at.O~ range. In addition, these data show that at 273.2 K, the A(c, T)/p(c, 0) ratio equals 0.067, and the slope of this ratio vs temperature is -2 x 10e4 (see Fig. 1 in Ref. 7). In order to calculate the line cross-sectional area as a function of temperature, we use this slope value in eqn (3e) resulting in:
and the temperature coefficient of sheet resistance. Now we can write eqn (4) as:
r(T) =
dpi(T) dT R,(T)[TCR(T)
, WC, T) ’ dT + Q,(T)
- 1.5va,,(T)]’
(4c)
Equations (4) and (4c) are of general application with aluminum-based lines, provided both terms in the numerator are known. From previous work the first term is known[4]. At temperatures around room ambient, the second term, dA(c, T)/dT, is known from previous work[7], as well as the present work, to be two orders of magnitude smaller than dp,(T)/dT. By neglecting the second term in the numerator, the metallization thickness and the resistivity can be determined to within approx. 2%. Thus for a quick thickness and resistivity characterization,
Santos Mayo and Harry A. Schafft
1996
TEMPERATURE (K)
Fig. 1. Line resistance vs temperature measured with a four-terminal Kelvin probe. A 5 mA constant current is passed through lines TClOS (0) and TC30 (A).
resistance and sheet resistance measurements are needed at two different temperatures around room ambient. Resistivity data are very useful to monitor metallization impurities. 4. RESULTS
Resistance data, R(c, T), are plotted in Fig. 1. There is a linear resistance versus temperature dependence in the 150-300 K region with a deviation from linearity of about 60ppm. At temperatures below 100 K there is a nonlinear transition region extending down to about 50 K. At even lower temperatures, there is another regime with a very slow variation with temperature which extends down to the limit of our experimental range, 9.2 K. We summarize our data in Table 1. Rows # 1 and # 2 show the line resistance data at 273.2 and 9.2 K, respectively. Row #3 shows AR(T)/AT calculated by a linear fit of the resistance vs temperature data in the 150-300 K temperature range. The corresponding correlation coefficient for each line is shown in row #4. The temperature dependence of resistance of similar lines from a different chip of the same wafer used here is known to be linear up to temperatures of about 500 K[13]. Row # 5 shows the tempera-
Table
I
ture coefficient of resistance at 273.2 K for each line. Their difference is 0.1%. From fit variations of the resistance vs temperature data, the standard deviation of the temperature coefficient of resistance at T = 273.2 K is estimated to be 0.2%. Consequently we assume that at temperatures around room ambient both lines have equal temperature coefficient of resistance. This indicates that the metallization has identical chemical composition and structural defects in both lines. Row #6 shows the nominal line length from photomask specifications. Row #7 shows the slope of the resistivity vs temperature data for p,(T) in the 150-300 K range, calculated from aluminum resistivity data [4]. Row # 8 shows the cross-sectional area at T = 273.2 K calculated with eqn (3f), as explained above. Row #9 shows the resistivity at 7’ = 9.2 K. The corresponding cross-sectional area is derived from the area at T = 273.2 K by using eqn (3d). These lines show a significant residual resistivity difference, 2.3%, that we understand in terms of stress differences[l I]. Since the temperature coefficient of resistance at T = 273.2 K is about the same we assume equal chemical composition and structural defect distribution in both lines. By assuming equal metallization thickness for both lines, from the data shown in row #8 we obtain the ratio of the electrically measured line widths at room temperature, W, : [R’,(TC3O)/W,(TClOS)],,,,
Parameter
1 2 3 4 5 6 7 8 9 10 11
R(273.22) (a) ~9.2) (n) AR/AT (150 2 T 5 300) (n/K) Corr. Coeff. TCR(273.2) (l/K) L,_,(295.5) (pm) Ap,/AT (150 2 T I 300) (pQcm/K) A (273.2) (pm*) P (G 9.2) Wcm) P (c, 273.2) (ram) A(c, 273.2) (&cm)
(5)
which is larger than the expected geometrical line width ratio, 3. Because of difficulty in achieving perfect control of the wet chemistry photolithographic processing used to pattern these lines, the actual line width is generally narrower by a small amount t than photomask specifications. We calculate t from the condition:
and used this width ratio to calculate the electrical line widths for TC30 and TCIOS, which are 28.8
Metallization line data
Row
= 3.28,
TC30
TClOS
1.569057 4.098403 0.280741 0.749862 5.9187 x 10-j 1.54404 x 10-r 0.999942 3.772138 x 10-j 3.767419 x IO-’ 805 640 1.147 x 10-Z 15.3682 4.6825 0.5340 0.5467 2.9955 2.9985 30.1 32.6
Characterization of IC line thickness 0.20
i
o TC10S A TC30
0.15
1 dA(c,T) = .2x104 p(e,9.2) dT
.~- O.lO AA A
A ~_~_~
,2oo o ° o ° ° A
A
= o o
O°
O O~
0.05
a~ 0 50
I 1 I 100 150 200 TEMPERATURE (K)
I 250
300
Fig. 2. D M R vs temperature calculated with parameters
shown in Table 1. Line TCIOS (I-1). Line TC30 (A). and 8.8/~m, respectively. With these values we calculate, from data shown in row #8, the room temperature line thickness, 0.534/~m. A calibrated [14] SEM was used to characterize the cross-section of identical lines fabricated on a different chip, thus allowing an independent measurement of the line geometrical thickness. The SEM thickness data were averaged over a number of observations on different cross-sections along the line, resulting in 0.542 ___0.0075 # m (SD 1.4%). This result is within one standard deviation of the electrical thickness data, 0.534 #m. It needs to be emphasized that the SEM thickness characterization technique used involves elaborate and expensive preparations that make difficult its use. However, the observed agreement is significant. The sheet resistance at 273.2K for TC30 is 56.1n~cm/I--1, and for TCIOS is 56.3 mtacm/I-']. Row # 10 shows the line resistivity calculated at 273.2 K, and row # 11 shows the DMR. Figure 2 shows the A(c, T)/p (c, 9.2) vs temperature data, corresponding to each line. At low temperatures there is a continuous increase from zero, up to a wide maximum extending from 200 to 250 K, followed by a slow decay towards room temperature. The slope of this decay is close to - 2 x 10-4. In the high-temperature regime the difference between these two sets of data is about 2%, similar to the difference in p (c, 9.2) values. The lower set of data, represented by squares, corresponds to the narrower line, TCIOS, which has a higher residual resistivity than the wider line. The shape of these curves is sensitive to p(c, 9.2) variations of less than 1%. The stress-induced residual resistivity component has its maximum value at absolute zero, and it decreases as the temperature increases. At temperatures near the annealing point, this component must be negligible. Thus in metallization lines, because of the metal-to-substrate pinning, stress-induced effects are more likely to effect the residual resistivity than in free wires. At temperatures near the absolute zero the shape of our A(c, T)/p(c, 9.2) data is different from the
1997
wire data[7], whereas at temperatures around room ambient both wire and line data are in close agreement. This behavior can be understood in terms of a stress-induced component on the residual resistivity which is a maximum at absolute zero and decreases as the temperature increases. For the purpose of this work, and based on these data agreement at high temperatures, we can evaluate the second term of the numerator in eqns (4) and (4c), i.e. dA(c, 273.2)/dT = - 2 x 10-4p(c, 9.2). As an application of eqn (4c), we show in Table 2, a comparison of both the thickness calculation based on electrical data with the SEM-measured line thickness data, corresponding to three AI-I at.% Si alloy samples patterned with the same mask. Sample A was fabricated at an outside facility, whereas samples B and C were fabricated at our NIST facility. Rows # 1 and # 2 show, respectively, the temperature coefficient of resistance and the sheet resistance at T = 273.2. Row # 3 shows the line thickness calculated with eqn (4c) and row # 4 shows the corresponding SEM measurements. Sample B has considerable debris covering the substrate around the metal. This obstructed a clear SEM observation of the line base, thus resulting in a reduced SEM thickness value. Row # 5 shows the ratio of line thickness calculated with eqn (4c) to the thickness measured by SEM, tt~)/tsEM. The agreement between both sets of data is within the SEM data accuracy. In order to calculate thickness of unknown aluminum-based metallization lines at temperatures around room ambient, from eqn (4a) or eqn (4b) the residual resistivity can be calculated by using present results, i.e. dA(c, 2 7 3 . 2 ) / d T = - 2 × 10-4p(c, 9.2), and A(c, 273.2) = 0.07p(c, 9.2). The metallization thickness can now be extracted from eqns (4) or (4c). 5. STRESS ANALYSIS
Figure 3 shows the resistance ratio of line TC 10S to line TC30 at various temperatures in the 9.2-295.5 K range. At the low temperature end, this ratio is about 2% larger than the room-temperature ratio, where electron-phonon scattering dominates. Between these high- and low-temperature extremes, there is an inflection point in the 50-75 K region where this curve turns from convex at low temperatures, to concave at high temperatures. Although these lines are simultaneously fabricated with the same process and are located about 2 mm apart from each other, they show differences of about 2% in their p(c, 9.2) values, as reported in Table 1 row #9. However, at T = 273.2 K both lines show, within experimental error, the same temperature coefficient of resistance and resistivity, which is indicative of the same residual resistivity at this temperature. We discuss this below, in term of differences in line stress rather than in chemical composition of the metal.
Santos Mayo and Harry A. Schafft
1998
Row 1 2 3 4 5
Parameter
Table 2. Electricaland SEM linethicknessdata Sample A Sample B
TCR(273.2) (K -l) Rs(273.2) (mf~/sq) t (273.2)~) (nm) t (293)SEM (nm) t(4c)/tsEM
4.037 x 10-3 36.98 757 767 0.9869
Although fluctuations in the sputter deposition process may lead to slight differences in line characteristics[15,16], we assume the higher resistance ratio measured at the low temperature region is primarily due to stress differences between the two lines, causing resistivity differences. We have calculated the stress field distribution in these metallization lines by using the ANSYS Finite Element Method, a commercially available solver for three-dimensional modeling*. The structure analyzed is composed of a 0.5 mm thick silicon substrate with 0.78 pm thick oxide overlayer plus 0.5/~m thick aluminum metallization line deposited on the oxide. The line has a rectangular shape, with its width along the x-direction, its thickness along the y-direction, and its length along the z-direction. Stress calculations were done by discretizing the aluminum layer into five, and the oxide layer into six equal-thickness sublayers along the y-direction. Figures 4-6 show calculated stress at 300 K for three different levels in the metal, along the x-, y- and z-directions, as a function of the x distance from the line edge. The annealing temperature is assumed to be 400 K. The maximum stress along each direction is localized at the metal-substrate interface, as expected from line anchoring to the substrate. Near the line edges there is a localized compression region which is clearly seen at the top metallization layer. Stresses are minimal along the y-direction because the metal is free to expand in a direction perpendicular to the
2,700
g
2.675
Sample C
3.559 × 10 -3 56.50 562 544 1.033
3.772 x 10 3 56.10 534 541 0.9871
substrate. The values of tensile or compressive stresses at each metal sublayer are determined by the difference between the annealing temperature, at which the metal-substrate structure is assumed to be in a stress-free condition, and the temperature for which the calculation is performed. Stress distributions were also calculated at 20 K for lines annealed at 700 K, showing similar results, with stresses along the x- and z-directions reaching values above the room-temperature aluminum yield point. Based on these results we conclude that at about 3/~m inside the line edges, the stress field reaches saturation along the x-, y- or z-directions. For lines wider than about 10/~m, the stress gradient near the central region is minimal, whereas the stress gradient near the edges is very large. For example, the results obtained at 20 K show that the x-component of the tensile stress gradient near the line edge is about 2 GPa//~m. For a 30/~m wide line, the central 24/~m wide region is under constant tensile stress. Similar results are obtained for the z-component of the stress. In lines less than 10/~m in width, thermally induced stress distributions have large gradients in the central region, and the effects of stress gradients are extended through the complete body. The maximum tensile stress calculated at 20 K is in excess of 550 MPa, which is above the room-temperature aluminum yield strength. However, these lines were thermally cycled a number of times in the 300-10 K temperature range yielding reproducible resistance data, which indicates that the low temperature yield strength is higher than the maximum calculated tensile stress, and the line preserves its structure with no plastic flow. High tensile stresses are related to metal voiding which is a serious interconnect reliability concern[17]. Based on our stress analysis we suggest Fig. 3 is understood in terms of enhanced resistivity in the narrower line, due to high stress gradient at the edge region.
g 2.650
6. C O N C L U S I O N S
Resistance measurements of two IC aluminumbased metallization lines, 10 and 30 pm in width and
2.625
2.600 0
[ 50
I 100
I 150
I 200
I 250
300
T E M P E R A T U R E (K)
Fig. 3. Resistance ratio R(TCIOS)/R(TC30) for the above two lines vs temperature. The error bar on each data point is +0.1%.
*Certain commercial equipment, instruments, or materials are identifiedin order to specify the experimental procedure. Such identification does not imply recommendation or endorsement by NIST, nor does it imply that the materials or equipment identifiedare necessarilythe best available for the purpose described.
Characterization of IC line thickness 0.020
I
I
I
Interface----~_ ~
I
0.020
I
I
1999 i
I
0.015
I
I 2.0
I 2.5
0.018
-.-...>//'"~.~
/'" Middle
E E O.010
~ 0.016
a
"~-Top
%
Y
'-Top
0.005 o9 uJ rr Io9
I
~
~
0
0.014
CL
N 0.012
-0.005 -0.010
) 015
0
I I I 1.0 1.5 2.0 X-DISTANCE (p.m)
I 2.5
3.0
Fig. 4. x-direction stresscomponent,calculatedat 300K, for the three sublayers, as indicated. The annealing temperature is assumed to be 400 K. The coordinate origin is located at the line edge. The inset shows half line cross section with the y-direction along the line thickness and the z-direction along the line length, which is perpendicular to the figure plane. 0.01 x 10 9 Dyne/mm2 = 100 MPa. 0.5/~m thick, were m a d e over the 9.2-295.5 K temperature range. Analysis of these d a t a shows D M R s consistent with those reported for thin aluminum--copper alloy wires with various copper contents (0.025 a t . % - 0 . 6 a t . ° ) . Q u a n t i t a t i v e agreement was observed at temperatures a b o v e approx. 250 K. F r o m this resistivity d a t a correspondence it can be estim a t e d that, at temperatures a r o u n d r o o m ambient, D M R s are within 2 % , for b o t h a l u m i n u m - b a s e d wires or IC interconnects. Based o n electrical resistance data, a formalism was developed to calculate the line cross-sectional area a n d thickness variation with temperature. M e t a l film thickness data, calculated from electrical resistance m e a s u r e d at two different temperatures, agree within the i n s t r u m e n t a l accuracy, with thickness d a t a m e a s u r e d by a calibrated SEM. A n increase o f the low-temperature resistance ratio of these two lines by approx. 2 % , over the r o o m - t e m -
m
0.020
i
i
i
I
0.0101 0
',
Acknowledgements--We are indebted to Dr Hai Tang for calculating line stress distributions. We thank J. M. Thomas for preparing samples for line cross-sectional observation and, S. N. Jones for the SEM operation. This work was partially supported by the National Semiconductor Metrology Program at the National Institute of Standards and Technology.
REFERENCES
1. A S T M F 1261-89, Standard test method for determin-
3. 4.
~Middle
6. >L -0 005
~'Top
-0.010
I 0.5
7. I I I 1.0 1.5 2.0 X-DISTANCE (Itm)
I 2.5
3.0
Fig. 5. y-direction stress component as a function of the x-direction. Stress along the y-direction is very small due to the metal freedom in a direction perpendicular to the substrate.
3.0
perature ratio value, was assumed to be due to differences in stress distributions in these lines. A finite-element stress analysis shows a large stress gradient located at the line edges, which gradually diminishes while extending approx. 3 p m t o w a r d the line center. Thus a larger fraction of the metal in the n a r r o w e r line would be u n d e r the effect o f this stress gradient, which appears to cause a n increase in the resistance ratio.
5. o.oo5 I--
I 1,5
Fig. 6. z-direction stress component as a function of the x-direction. The edge effects are concentrated on a negligible small region in comparison to the line length.
2.
OOlO
I 1.0
X-DISTANCE(pm)
I
m o.o15[
I 0.5
8. 9.
ing the average width and cross-sectional area of a straight thin film metal line. 1989 Annual Book of A S T M Standards, American Society for Testing and Materials, Philadelphia, Pa (1989). A. Matthiessen and C. Vogt, Ann. Phys., Leipzig 122, 19 (1864). J. Bass, Adv. Phys. 21, 431 (1972). P. D. Desai, H. M. James and C. Y. Ho, J. Phys. Chem. Ref. Data 13, 1131 (1984). D. K. C. MacDonald, Electrical conductivity of metals and alloys at low temperatures. In Encyclopedia of Physics (Edited by S. Flugge), Vol. 15, pp. 137-197. Springer, Berlin (1956). J. S. Dugdale and Z. S. Basinski, Phys. Rev. 157, 552 (1967). C. Papastaikoudis, K. Papathanasopoulos, E. Rocofylou and W. Tselfes, Phys. Rev. B 14, 3394 (1976). A. yon Bassewitz and E. N. Mitchell, Phys. Rev. 182, 712 (1969). R. G. Wilson, F. A. Stevie and P. M. Kahora, in Secondary Ion Mass Spectrometry SIMS VIII (Edited by A. Benninghoven, K. T. F. Janssen, J. Trumpner and H. W. Werner), pp. 487-490. Wiley, New York (1992).
2000
Santos Mayo and Harry A. Schafft
10. G. W. Wilson and B. P. Shina, Thin Solid Films 8, 207 (1971). 11. N. Wiser, Contemp. Phys. 25, 211 (1984). 12. R. J. Corrucini and J. Gniewek, Thermal Expansion of Technical Solids at Low Temperatures. National Bureau of Standards, Monograph 29 (1961). 13. H. A. Schafft and J. S. Suehle, SolM-St. Electron. 35, 403 (1992). 14. To calibrate the SEM magnification, a NIST-developed standard reference material, SRM 484c, was used. See NIST Special Publication 260, p. 90 (1990-1991), U.S.
Department of Commerce, National Institute of Standards and Technology. A discussion on calibration uncertainty of this standard can be found in J. Fu, M. C. Croarkin and T. Vorburger, J. Res. NIST 99, 191 (1994). 15. J. A. Thornton, Ann. Rev. Mater. Sci. 7, 239 (1977). 16. J. A. Thornton, J. Vac. Sci. Technol. 11, 666 (1974). 17. M. A. Korhonen, C. A. Paszkiet and C-Y. Li, J. appl. Phys. 69, 8083 (1991).