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Electrical properties of a heterojunction bipolar transistor structure with a resistive gate
Solid-State Electronics Vol. 37, No. 9, pp. 1595-1598,1994 Copyright © 1994ElsevierScienceLtd 0038-1101(93)E0123-I Printed in Great Britain.All rights reserved
Pergamon
0038-1101/94 $7.00+ 0.00
ELECTRICAL PROPERTIES OF A HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE WITH A RESISTIVE GATE HOUNG-CHI WEI, YEONG-HERWANG and MAu-PHON HOUNG Department of Electrical Engineering, National Cheng-Kung Univei'sity, Tainan, Taiwan 70101, Republic of China (Received 7 September 1993; in revised form 24 November 1993)
Abstract--A conventional heterojunction bipolar transistor with a resistive gate, formed by placing the third location in the depletion region of the collector layer instead of the base layer, is investigated. The influencesof the gate voltage on the device performance then strongly depend on the applied voltage. The results show that the device operated under voltage-controlled mode exhibits novel N-shaped negative differential resistance (NDR)" characteristics, which have large room temperature NDR peak-to-valley current ratios (e.g. 140 at a gate bias of 1.5 V) and large voltage extension in N-shaped NDR region (about 9 V). However, the device exhibits the transistor characteristics with the current gain of 4 under current-injected mode. The above discrepanciesbetween voltage-controlledand current-injected modes are attributed to the existence of the resistive gate.
i. INTRODUCTION Heterojunction bipolar transistors (HBTs) have attracted much interest due to their high current gain feature[I,2] and high frequency response[3]. These characteristics are a result of the traditional transistor design, in which the third terminal is in ohmic contact with the base layer. And, the base layer holds the neutral situation under voltagecontrolled and current-injected modes, resulting in a collector current that practically approaches to the emitter current (a ~ 1) and is virtually independent of the collector-base voltage Vca[4]. The device output characteristics exhibit the flat curves except at higher collector currents where the heating effects cause negative differential resistance (NDR) phenomenon[5,6]. Lately, a so-called bipolarunipolar transition transistor possessing a very thin, heavily dope base layer, which is no longer neutral at higher applied voltage, has been used to obtain controllable NDRs and large peak-to-valley current ratios (PTVs) under voltage-controlled and currentinjected modes[7,8]. The N D R devices have also attracted considerable attentions as functional devices due to their ability to achieve many circuits with greatly reduced complexity, especially for the three-terminal N D R device[9]. In this paper, the electrical characteristics of the conventional HBT structure with the thirdterminal contact located in the collector re#on are investigated. The output current is no longer independent of the applied voltage[4]. At smaller applied voltage, a high level current (the peak current) is obtained when we look at characteristics
in terms of transistor operation with the gate voltage to effectively modulate the base-emitter junction. At higher applied voltage, the gate voltage is suppressed, resulting in a very low current (the valley current) that is equivalent to that of the transistor with base-opened operation. As expected, the device exhibits the voltage-controllable NDR characteristics with larger room temperature PTV under voltagecontrolled mode[10]. However, the transistor characteristics are measured under current-injected mode. That is, the proposed device can exhibit either transistor behavior or voltage-controllable NDR behavior, depending on the device operation, which is different from the conventional characteristics of HBT and bipolar-unipolar transistor mentioned above. The operating mechanism of the proposed device will be discussed in detail. 2. DEVICEGROWTHAND FABRICATION The conventional A1GaAs/GaAs HTB structure was grown by molecular beam epitaxy. First, a 3000A GaAs buffer layer with Si doped to 5 x 1018cm-3 was grown on a (100) n+-GaAs substrate, followed by a 5000 A n-GaAs collector layer with Si doped to 5 x 1016cm-3 and a 2000A p +-GaAs base layer with Be doped to 5 x 10n crn -s. Then, a 1000 A N-AIGaAs emitter layer with composition of 0.3 and Si doped to 5 x 10I~cm -3 was grown. Finally a 2000 A n +-GaAs cap layer with Si doped to 5 x 10~acm-3 was deposited for good ohmic contact. In the fabrication process, both lift-off and chemical etching techniques were employed. First,
1595
HOUNG-CHI WEI ef al.
1596
Au/Ge was evaporated and defined by photolithography for the cathode pattern. The cathodemesa mask was then formed for the cathode mesa etching. Conventional HBTs are fabricated by etching a mesa down to the base layer and depositing the base contact. Here the cathode mesa is defined as an etch down from the cap layer to the depletion zone of the collector layer, which constitutes the major difference of our device compared to the conventional HBT device. The etching depth was estimated by the (3: 1:50) etching rate of NH,OH:H,O,:H,O solution and carefully confirmed by the Dektak depth profiler. Au/Zn was self-aligned evaporated and also defined by photolithography for the gate pattem[ 111. Finally, the active device was isolated by device mesa etching using a solution of H,SO,: H,O,: Hz0 (1: 8: 18) and alloyed at 45OC for 30 s in forming N2 gas for the ohmic contact. Good ohmic contact was, hence, made at the cathode. However, alloying causes atomic Zn into the the depletion zone of the collector layer. As a result, a heavily doped p+ region under the gate metal contact was formed[ 121.The p ++I and p+-i-p +-N structures were created at the gateanode and gate-cathode terminals, respectively. The resistive gate is hence formed in the gate-cathode junction. The schematic illustration of the proposed device is shown in Fig. 1. Both the cathode area and the gate area are 1 x 10-4cmZ and the anode area The Z-V characteristics were is 1 x lo-‘cm*. measured by HP4145B semiconductor parameter analyzer and Tektronix 370A. 3. RESULTS AND DISCUSSION
The IA-VAK output characteristic under voltagecontrolled mode is shown in Fig. 2 when the device is operated at a fixed gate bias of 2.5 V. Significant
IA f
&ode
Fig. 1. Schematic illustration of the proposed device.
I&
IA (uA)
CmA)
r
-1.120 1.200
1
IK ,
,
, VAX
,
,
,
.
.88OO/div
% 1 VI
,
-200.0 10.00
Fig. 2. The ZA-VAKcharacteristics under voltage-controlled mode with a gate voltage of 0.5 V. Also, the relationship between the terminal currents Z, , Z, and ZKas a function of VAK are shown.
NDR characteristic is observed, although the offset voltage and the leakage current obviously exist. It is found that the NDR behavior occurs with gate biases larger than 1.2 V in our measurement. In order to understand the mechanism of the NDR occurrence, the terminal currents Zo and Za are measured and employed to explain the carrier transport in the proposed device, as also shown in Fig. 2. The NDR phenomena modelled are described here. As to the numerical results will be presented elsewhere[ 131. . Imtially, a voltage VAKless than the gate voltage is applied to the device, the base-emitter junction is effectively modulated. The electrons from the emitter region then inject into the collector region and constitute the component of the anode current. Certainly, the holes from the p+ region under the gate metal also flow into the collector region and also consitute a component of the anode current. The anode current is hence the addition of the hole current and the electron current, as seen in Fig. 1. However, the hole current is larger than the electron current since the resistive gate exists in the gate-cathode junction, leading to only part of the gate voltage dropping across the base-emitter junction. Consequently, the offset voltage and the leakage current (the negative current) are observed[l4], as shown in Fig. 2. With increasing VAK, the gate voltage on the hole current is seriously suppressed, compared to that on the electron current due to less resistance in the gate-anode junction and the existence of the resistive gate in the gate-cathode junction. As clearly indicated in Fig. 2, the amount of the gate current is reduced more rapidly than the cathode current. The gate current and the cathode current can be considered as the hole current and the electron current, respectively, due to the p + region under the gate metal[4] and the AlGaAs heterostructure in the emitter[l]. Hence the anode current increases and becomes positive with VAK until the peak current is achieved. In such a situation, the hole current plays
Properties of an HBT with a resistive gate
an unimportant role and the anode current is dominated by the electron current. According to the above mentioned, the VAK also suppresses the gate voltage effect on the modulation of the base--emitter junction so that we can regard the operation of the device as a "base resistance modulated" transistor. This result decreases the electron current and yields the N D R behavior. When the V^K is further applied, the influences of the gate voltage on both the currents may be neglected. The device then looks like a transistor operation with a base-opened circuit and the anode current is equivalent to the saturation current, lcEo. The lower valley current is then obtained, resulting in the high PTV ratio at room temperature. At larger V^K, avalanche breakdown will occur in the depletion region of the base-collector junction and the breakdown voltage is similar to that of the measured device with the gate floating. Therefore, the measured results show the highest PTV ratio up to 140 at a gate bias of 1.5 V and the voltage extension of 9 V in the N-shaped N D R region. According to the above mechanism of the N D R occurrence, the hole current initially plays a determining role in the offset voltage and the leakage current. Besides, the hole current limits the peak current, as seen in Fig. 2. It is believed that if the hole current is a minor component in the anode current by designing the device structure, the peak current, the offset voltage, and the leakage current can be improved. For example, the graded emitter or the homojunction emitter design may yield much electron current, and the heterostructure in the collector region may retard the hole transport. The electron current determines the N D R occurrence. As the Zn diffuses into the depletion region of the n-GaAs collector layer, the structure between the gatecathode structure is a p + - i - p ÷ - N junction in which the I - V curve has a diode behavior with the cut-in voltage of 1.2 V. This diode behavior means that the base--emitter junction can be effectively modulated by the gate voltage larger than 1.2 V, resulting in the emitter electron injection. Hence, when the gate voltage is less than the cut-in voltage of gate-cathode junction, it cannot effectively modulate the
1597
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1.2
5.0
1.0
4.0
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>~o3.0 2.0
0.4
1.0
0.2
0"I~I:0
1:0 " 2:0
" 3:0
" 4:0
" 5:8 .0
v,,~(v) Fig. 4. A plot of the gate voltage as a function of V^K. The variation of Vo^ is also shown in the figure. base-emitter junction. The N D R behavior then cannot be measured with the gate voltage less than 1.2 V. Figure 3 shows the PTV and the peak current and the valley current as a function of the gate bias. Although the peak current increases with the increasing gate voltage, the highest PTV occurs at the gate bias of 1.5 V. At higher gate bias, the recombination current in the depletion region of the collector layer and the surface leakage current may be large, as indicated in Fig. 1 by the circle, so that the valley current increases and the PTV decreases. Under the current-injected mode, the fixed gate current is supplied by the curve tracer instrument. In order to maintain the fixed gate current in the device, the gate voltage must increase with increasing the applied voltage which suppresses the hole current, as shown in Fig. 4 at a fixed gate current of 400/~A. Figure 4 also shows the gate voltage with respect to the applied voltage (VcA) as a function of VAK.Since less resistance in the gate-anode junction results in the serious suppression of the gate voltage by the applied voltage, the VCAis slightly decreased with the VAK and is smaller than the cut-in voltage of gate-anode junction (1.0 V). So the gate current flowing through the base-emitter junction is hence constant and the device exhibits transistor curves with a current gain of 4, as shown in Fig. 5. Due to
IA
i:i
......
ISadt~
.......
~l~aMIIII
°
****
/
.,d o
w
.
40
;,
.............. --**
Cam voaa0e, v a ~ Fig. 3. The PTV and the peak current and the valley current as a function of the gate voltage.
/
o
/
/r
/,
/ IVldiv
VAK
Fig. 5. The I^--V^Kcharacteristics under common cathode operation with the gate current of 100/~A per step. The current gain is about 4.
1598
HOUNG-CHIWEI et al.
the recombination current in the depletion region of the collector layer, the current gain is small. 4. CONCLUSION In summary, we have proposed and demonstrated a three-terminal N D R using heterojunction bipolar transistor structure. The gate position is placed in the depletion region in the collector layer, which is a key factor in achieving N D R behavior under voltagecontrolled mode. The proposed device posseses the following characteristics: three-terminal operation, high PTV at r o o m temperature, and larger extension in the N-shaped N D R region. The transistor characteristic is also exhibited under current-injected mode. By optimizing the device structure, the better electrical performances will be expected. Acknowledgement--Tlus work was supported in part by National Science Council of the Republic of China under contract Nos. NSC-81-0404-E006-612 and NSC-82-0404E006-435.
REFERENCES
1. H. Kroemer, Proc. IEEE 70, 13 (1982).
2. P. M. Asbeck, D. L. Miller, R. J. Anderson and F. H. Eisen, IEEE Electron Device Lett. EDL-5, 310 (1984). 3. P. M. Asbeck, D. L. Miller, W. C. Peterson and C. G. Kirkpatrick, IEEE Electron Device Lett. EDL-3, 366 (1982). 4. S. M. Sze, Physics o f Semiconductor Device, 2nd Edn. Wiley-lnterscience, New York (1981). 5. R. Hayes, F. Capasso, A. C. Gossard, R. J. Malik and W. Wiegmann, Electron. Lett. No. 19, 140 0983). 6. G. B. Gao, Z. F. Fan and H. Morkoc, Appl. Phys. Lett. 61, 198 (1992). 7. K. F. Yarn, Y. H. Wang and C. Y. Chang, Appl. Phys. Left. 54, 1157 (1989). 8. K. F. Yarn, Y. H. Wang and C. Y. Chang, Appl. Phys. Lett. 57, 777 (1990). 9. F. Capasso, S. Sen, F. Beltram, L. M. Lunard, A. S. Vengurlekar, P. R. Smith, N. J. Shah, R. J. Malik and A. Y. Cho, IEEE Electron Devices 36, 2065 (1989). 10. H. C. Wei, Y. H. Wang and M. P. Houng, Proc. Int. Symp. GaAs and Related Compounds, Karuizawa (1992). 11. K. Eda, M. Inada, Y. Ota, A. Nakagawa, T. Hirose and M. Yanagihara, IEEE Electron Device Lett. EDL-7, 694 (1986). 12. S. Tiwari, A. Ginzberg, S. Akhtar, S. L. Wright, R. F. Marks, Y. H. Kwark and R. Kiehl, IEEE Electron Device Lett. EDL-9, 422 (1988). 13. H. C. Wei, Y. H. Wang and M. P. Houng, to be published. 14. S. C. Lee, J. N. Kuo and H. H. Lin, Appl. Phys. Left. 40, 1114 (1984).
Pergamon
0038-1101/94 $7.00+ 0.00
ELECTRICAL PROPERTIES OF A HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE WITH A RESISTIVE GATE HOUNG-CHI WEI, YEONG-HERWANG and MAu-PHON HOUNG Department of Electrical Engineering, National Cheng-Kung Univei'sity, Tainan, Taiwan 70101, Republic of China (Received 7 September 1993; in revised form 24 November 1993)
Abstract--A conventional heterojunction bipolar transistor with a resistive gate, formed by placing the third location in the depletion region of the collector layer instead of the base layer, is investigated. The influencesof the gate voltage on the device performance then strongly depend on the applied voltage. The results show that the device operated under voltage-controlled mode exhibits novel N-shaped negative differential resistance (NDR)" characteristics, which have large room temperature NDR peak-to-valley current ratios (e.g. 140 at a gate bias of 1.5 V) and large voltage extension in N-shaped NDR region (about 9 V). However, the device exhibits the transistor characteristics with the current gain of 4 under current-injected mode. The above discrepanciesbetween voltage-controlledand current-injected modes are attributed to the existence of the resistive gate.
i. INTRODUCTION Heterojunction bipolar transistors (HBTs) have attracted much interest due to their high current gain feature[I,2] and high frequency response[3]. These characteristics are a result of the traditional transistor design, in which the third terminal is in ohmic contact with the base layer. And, the base layer holds the neutral situation under voltagecontrolled and current-injected modes, resulting in a collector current that practically approaches to the emitter current (a ~ 1) and is virtually independent of the collector-base voltage Vca[4]. The device output characteristics exhibit the flat curves except at higher collector currents where the heating effects cause negative differential resistance (NDR) phenomenon[5,6]. Lately, a so-called bipolarunipolar transition transistor possessing a very thin, heavily dope base layer, which is no longer neutral at higher applied voltage, has been used to obtain controllable NDRs and large peak-to-valley current ratios (PTVs) under voltage-controlled and currentinjected modes[7,8]. The N D R devices have also attracted considerable attentions as functional devices due to their ability to achieve many circuits with greatly reduced complexity, especially for the three-terminal N D R device[9]. In this paper, the electrical characteristics of the conventional HBT structure with the thirdterminal contact located in the collector re#on are investigated. The output current is no longer independent of the applied voltage[4]. At smaller applied voltage, a high level current (the peak current) is obtained when we look at characteristics
in terms of transistor operation with the gate voltage to effectively modulate the base-emitter junction. At higher applied voltage, the gate voltage is suppressed, resulting in a very low current (the valley current) that is equivalent to that of the transistor with base-opened operation. As expected, the device exhibits the voltage-controllable NDR characteristics with larger room temperature PTV under voltagecontrolled mode[10]. However, the transistor characteristics are measured under current-injected mode. That is, the proposed device can exhibit either transistor behavior or voltage-controllable NDR behavior, depending on the device operation, which is different from the conventional characteristics of HBT and bipolar-unipolar transistor mentioned above. The operating mechanism of the proposed device will be discussed in detail. 2. DEVICEGROWTHAND FABRICATION The conventional A1GaAs/GaAs HTB structure was grown by molecular beam epitaxy. First, a 3000A GaAs buffer layer with Si doped to 5 x 1018cm-3 was grown on a (100) n+-GaAs substrate, followed by a 5000 A n-GaAs collector layer with Si doped to 5 x 1016cm-3 and a 2000A p +-GaAs base layer with Be doped to 5 x 10n crn -s. Then, a 1000 A N-AIGaAs emitter layer with composition of 0.3 and Si doped to 5 x 10I~cm -3 was grown. Finally a 2000 A n +-GaAs cap layer with Si doped to 5 x 10~acm-3 was deposited for good ohmic contact. In the fabrication process, both lift-off and chemical etching techniques were employed. First,
1595
HOUNG-CHI WEI ef al.
1596
Au/Ge was evaporated and defined by photolithography for the cathode pattern. The cathodemesa mask was then formed for the cathode mesa etching. Conventional HBTs are fabricated by etching a mesa down to the base layer and depositing the base contact. Here the cathode mesa is defined as an etch down from the cap layer to the depletion zone of the collector layer, which constitutes the major difference of our device compared to the conventional HBT device. The etching depth was estimated by the (3: 1:50) etching rate of NH,OH:H,O,:H,O solution and carefully confirmed by the Dektak depth profiler. Au/Zn was self-aligned evaporated and also defined by photolithography for the gate pattem[ 111. Finally, the active device was isolated by device mesa etching using a solution of H,SO,: H,O,: Hz0 (1: 8: 18) and alloyed at 45OC for 30 s in forming N2 gas for the ohmic contact. Good ohmic contact was, hence, made at the cathode. However, alloying causes atomic Zn into the the depletion zone of the collector layer. As a result, a heavily doped p+ region under the gate metal contact was formed[ 121.The p ++I and p+-i-p +-N structures were created at the gateanode and gate-cathode terminals, respectively. The resistive gate is hence formed in the gate-cathode junction. The schematic illustration of the proposed device is shown in Fig. 1. Both the cathode area and the gate area are 1 x 10-4cmZ and the anode area The Z-V characteristics were is 1 x lo-‘cm*. measured by HP4145B semiconductor parameter analyzer and Tektronix 370A. 3. RESULTS AND DISCUSSION
The IA-VAK output characteristic under voltagecontrolled mode is shown in Fig. 2 when the device is operated at a fixed gate bias of 2.5 V. Significant
IA f
&ode
Fig. 1. Schematic illustration of the proposed device.
I&
IA (uA)
CmA)
r
-1.120 1.200
1
IK ,
,
, VAX
,
,
,
.
.88OO/div
% 1 VI
,
-200.0 10.00
Fig. 2. The ZA-VAKcharacteristics under voltage-controlled mode with a gate voltage of 0.5 V. Also, the relationship between the terminal currents Z, , Z, and ZKas a function of VAK are shown.
NDR characteristic is observed, although the offset voltage and the leakage current obviously exist. It is found that the NDR behavior occurs with gate biases larger than 1.2 V in our measurement. In order to understand the mechanism of the NDR occurrence, the terminal currents Zo and Za are measured and employed to explain the carrier transport in the proposed device, as also shown in Fig. 2. The NDR phenomena modelled are described here. As to the numerical results will be presented elsewhere[ 131. . Imtially, a voltage VAKless than the gate voltage is applied to the device, the base-emitter junction is effectively modulated. The electrons from the emitter region then inject into the collector region and constitute the component of the anode current. Certainly, the holes from the p+ region under the gate metal also flow into the collector region and also consitute a component of the anode current. The anode current is hence the addition of the hole current and the electron current, as seen in Fig. 1. However, the hole current is larger than the electron current since the resistive gate exists in the gate-cathode junction, leading to only part of the gate voltage dropping across the base-emitter junction. Consequently, the offset voltage and the leakage current (the negative current) are observed[l4], as shown in Fig. 2. With increasing VAK, the gate voltage on the hole current is seriously suppressed, compared to that on the electron current due to less resistance in the gate-anode junction and the existence of the resistive gate in the gate-cathode junction. As clearly indicated in Fig. 2, the amount of the gate current is reduced more rapidly than the cathode current. The gate current and the cathode current can be considered as the hole current and the electron current, respectively, due to the p + region under the gate metal[4] and the AlGaAs heterostructure in the emitter[l]. Hence the anode current increases and becomes positive with VAK until the peak current is achieved. In such a situation, the hole current plays
Properties of an HBT with a resistive gate
an unimportant role and the anode current is dominated by the electron current. According to the above mentioned, the VAK also suppresses the gate voltage effect on the modulation of the base--emitter junction so that we can regard the operation of the device as a "base resistance modulated" transistor. This result decreases the electron current and yields the N D R behavior. When the V^K is further applied, the influences of the gate voltage on both the currents may be neglected. The device then looks like a transistor operation with a base-opened circuit and the anode current is equivalent to the saturation current, lcEo. The lower valley current is then obtained, resulting in the high PTV ratio at room temperature. At larger V^K, avalanche breakdown will occur in the depletion region of the base-collector junction and the breakdown voltage is similar to that of the measured device with the gate floating. Therefore, the measured results show the highest PTV ratio up to 140 at a gate bias of 1.5 V and the voltage extension of 9 V in the N-shaped N D R region. According to the above mechanism of the N D R occurrence, the hole current initially plays a determining role in the offset voltage and the leakage current. Besides, the hole current limits the peak current, as seen in Fig. 2. It is believed that if the hole current is a minor component in the anode current by designing the device structure, the peak current, the offset voltage, and the leakage current can be improved. For example, the graded emitter or the homojunction emitter design may yield much electron current, and the heterostructure in the collector region may retard the hole transport. The electron current determines the N D R occurrence. As the Zn diffuses into the depletion region of the n-GaAs collector layer, the structure between the gatecathode structure is a p + - i - p ÷ - N junction in which the I - V curve has a diode behavior with the cut-in voltage of 1.2 V. This diode behavior means that the base--emitter junction can be effectively modulated by the gate voltage larger than 1.2 V, resulting in the emitter electron injection. Hence, when the gate voltage is less than the cut-in voltage of gate-cathode junction, it cannot effectively modulate the
1597
8.0
1.2
5.0
1.0
4.0
0.8 !0..
>~o3.0 2.0
0.4
1.0
0.2
0"I~I:0
1:0 " 2:0
" 3:0
" 4:0
" 5:8 .0
v,,~(v) Fig. 4. A plot of the gate voltage as a function of V^K. The variation of Vo^ is also shown in the figure. base-emitter junction. The N D R behavior then cannot be measured with the gate voltage less than 1.2 V. Figure 3 shows the PTV and the peak current and the valley current as a function of the gate bias. Although the peak current increases with the increasing gate voltage, the highest PTV occurs at the gate bias of 1.5 V. At higher gate bias, the recombination current in the depletion region of the collector layer and the surface leakage current may be large, as indicated in Fig. 1 by the circle, so that the valley current increases and the PTV decreases. Under the current-injected mode, the fixed gate current is supplied by the curve tracer instrument. In order to maintain the fixed gate current in the device, the gate voltage must increase with increasing the applied voltage which suppresses the hole current, as shown in Fig. 4 at a fixed gate current of 400/~A. Figure 4 also shows the gate voltage with respect to the applied voltage (VcA) as a function of VAK.Since less resistance in the gate-anode junction results in the serious suppression of the gate voltage by the applied voltage, the VCAis slightly decreased with the VAK and is smaller than the cut-in voltage of gate-anode junction (1.0 V). So the gate current flowing through the base-emitter junction is hence constant and the device exhibits transistor curves with a current gain of 4, as shown in Fig. 5. Due to
IA
i:i
......
ISadt~
.......
~l~aMIIII
°
****
/
.,d o
w
.
40
;,
.............. --**
Cam voaa0e, v a ~ Fig. 3. The PTV and the peak current and the valley current as a function of the gate voltage.
/
o
/
/r
/,
/ IVldiv
VAK
Fig. 5. The I^--V^Kcharacteristics under common cathode operation with the gate current of 100/~A per step. The current gain is about 4.
1598
HOUNG-CHIWEI et al.
the recombination current in the depletion region of the collector layer, the current gain is small. 4. CONCLUSION In summary, we have proposed and demonstrated a three-terminal N D R using heterojunction bipolar transistor structure. The gate position is placed in the depletion region in the collector layer, which is a key factor in achieving N D R behavior under voltagecontrolled mode. The proposed device posseses the following characteristics: three-terminal operation, high PTV at r o o m temperature, and larger extension in the N-shaped N D R region. The transistor characteristic is also exhibited under current-injected mode. By optimizing the device structure, the better electrical performances will be expected. Acknowledgement--Tlus work was supported in part by National Science Council of the Republic of China under contract Nos. NSC-81-0404-E006-612 and NSC-82-0404E006-435.
REFERENCES
1. H. Kroemer, Proc. IEEE 70, 13 (1982).
2. P. M. Asbeck, D. L. Miller, R. J. Anderson and F. H. Eisen, IEEE Electron Device Lett. EDL-5, 310 (1984). 3. P. M. Asbeck, D. L. Miller, W. C. Peterson and C. G. Kirkpatrick, IEEE Electron Device Lett. EDL-3, 366 (1982). 4. S. M. Sze, Physics o f Semiconductor Device, 2nd Edn. Wiley-lnterscience, New York (1981). 5. R. Hayes, F. Capasso, A. C. Gossard, R. J. Malik and W. Wiegmann, Electron. Lett. No. 19, 140 0983). 6. G. B. Gao, Z. F. Fan and H. Morkoc, Appl. Phys. Lett. 61, 198 (1992). 7. K. F. Yarn, Y. H. Wang and C. Y. Chang, Appl. Phys. Left. 54, 1157 (1989). 8. K. F. Yarn, Y. H. Wang and C. Y. Chang, Appl. Phys. Lett. 57, 777 (1990). 9. F. Capasso, S. Sen, F. Beltram, L. M. Lunard, A. S. Vengurlekar, P. R. Smith, N. J. Shah, R. J. Malik and A. Y. Cho, IEEE Electron Devices 36, 2065 (1989). 10. H. C. Wei, Y. H. Wang and M. P. Houng, Proc. Int. Symp. GaAs and Related Compounds, Karuizawa (1992). 11. K. Eda, M. Inada, Y. Ota, A. Nakagawa, T. Hirose and M. Yanagihara, IEEE Electron Device Lett. EDL-7, 694 (1986). 12. S. Tiwari, A. Ginzberg, S. Akhtar, S. L. Wright, R. F. Marks, Y. H. Kwark and R. Kiehl, IEEE Electron Device Lett. EDL-9, 422 (1988). 13. H. C. Wei, Y. H. Wang and M. P. Houng, to be published. 14. S. C. Lee, J. N. Kuo and H. H. Lin, Appl. Phys. Left. 40, 1114 (1984).