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Electrical properties of CdTe metal-semiconductor field effect transistors
FET VLSI circuits arc considered. Power dissipation sets an upper complexity limit for a given logic circuit implemen/ation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates the logic chips of 15000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits will be needed to extend circuit complexity to the range currently dominated by silicon. (23 refs.) Sub-huif micrometer gate rift-off by three layer resist process via electron beam lithography for gallium arsenide monolithic microwave integrated circuits (MIMICs) R M NAGARAJAN, S D RASK, M R KING, T K YARD (Gallium Arsenide Components Group, Unisys Corp., Eagan, MN, USA) Proc. SPIE - - InL Soc. O p t Eng. (USA), vol. 923, pp. 194--200 (1988). (Electron-Beam, X-Ray, and IonBeam Technology: Submicrometer Lithographies VII, Santa Clara, CA. USA. 2-4 March 1988) A three layer resist process for gate lift-off on gallium arsenide MIMICs by electron beam and optical lithographies is described. The electron beam lithography process consists of poly (dimethyl glutarimide) PMGI as the planarising layer, a plasma enhanced chemical vapour deposition silicon nitride (SIN) as an intermediate barrier layer and poly (methyl methacrylate), PMMA. as the top imaging layer. The PMMA is exposed by Cambridge electron beam system EBMF 6.4 at 20 keV and developed in methyl ethyl kctone/isopropyl alcohol. The pattern is then transferred to the SiN layer by CF4/O2 plasma etching. The SiN layer is then used as the mask to transfer the pattel'~, to the PMGI layer by 02 reactive ion etching until the GaAs is exposed. The various processing parameters are optimised to obtain lip or overhang suitable for lift--off with 0.20 lam gate dimension. After the GaAs has been recessed (to reduce the parasitic source resistance), a thick 9000 A Ti/Pt/Au gate metal is evaporated and the unwanted gate metal is lifted off using PMGI stripper. (4 refs.) Electron beam/optical hybrid lithography for the productiun of gallium arsenide monolithic microwave integrated circuits (MIMICs) R M NAGARAJAN, S D RASK (Gallium Arsenidc Components Group, Unisys Corp., Eagan, MN, USA) Proc. SPIE - - lnL Soc. Opt. Eng. (USA), vol. 923, pp. 266--273 (1988). (Electron-Beam, X-Ray, and IonBeam Technology: Submicrometer Lithographies VII. Santa Clara, CA. USA. 2--4 March 1988) A hybrid lithography technique is described in which selected levels are fabricated by high resolution direct
write electron beam lithography and all other levels are fabricated optically. This technique permits sub-half micron geometries and the site-by-site alignment for each field written by electron beam lithography while still maintaining the high throughput possible with optical lithography. Analysis of planar channeling effects on the threshold voltage uniformity of GaAs metal-semiconductor fieldeffect transistors using stereographic projection H MIKAMI, N UCHITOMI, N TOYODA (VLSI Res. Center, Toshiba Corp., Kawasaki, Japan) J. Appl. Phys. (USA), vol. 64, no. 2, pp. 610-613 (15 July 1988) Planar channeling effects on the threshold voltage uniformity of GaAs metal-semiconductor field-effect transistors within 3-in. GaAs wafers have been investigated using the stereographic projection method. This method is very useful for a quantitative understanding of the angular relationship between the direction of an incident ion beam and wafer orientation during implantation. The ratio N(XO/N(X2) of the peak carrier concentration at a depth of X~ to the carrier concentration of a depth of X2 = 2X1, obtained from the carrier depth profiles, was employed as a suitable parameter which effectively reflects the variation in the carrier profiles arising from the planar channeling effects. The conclusion, that the most uniform implants are attained at an azimuthal angle of 26.5 ° when tilting the wafer 10 °, was analytically derived from the stereographic projection method and was experimentally confirmed. (9 refs.)
Electrical properties of CdTe metui-semiconductor field effect transistors D I DREIFUS, R M KOLBAS (Dept. of Electr. & Cornput. Eng., North Carolina State Univ., Raleigh, NC, USA), J R TASSITINO, R L HARPER, R N BICKNELL, J F SCHETZINA J. Vac. Sci. Technol. A. Vac. Surf. Films (USA), vol. 6, no. 4, pp. 2722-2724 (July-Aug. 1988). (1987 U.S. Workshop on the Physics and Chemistry of Mercury Cadmium TeUuride, New Orleans, LA, USA, 6--8 Oct. 1987) Interest in CdTc field effect transistor and multigated devices stems from the fact that CdTe is lattice matched to HgCdTe. As a consequence, it may be possible to develop a monolithic technology that combines HgCdTe infrared focal plane arrays with on-board signal processing based on CdTe devices. Although CdTe metal-semiconductor field effect transistors have only recently been fabricated for the first time, rapid improvements in device performance have been realised. All of the devices studied to date have employed CdTe:In epilayers grown by photoassisted molecular-beam epitaxy. The authors report devices having gold Schottky barriers with reverse breakdown voltages as high as 13.5 V and ideality factors approaching 1,2 which exhibit good depletion mode transistor action. Also, carrier concentrations determined by capacitance-voltage measurements agree with Hall-effect measurements. (11 refs.)
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write electron beam lithography and all other levels are fabricated optically. This technique permits sub-half micron geometries and the site-by-site alignment for each field written by electron beam lithography while still maintaining the high throughput possible with optical lithography. Analysis of planar channeling effects on the threshold voltage uniformity of GaAs metal-semiconductor fieldeffect transistors using stereographic projection H MIKAMI, N UCHITOMI, N TOYODA (VLSI Res. Center, Toshiba Corp., Kawasaki, Japan) J. Appl. Phys. (USA), vol. 64, no. 2, pp. 610-613 (15 July 1988) Planar channeling effects on the threshold voltage uniformity of GaAs metal-semiconductor field-effect transistors within 3-in. GaAs wafers have been investigated using the stereographic projection method. This method is very useful for a quantitative understanding of the angular relationship between the direction of an incident ion beam and wafer orientation during implantation. The ratio N(XO/N(X2) of the peak carrier concentration at a depth of X~ to the carrier concentration of a depth of X2 = 2X1, obtained from the carrier depth profiles, was employed as a suitable parameter which effectively reflects the variation in the carrier profiles arising from the planar channeling effects. The conclusion, that the most uniform implants are attained at an azimuthal angle of 26.5 ° when tilting the wafer 10 °, was analytically derived from the stereographic projection method and was experimentally confirmed. (9 refs.)
Electrical properties of CdTe metui-semiconductor field effect transistors D I DREIFUS, R M KOLBAS (Dept. of Electr. & Cornput. Eng., North Carolina State Univ., Raleigh, NC, USA), J R TASSITINO, R L HARPER, R N BICKNELL, J F SCHETZINA J. Vac. Sci. Technol. A. Vac. Surf. Films (USA), vol. 6, no. 4, pp. 2722-2724 (July-Aug. 1988). (1987 U.S. Workshop on the Physics and Chemistry of Mercury Cadmium TeUuride, New Orleans, LA, USA, 6--8 Oct. 1987) Interest in CdTc field effect transistor and multigated devices stems from the fact that CdTe is lattice matched to HgCdTe. As a consequence, it may be possible to develop a monolithic technology that combines HgCdTe infrared focal plane arrays with on-board signal processing based on CdTe devices. Although CdTe metal-semiconductor field effect transistors have only recently been fabricated for the first time, rapid improvements in device performance have been realised. All of the devices studied to date have employed CdTe:In epilayers grown by photoassisted molecular-beam epitaxy. The authors report devices having gold Schottky barriers with reverse breakdown voltages as high as 13.5 V and ideality factors approaching 1,2 which exhibit good depletion mode transistor action. Also, carrier concentrations determined by capacitance-voltage measurements agree with Hall-effect measurements. (11 refs.)
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