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Electrical properties of Pt interconnects for passive crossbar memory arrays
Microelectronic Engineering 86 (2009) 2275–2278
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Electrical properties of Pt interconnects for passive crossbar memory arrays R. Rosezin a, C. Nauenheim a, S. Trellenkamp b, C. Kügeler a,*, R. Waser a,c,d a
Institut für Festkörperforschung, Forschungszentrum Jülich GmbH, Jülich 52425, Germany Institut für Bio- und Nanosysteme, Forschungszentrum Jülich GmbH, Jülich 52425, Germany Institut für Werkstoffe der Elektrotechnik II, RWTH Aachen, Aachen 52074, Germany d JARA- Fundamentals of Future Information Technology, Germany b c
a r t i c l e
i n f o
Article history: Received 16 December 2008 Received in revised form 6 March 2009 Accepted 7 April 2009 Available online 18 April 2009 Keywords: Nano electrodes Nano crossbar arrays Nano structuring Resistive switching
a b s t r a c t We report on the fabrication and the electrical characterization of platinum interconnects for novel nonvolatile memory technologies. These nanowires present an important and essential contribution to the deep nanometer scaling of alternative architectures beyond CMOS, e.g. nanocrossbar arrays with resistance switching junctions. The nanowires, which have a thickness of 25 nm and a width ranging from 200 nm down to 40 nm, were patterned using electron beam direct writing. They were deposited by UHV electron beam evaporation in combination with a lift-off process. The electrical characteristic is increasingly affected by the contribution of surface effects like scattering at grain boundaries and scattering at the surfaces as the wire dimensions become smaller. With decreasing width of the platinum wire an increasing resistivity was observed, which is consistent with the theories of Fuchs-Sondheimer and Mayadas-Shatzkes. Our studies have shown that the investigated structures possess a high stability concerning the operational current densities up to 4 107 A/cm2, and an additional annealing step results in an improvement of the electrical wire properties, which is explained by a higher quality of the grain boundaries and side walls. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction The pursuit to extend the performance gain of devices in information and communication technology continues according to Moore’s law. With the intention to manage the emerging physical and economical limits, alternative concepts beyond CMOS attract attention. A fundamental approach to build storage devices is the application of resistance switching materials with at least two different, switchable resistance states. These resistances can be interpreted as ‘1’ (low resistance) and ‘0’ (high resistance), whereas intermediate states offer the opportunity of multiple bits per cell, adding up to a higher integration density [1]. To toggle these devices write signals which exceed certain thresholds have to be applied, thus writing or erasing the resistance states. The non-volatile information can be retrieved with a read signal well below these thresholds. The simple configuration of a bottom electrode, the functional material and a top electrode allows for a two terminal device with a high potential for future integration aspects. Crossbar arrays [2,3] create these devices at every junction and are the basis for alternative, inexpensive fabrication processes, e.g. nano-imprint lithography, which additionally offers the suitability for a high throughput [4,5]. Our aim is the investigation of a suitable electrode for a pas* Corresponding author. Tel.: +49 2461 616074; fax: +49 2461 612550. E-mail address: [email protected] (C. Kügeler). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.04.004
sive crossbar array adapted for an adequate resistance switching material. Such material candidates were examined and described numerously during the last decades, including solid electrolytes [6,7], ternary oxides [1,8,9], binary oxides [10,11], and phase change compounds [12,13]. Some promising materials require a combination with an inert electrode or interconnect structure [14]. We performed detailed examinations of platinum interconnects, as this avoids undesirable effects such as oxidizing interfaces with base metals or creation of metallic filaments from diffusive electrode materials like Cu and Ag. The reduction of the conductor thickness and its width into the nanometer region emphasizes ballistic effects in addition to linear dimensional dependencies. As the mean free path of the electrons becomes comparable to the wire size, surface scattering as well as the backscattering at grain boundaries becomes relevant. Both effects increase the resistivity of the platinum and may limit the downscaling of the wire dimensions for real device operation. If the resistance of a single address-wire within an array becomes much larger than the ON resistance of the device, a disproportional high erase voltage has to be applied. However, the value of the erase voltage is technically limited by a specific input signal. Another important design issue concerns the voltage gradient along a single conductor due to its resistance during operation. The voltage drop over the outermost cells in the OFF state has to be higher than the voltage drop over any arbitrarily addressed cell in the ON state including its connecting line as described by Mustafa and
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Waser [15]. Therefore, the size effect on the resistivity might influence the maximum array size. The aim of this work is to show that at low feature sizes the platinum conductors still have a sufficient specific resistivity and are able to endure the necessary current densities. 2. Fabrication The process flow for the fabrication of platinum nanowires is shown in Fig. 1. Here, electron beam lithography is the key process. To obtain a suitable undercut for lift-off, a two layer resist process was employed. In a first step, polymethyl methacrylate methyl acrylic acid (PMMA-MAA) was spun upon the SiO2 surface of a 1 in. sample. After baking for two minutes at 210 °C, a layer of polymethyl methacrylate (PMMA) with a molecular weight of 950 K was spun on top (Fig. 1a). This layer was baked for two minutes at 180 °C. The sample was then patterned with a Leica EBPG 5000 Plus electron beam writer (Fig. 1b) with a dose of 300 lC/cm2. Since the PMMA-MAA has a much higher sensitivity regarding electron than the PMMA, an undercut is produced. After developing in methyl-isobutyl-ketone mixed with isopropyl alcohol for 75 s at room temperature and stopping in isopropyl alcohol (Fig. 1c), a thin adhesion layer of around 5 nm titanium was e-beam evaporated on the patterned sample surface. In situ, the 25 nm thick layer of platinum was then evaporated on top (Fig. 1d). The metallization was performed at room temperature with a background pressure in the range of 107 mbar and a deposition rate below 5 Å s1. The thickness of both layers was monitored using a quartz crystal oscillator. The excess metal on the unexposed e-beam resist was then removed by lift-off in an acetone bath (Fig. 1e). In this case, the titanium underneath the platinum is necessary to provide adhesion to the underlying SiO2. The influence of this layer on the electrical measurement results can be neglected since the layer is very thin. The error introduced is estimated to give values for the resistance which are less than 5% lower, compared to a wire without the adhesion layer. A scanning electron micrograph of a structure with a wire width of 50 nm is shown in Fig. 2. 3. Experimental The electrical characterization of the fabricated structures was conducted by an Agilent B1500A semiconductor device analyzer
Fig. 2. SEM micrograph of a 4-point test structure with a wire width of 50 nm.
in combination with a probe station from Süss Microtec. To study the influence of the wire dimensions on the resistivity, the resistance of various wires with widths ranging from 200 nm down to 40 nm was measured. Fig. 3 shows some exemplary R(I)-traces for different wire widths which were used to extract the resistivity. The wire length of 2 lm and the platinum thickness of 25 nm were kept constant for all samples. To provide comparability for all characterized wires with different width, and to avoid any process dependent variations of the maintained data, all measured structures were fabricated within the very same process flow on one substrate. Tests of several samples were performed, to assure the reproducibility of the obtained results. All measurements were conducted at room temperature. For the interpretation of the electrical measurements, we consider two additional effects that contribute to the basic resistivity of the wire. The first one is a scattering of electrons at the surface of the metal, according to the Fuchs-Sondheimer theory [16], and the second one is grain boundary scattering, as described by the model of Mayadas and Shatzkes [17]. Steinhögl et al. [18,19] combined both models for rectangular copper wires corresponding to Eq. (1):
q 1 1 1 ¼ 2C k0 ð1 pÞ þ þ q0 t w 1 32a þ 3a2 3a3 ln 1 þ a1
Fig. 1. Fabrication process flow for platinum nanowires. (a) Deposition of a double layer resist, (b) Electron beam patterning, (c) Development, (d) Blanket evaporation of Ti and Pt, (e) Lift-off in acetone, (f) final structure.
Fig. 3. Exemplary R (I) traces for different line widths.
ð1Þ
R. Rosezin et al. / Microelectronic Engineering 86 (2009) 2275–2278
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In this equation, C = 1.2 is a geometry factor for rectangular wire cross-sections, k0 = 23 nm is the electron mean free path of platinum at room temperature [20] and q0 = 10.5 108 Xm is the bulk resistivity of platinum [21]. The parameters w and t denote the width and the thickness of the wire, respectively. The amount of specular scattering at the walls, modelled by p, can take values ranging from 0 to 1. In the case of p = 1, an entirely specular reflection occurs at the surface, resulting in no additional contribution to the resistivity. The direct opposite is a complete diffuse scattering that results in a maximum contribution to the resistance and which is described by p = 0. Grain boundaries are the microstructural properties of the wire that influence its resistance considerably, if the dimensions of the conductor approach the same order of magnitude as the grain size d. The impact on the resistance is described by the factor a, where
a¼
k0 R : d 1R
ð2Þ
R is the probability of scattering at grain boundaries within the material. If all electrons are scattered at grain boundaries, no conduction can take place and R = 1. By contrast, grain boundaries are not affecting the resistance, if no scattering occurs and R = 0. A simplified visualization of sidewall scattering and grain boundary scattering can be found in Fig. 4. The values of the mean grain size d were gathered from SEM micrographs of the fabricated structures. The diameter in-plane in relation to the charge transfer varies from 6 nm for smaller wires to 15 nm for expanded wires. For the following calculations a linear fit of the acquired grain diameters is used. The measured resistances are normalized to the bulk resistivity and are shown in Fig. 5. The value of the extracted resistivity increases considerably for decreasing wire width. The solid line represents a least squares fit (with an error of 14.4%) to the measurement data. The extracted parameters according to the formula given above are p = 0.48 and R = 0.22. This indicates fairly good microstructural properties and a quite large part of diffuse scattering at the side walls. The error bars shown in both figures are taken from minimum and maximum observed values. Further process and integration steps include a thermal treatment concerning the embedding of the electrodes or the application of the switching material [22]. For this reason, the electrical characteristics of platinum wires were tested after an annealing process of 1 h at 425 °C under nitrogen atmosphere in a Centrotherm rapid thermal annealing furnace, which is within the thermal budget of CMOS processing. The subsequent analysis revealed, as shown in Fig. 6, that the resistivity of the wires was lowered substantially. Calculations using the least squares method give an error of less than 5.5 % with
Fig. 4. Schematic top view of a conductor with simplified description of sidewall and grain boundary scattering.
Fig. 5. Normalized resistivity versus wire width of the as deposited sample. The solid points indicate the values found experimentally, the solid line represents the fit according to the combined model and the dashed line is the bulk value for platinum.
Fig. 6. Normalized resistivity versus wire width of the sample annealed at 425 °C. The solid points indicate the values found experimentally, the solid line represents the fit according to the combined model and the dashed line is the bulk value for platinum.
values of p = 0.74 and R = 0.14, indicating an improved wire quality due to less scattering at the grain boundaries and a more specular sidewall. Compared to the not annealed state, the resistivity in the annealed state is about 30% lower for all data points. Additionally, as-deposited structures were treated at 600 °C for one hour showing a similar improvement in resistivity. Since there was no significant improvement in resistivity compared to the 425 °C process, this annealing temperature is fully sufficient to improve wire quality, ensuring CMOS compatibility with regard to the thermal budget. Also, this provides full availability of the processes and materials typically used to fabricate resistively switching nanocrossbar arrays. No comparable study has been conducted for platinum wires in this range of dimensions. However, some data on platinum nanofilms exists. The existent values for the parameter R range from 0.35 to 0.8 [23], which indicates the good quality of the produced wires within this study. For the sidewall scattering, one could refer to studies on copper where the values for p are in the range between 0.33 and 0.6 [24]. In these studies it has also been pointed out that p and R are strongly correlated. The improvement of the quality due to an annealing step might result from defect healing in the nanowires.
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Additionally, wires were stressed by a current which is considerably higher than those which typically arise during write and erase operations. To estimate the impact on platinum wires in crossbar arrays, a 100 nm wide conductor with a length of several microns was operated with 1 mA for more than 12 h. This corresponds to a current density of 4 107 A/cm2. The resistance stays constant at 9.6 kX without significant changes or a thermo electrical break. This result proves that a conductor can be scaled down to achieve higher integration densities without sacrificing any compatibility with materials and operation modes. However, problems might arise due to an increasing current density as consequence of a decreasing wire cross-section. 4. Summary We have fabricated rectangular platinum nanowires by electron beam lithography and UHV electron beam evaporation with a width down to 40 nm and a constant thickness of 25 nm. The resistance of these wires was characterized by DC-Kelvin probing. An increase in resistivity was found with decreasing wire width which can be explained and modelled by a combination of the Fuchs-Sondheimer and Mayadas-Shatzkes theory. The resistivity of the platinum could be reduced by an annealing step which was carried out under nitrogen atmosphere. This improvement in resistivity was attributed to a better quality of grain boundaries and sidewalls. The increase in wire resistance due to size effects is negligible for a single section of an array if compared to the on/off ratio, which is a few orders of magnitude for typical materials. Therefore, the cell behaviour is still dominated by switching effects. It was shown that the conductors clearly facilitate the typical operating currents which are expected for such materials in future crossbar memory devices. In summary, for the application as conductors in a crossbar array or other nano-sized devices, platinum wires show high potential for future downscaling in face of increasing resistivity with lower line width and occurring limits for the possible size of crossbar arrays. Acknowledgements The authors would like to thank Hans Haselier (IFF) and Hans Wingens (IBN) for the metallization of the samples as well as Prof. Dr. Herbert Schroeder (IFF) for fruitful discussions.
References [1] A. Beck, J.G. Bednorz, C. Gerber, C. Rossel, D. Widmer, Applied Physics Letters 77 (2000) 139–141. [2] J.E. Green, J.W. Choi, A. Boukai, Y. Bunimovich, E. Johnston-Halperin, E. DeIonno, Y. Luo, B.A. Sheriff, K. Xu, Y.S. Shin, H.-R. Tseng, J.F. Stoddart, J.R. Heath, Nature 445 (2007) 414–417. [3] C. Nauenheim, C. Kügeler, A. Rüdiger, R. Waser, A. Flocke, T. G. Noll, NANO ’08, in: Eighth IEEE Conference on Nanotechnology (2008). [4] M. Austin, H. Ge, W. Wu, M. Li, Z. Yu, D. Wasserman, S. Lyon, S. Chou, Applied Physics Letters 84 (2004) 5299–5301. [5] M. Meier, C. Nauenheim, S. Gilles, D. Mayer, C. Kügeler, R. Waser, Microelectronic Engineering 85 (2008) 870–872. [6] M.N. Kozicki, M. Park, M. Mitkova, IEEE Transactions on Nanotechnology 4 (2005) 331–338. [7] C. Schindler, S.C.P. Thermadam, R. Waser, M.N. Kozicki, IEEE Transactions on Electron Devices 54 (2008) 2764–2768. [8] K. Szot, W. Speier, G. Bihlmayer, R. Waser, Nature Materials 5 (2006) 312– 320. [9] S.Q. Liu, N.J. Wu, A. Ignatiev, Applied Physics Letters 76 (2000) 2749–2751. [10] S. Seo, M. Lee, D. Seo, E. Jeoung, D. Suh, Y. Joung, I. Yoo, I. Hwang, S. Kim, I. Byun, J. Kim, J. Choi, B. Park, Applied Physics Letters 85 (2004) 5655– 5657. [11] D.S. Jeong, H. Schroeder, R. Waser, Electrochemical and Solid-State Letters 10 (2007) G51–G53. [12] M. Wuttig, N. Yamada, Nature Materials 6 (2000) 824–832. [13] W.Y. Cho, B.-H. Cho, B.-G. Choi, H.-R. Oh, S. Kang, K.-S. Kim, K.-H. Kim, D.-E. Kim, C.-K. Kwak, H.-G. Byun, Y. Hwang, S. Ahn, G.-H. Koh, G. Jeong, H. Jeong, K. Kim, IEEE Journal of Solid-State Circuits 40 (2005) 293– 300. [14] D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, Nature 453 (2008) 80– 83. [15] J. Mustafa, R. Waser, IEEE Transactions on Nanotechnology 5 (2006) 687– 691. [16] E.H. Sondheimer, Advances in Physics 1 (1952) 1–42. [17] A.F. Mayadas, M. Shatzkes, Physical Review B 1 (1970) 1382–1389. [18] W. Steinhögl, G. Schindler, G. Steinlesberger, M. Traving, M. Engelhardt, International Conference on Simulation of Semiconductor Processes and Devices (2003) 27–30. [19] W. Steinhögl, G. Schindler, G. Steinlesberger, M. Engelhardt, Physical Review B 66 (2002) 075414. [20] G.Q. Zhang, X. Zhang, B.Y. Cao, M. Fujii, K. Takahashi, T. Ikuta, Applied Physics Letters 89 (2006) 114102. [21] X. Zhang, H. Xie, M. Fujii, H. Ago, K. Takahashi, T. Ikuta, H. Abe, T. Shimizu, Applied Physics Letters 86 (2005) 171912. [22] M. Meier, C. Schindler, S. Gilles, R. Rosezin, A. Rüdiger, C. Kügeler, R. Waser, IEEE Electronic Device Letters 30 (2009) 8–10. [23] Q.G. Zhang, B.Y. Cao, X. Zhang, M. Fujii, K. Takahashi, Journal of Physics: Condensed Matter 18 (2006) 7937–7950. [24] W. Steinhögl, G. Schindler, G. Steinlesberger, M. Traving, M. Engelhardt, Journal of Applied Physics 97 (2005) 023706.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Electrical properties of Pt interconnects for passive crossbar memory arrays R. Rosezin a, C. Nauenheim a, S. Trellenkamp b, C. Kügeler a,*, R. Waser a,c,d a
Institut für Festkörperforschung, Forschungszentrum Jülich GmbH, Jülich 52425, Germany Institut für Bio- und Nanosysteme, Forschungszentrum Jülich GmbH, Jülich 52425, Germany Institut für Werkstoffe der Elektrotechnik II, RWTH Aachen, Aachen 52074, Germany d JARA- Fundamentals of Future Information Technology, Germany b c
a r t i c l e
i n f o
Article history: Received 16 December 2008 Received in revised form 6 March 2009 Accepted 7 April 2009 Available online 18 April 2009 Keywords: Nano electrodes Nano crossbar arrays Nano structuring Resistive switching
a b s t r a c t We report on the fabrication and the electrical characterization of platinum interconnects for novel nonvolatile memory technologies. These nanowires present an important and essential contribution to the deep nanometer scaling of alternative architectures beyond CMOS, e.g. nanocrossbar arrays with resistance switching junctions. The nanowires, which have a thickness of 25 nm and a width ranging from 200 nm down to 40 nm, were patterned using electron beam direct writing. They were deposited by UHV electron beam evaporation in combination with a lift-off process. The electrical characteristic is increasingly affected by the contribution of surface effects like scattering at grain boundaries and scattering at the surfaces as the wire dimensions become smaller. With decreasing width of the platinum wire an increasing resistivity was observed, which is consistent with the theories of Fuchs-Sondheimer and Mayadas-Shatzkes. Our studies have shown that the investigated structures possess a high stability concerning the operational current densities up to 4 107 A/cm2, and an additional annealing step results in an improvement of the electrical wire properties, which is explained by a higher quality of the grain boundaries and side walls. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction The pursuit to extend the performance gain of devices in information and communication technology continues according to Moore’s law. With the intention to manage the emerging physical and economical limits, alternative concepts beyond CMOS attract attention. A fundamental approach to build storage devices is the application of resistance switching materials with at least two different, switchable resistance states. These resistances can be interpreted as ‘1’ (low resistance) and ‘0’ (high resistance), whereas intermediate states offer the opportunity of multiple bits per cell, adding up to a higher integration density [1]. To toggle these devices write signals which exceed certain thresholds have to be applied, thus writing or erasing the resistance states. The non-volatile information can be retrieved with a read signal well below these thresholds. The simple configuration of a bottom electrode, the functional material and a top electrode allows for a two terminal device with a high potential for future integration aspects. Crossbar arrays [2,3] create these devices at every junction and are the basis for alternative, inexpensive fabrication processes, e.g. nano-imprint lithography, which additionally offers the suitability for a high throughput [4,5]. Our aim is the investigation of a suitable electrode for a pas* Corresponding author. Tel.: +49 2461 616074; fax: +49 2461 612550. E-mail address: [email protected] (C. Kügeler). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.04.004
sive crossbar array adapted for an adequate resistance switching material. Such material candidates were examined and described numerously during the last decades, including solid electrolytes [6,7], ternary oxides [1,8,9], binary oxides [10,11], and phase change compounds [12,13]. Some promising materials require a combination with an inert electrode or interconnect structure [14]. We performed detailed examinations of platinum interconnects, as this avoids undesirable effects such as oxidizing interfaces with base metals or creation of metallic filaments from diffusive electrode materials like Cu and Ag. The reduction of the conductor thickness and its width into the nanometer region emphasizes ballistic effects in addition to linear dimensional dependencies. As the mean free path of the electrons becomes comparable to the wire size, surface scattering as well as the backscattering at grain boundaries becomes relevant. Both effects increase the resistivity of the platinum and may limit the downscaling of the wire dimensions for real device operation. If the resistance of a single address-wire within an array becomes much larger than the ON resistance of the device, a disproportional high erase voltage has to be applied. However, the value of the erase voltage is technically limited by a specific input signal. Another important design issue concerns the voltage gradient along a single conductor due to its resistance during operation. The voltage drop over the outermost cells in the OFF state has to be higher than the voltage drop over any arbitrarily addressed cell in the ON state including its connecting line as described by Mustafa and
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Waser [15]. Therefore, the size effect on the resistivity might influence the maximum array size. The aim of this work is to show that at low feature sizes the platinum conductors still have a sufficient specific resistivity and are able to endure the necessary current densities. 2. Fabrication The process flow for the fabrication of platinum nanowires is shown in Fig. 1. Here, electron beam lithography is the key process. To obtain a suitable undercut for lift-off, a two layer resist process was employed. In a first step, polymethyl methacrylate methyl acrylic acid (PMMA-MAA) was spun upon the SiO2 surface of a 1 in. sample. After baking for two minutes at 210 °C, a layer of polymethyl methacrylate (PMMA) with a molecular weight of 950 K was spun on top (Fig. 1a). This layer was baked for two minutes at 180 °C. The sample was then patterned with a Leica EBPG 5000 Plus electron beam writer (Fig. 1b) with a dose of 300 lC/cm2. Since the PMMA-MAA has a much higher sensitivity regarding electron than the PMMA, an undercut is produced. After developing in methyl-isobutyl-ketone mixed with isopropyl alcohol for 75 s at room temperature and stopping in isopropyl alcohol (Fig. 1c), a thin adhesion layer of around 5 nm titanium was e-beam evaporated on the patterned sample surface. In situ, the 25 nm thick layer of platinum was then evaporated on top (Fig. 1d). The metallization was performed at room temperature with a background pressure in the range of 107 mbar and a deposition rate below 5 Å s1. The thickness of both layers was monitored using a quartz crystal oscillator. The excess metal on the unexposed e-beam resist was then removed by lift-off in an acetone bath (Fig. 1e). In this case, the titanium underneath the platinum is necessary to provide adhesion to the underlying SiO2. The influence of this layer on the electrical measurement results can be neglected since the layer is very thin. The error introduced is estimated to give values for the resistance which are less than 5% lower, compared to a wire without the adhesion layer. A scanning electron micrograph of a structure with a wire width of 50 nm is shown in Fig. 2. 3. Experimental The electrical characterization of the fabricated structures was conducted by an Agilent B1500A semiconductor device analyzer
Fig. 2. SEM micrograph of a 4-point test structure with a wire width of 50 nm.
in combination with a probe station from Süss Microtec. To study the influence of the wire dimensions on the resistivity, the resistance of various wires with widths ranging from 200 nm down to 40 nm was measured. Fig. 3 shows some exemplary R(I)-traces for different wire widths which were used to extract the resistivity. The wire length of 2 lm and the platinum thickness of 25 nm were kept constant for all samples. To provide comparability for all characterized wires with different width, and to avoid any process dependent variations of the maintained data, all measured structures were fabricated within the very same process flow on one substrate. Tests of several samples were performed, to assure the reproducibility of the obtained results. All measurements were conducted at room temperature. For the interpretation of the electrical measurements, we consider two additional effects that contribute to the basic resistivity of the wire. The first one is a scattering of electrons at the surface of the metal, according to the Fuchs-Sondheimer theory [16], and the second one is grain boundary scattering, as described by the model of Mayadas and Shatzkes [17]. Steinhögl et al. [18,19] combined both models for rectangular copper wires corresponding to Eq. (1):
q 1 1 1 ¼ 2C k0 ð1 pÞ þ þ q0 t w 1 32a þ 3a2 3a3 ln 1 þ a1
Fig. 1. Fabrication process flow for platinum nanowires. (a) Deposition of a double layer resist, (b) Electron beam patterning, (c) Development, (d) Blanket evaporation of Ti and Pt, (e) Lift-off in acetone, (f) final structure.
Fig. 3. Exemplary R (I) traces for different line widths.
ð1Þ
R. Rosezin et al. / Microelectronic Engineering 86 (2009) 2275–2278
2277
In this equation, C = 1.2 is a geometry factor for rectangular wire cross-sections, k0 = 23 nm is the electron mean free path of platinum at room temperature [20] and q0 = 10.5 108 Xm is the bulk resistivity of platinum [21]. The parameters w and t denote the width and the thickness of the wire, respectively. The amount of specular scattering at the walls, modelled by p, can take values ranging from 0 to 1. In the case of p = 1, an entirely specular reflection occurs at the surface, resulting in no additional contribution to the resistivity. The direct opposite is a complete diffuse scattering that results in a maximum contribution to the resistance and which is described by p = 0. Grain boundaries are the microstructural properties of the wire that influence its resistance considerably, if the dimensions of the conductor approach the same order of magnitude as the grain size d. The impact on the resistance is described by the factor a, where
a¼
k0 R : d 1R
ð2Þ
R is the probability of scattering at grain boundaries within the material. If all electrons are scattered at grain boundaries, no conduction can take place and R = 1. By contrast, grain boundaries are not affecting the resistance, if no scattering occurs and R = 0. A simplified visualization of sidewall scattering and grain boundary scattering can be found in Fig. 4. The values of the mean grain size d were gathered from SEM micrographs of the fabricated structures. The diameter in-plane in relation to the charge transfer varies from 6 nm for smaller wires to 15 nm for expanded wires. For the following calculations a linear fit of the acquired grain diameters is used. The measured resistances are normalized to the bulk resistivity and are shown in Fig. 5. The value of the extracted resistivity increases considerably for decreasing wire width. The solid line represents a least squares fit (with an error of 14.4%) to the measurement data. The extracted parameters according to the formula given above are p = 0.48 and R = 0.22. This indicates fairly good microstructural properties and a quite large part of diffuse scattering at the side walls. The error bars shown in both figures are taken from minimum and maximum observed values. Further process and integration steps include a thermal treatment concerning the embedding of the electrodes or the application of the switching material [22]. For this reason, the electrical characteristics of platinum wires were tested after an annealing process of 1 h at 425 °C under nitrogen atmosphere in a Centrotherm rapid thermal annealing furnace, which is within the thermal budget of CMOS processing. The subsequent analysis revealed, as shown in Fig. 6, that the resistivity of the wires was lowered substantially. Calculations using the least squares method give an error of less than 5.5 % with
Fig. 4. Schematic top view of a conductor with simplified description of sidewall and grain boundary scattering.
Fig. 5. Normalized resistivity versus wire width of the as deposited sample. The solid points indicate the values found experimentally, the solid line represents the fit according to the combined model and the dashed line is the bulk value for platinum.
Fig. 6. Normalized resistivity versus wire width of the sample annealed at 425 °C. The solid points indicate the values found experimentally, the solid line represents the fit according to the combined model and the dashed line is the bulk value for platinum.
values of p = 0.74 and R = 0.14, indicating an improved wire quality due to less scattering at the grain boundaries and a more specular sidewall. Compared to the not annealed state, the resistivity in the annealed state is about 30% lower for all data points. Additionally, as-deposited structures were treated at 600 °C for one hour showing a similar improvement in resistivity. Since there was no significant improvement in resistivity compared to the 425 °C process, this annealing temperature is fully sufficient to improve wire quality, ensuring CMOS compatibility with regard to the thermal budget. Also, this provides full availability of the processes and materials typically used to fabricate resistively switching nanocrossbar arrays. No comparable study has been conducted for platinum wires in this range of dimensions. However, some data on platinum nanofilms exists. The existent values for the parameter R range from 0.35 to 0.8 [23], which indicates the good quality of the produced wires within this study. For the sidewall scattering, one could refer to studies on copper where the values for p are in the range between 0.33 and 0.6 [24]. In these studies it has also been pointed out that p and R are strongly correlated. The improvement of the quality due to an annealing step might result from defect healing in the nanowires.
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Additionally, wires were stressed by a current which is considerably higher than those which typically arise during write and erase operations. To estimate the impact on platinum wires in crossbar arrays, a 100 nm wide conductor with a length of several microns was operated with 1 mA for more than 12 h. This corresponds to a current density of 4 107 A/cm2. The resistance stays constant at 9.6 kX without significant changes or a thermo electrical break. This result proves that a conductor can be scaled down to achieve higher integration densities without sacrificing any compatibility with materials and operation modes. However, problems might arise due to an increasing current density as consequence of a decreasing wire cross-section. 4. Summary We have fabricated rectangular platinum nanowires by electron beam lithography and UHV electron beam evaporation with a width down to 40 nm and a constant thickness of 25 nm. The resistance of these wires was characterized by DC-Kelvin probing. An increase in resistivity was found with decreasing wire width which can be explained and modelled by a combination of the Fuchs-Sondheimer and Mayadas-Shatzkes theory. The resistivity of the platinum could be reduced by an annealing step which was carried out under nitrogen atmosphere. This improvement in resistivity was attributed to a better quality of grain boundaries and sidewalls. The increase in wire resistance due to size effects is negligible for a single section of an array if compared to the on/off ratio, which is a few orders of magnitude for typical materials. Therefore, the cell behaviour is still dominated by switching effects. It was shown that the conductors clearly facilitate the typical operating currents which are expected for such materials in future crossbar memory devices. In summary, for the application as conductors in a crossbar array or other nano-sized devices, platinum wires show high potential for future downscaling in face of increasing resistivity with lower line width and occurring limits for the possible size of crossbar arrays. Acknowledgements The authors would like to thank Hans Haselier (IFF) and Hans Wingens (IBN) for the metallization of the samples as well as Prof. Dr. Herbert Schroeder (IFF) for fruitful discussions.
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